JPH02124538A - Active matrix type liquid crystal display device - Google Patents
Active matrix type liquid crystal display deviceInfo
- Publication number
- JPH02124538A JPH02124538A JP63278193A JP27819388A JPH02124538A JP H02124538 A JPH02124538 A JP H02124538A JP 63278193 A JP63278193 A JP 63278193A JP 27819388 A JP27819388 A JP 27819388A JP H02124538 A JPH02124538 A JP H02124538A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- picture element
- write bus
- liquid crystal
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 17
- 239000011159 matrix material Substances 0.000 title claims description 8
- 239000010408 film Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 230000007547 defect Effects 0.000 abstract description 25
- 230000002950 deficient Effects 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 230000007480 spreading Effects 0.000 abstract description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 6
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 6
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 101100214491 Solanum lycopersicum TFT3 gene Proteins 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136268—Switch defects
Abstract
Description
【発明の詳細な説明】
〔概 要〕
アクティブマトリクス型液晶表示装置に関し、エバーオ
フ点欠陥に起因する表示欠陥の拡大を防止することを目
的とし、
絶縁性基板上にマトリクス状に配列された複数個の画素
電極と、該画素電極に対応付けて配置された薄膜トラン
ジスタと、該薄膜トランジスタに選択信号を印加する走
査バスと、前記薄膜トランジスタを介して前記画素電極
に表示データを供給する書き込みバスを有する構成にお
いて、前記画素電極と書き込みバスとを、少なくとも一
方側から導出した接続部により一部オーバラップさせ、
且つこのオーバラップ部に絶縁膜を介在させた構成とす
る。[Detailed Description of the Invention] [Summary] Regarding an active matrix type liquid crystal display device, the purpose of this invention is to prevent the expansion of display defects caused by ever-off point defects, and to prevent the expansion of display defects caused by ever-off point defects. A pixel electrode, a thin film transistor arranged in correspondence with the pixel electrode, a scan bus for applying a selection signal to the thin film transistor, and a write bus for supplying display data to the pixel electrode via the thin film transistor. , the pixel electrode and the write bus are partially overlapped by a connection portion led out from at least one side;
In addition, an insulating film is interposed in this overlap portion.
本発明はアクティブマトリクス型液晶表示装置に関する
。The present invention relates to an active matrix liquid crystal display device.
第3図(a)、 (b)に、従来の薄膜l・ランジスタ
駆動液晶表示装置の構造を模式的に示す。同図(a)に
示すように、薄膜I・ランジスタ(以後TPTと略記す
る)3の制御電極は走査ハスSBに、被制御電極の一方
はデータバスとも呼ぶ書き込みバスWBに、他方は画素
電極已に接続されている。」二記′rFT3は走査パス
SBから選択信号を受けてオンとなり、この時の書き込
みバスWB上の表示データが画素電極に送られ、表示が
行われる。FIGS. 3(a) and 3(b) schematically show the structure of a conventional thin-film transistor-driven liquid crystal display device. As shown in Figure (a), the control electrode of the thin film transistor (hereinafter abbreviated as TPT) 3 is connected to the scanning bus SB, one of the controlled electrodes is connected to the write bus WB, also called a data bus, and the other is connected to the pixel electrode. is connected to 已. 2'rFT3 is turned on upon receiving a selection signal from the scan path SB, and the display data on the write bus WB at this time is sent to the pixel electrodes to perform display.
−F記液晶表示装置の断面構造は、同図(a)のAA矢
視部の断面図である(b)に見られるように、lTO膜
のような透明導電膜からなる画素電極E書き込みハスW
B、配向膜4.および図示はされていないが走査バスS
B、TPT3等をガラス基板1上に形成したTFT基板
Pと、ITO膜等からなる対向電極E′とその上に配向
膜4゛をガラス基板1“−にに形成した対向基板P°間
に、液晶5を挟持する構成を有する。-F The cross-sectional structure of the liquid crystal display device is as shown in (b), which is a cross-sectional view taken along the arrow AA in Fig. W
B. Alignment film 4. and scan bus S, not shown.
B, between a TFT substrate P in which TPT3 etc. are formed on a glass substrate 1, a counter electrode E' made of an ITO film etc. and a counter substrate P° in which an alignment film 4' is formed on a glass substrate 1'- , has a configuration in which the liquid crystal 5 is sandwiched between the two.
かかる構成において、TFT3の断線欠陥等により、常
に書き込みバスWBから絶縁状態に保たれる画素(今後
エバーオフ点欠陥と呼ぶ)の画素電極Eの電位は、それ
を取り囲む周辺の走査ハスSB、書き込みハスWBの電
位で定まる。In this configuration, the potential of the pixel electrode E of a pixel (hereinafter referred to as an ever-off point defect) that is always kept insulated from the write bus WB due to a disconnection defect in the TFT 3, etc. It is determined by the potential of WB.
このようなエバーオフ点欠陥が存在する場合、駆動時間
の経過につれて、このエバーオフ点欠陥の周辺部の光学
状態が変化し、表示欠陥が拡大する現象が生じ、表示品
質を著しく損なっていた。When such an ever-off point defect exists, the optical state around the ever-off point defect changes as driving time passes, causing a phenomenon in which the display defect expands, significantly impairing display quality.
本発明者らは」−記表示欠陥の原因を種々検討の結果、
表示欠陥部では外部からの印加電圧がない時であっても
画素電極Eと対向電極E°間に電位差が存在しており、
そのために外部から正負対称な電圧波形を印加しても液
晶5に加わる電圧は非対称なものになるため、正常な画
素に比べて異なる光学状態を示していることを見出した
。即ちエバーオフ点欠陥部の電荷が周辺の画素に回り込
む結果、周辺部の電位が変化するものと考えられる。As a result of various studies on the causes of the display defects, the present inventors found that
In the display defect area, a potential difference exists between the pixel electrode E and the counter electrode E° even when no voltage is applied from the outside.
Therefore, even if a voltage waveform with positive and negative symmetry is applied from the outside, the voltage applied to the liquid crystal 5 becomes asymmetrical, and it has been found that the pixel exhibits a different optical state compared to a normal pixel. That is, it is considered that the electric charge in the ever-off point defect portion flows around to the surrounding pixels, and as a result, the potential in the peripheral portion changes.
ここでエバーオフ点欠陥部が電荷を持つ理由は次のよう
に解される。エバーオフ点欠陥部の電位は周辺の走査バ
スSBと書き込みハスWBの影宮により定まる。このう
ち、書き込みバスWBには正負対称の電圧が印加されて
いるのに対し、走査バスSBの電位は時間平均しても0
にならない直流成分を持っている。従ってエバーオフ点
欠陥部の電位もまたある直流成分を持つごとになる結果
、液晶5中の電荷がエバーオフ点欠陥部に集まるものと
解される。Here, the reason why the ever-off point defect portion has a charge can be understood as follows. The potential of the ever-off point defective portion is determined by the shadows of the surrounding scan bus SB and write lotus WB. Of these, voltages with positive and negative symmetry are applied to the write bus WB, while the potential of the scan bus SB is 0 even on time average.
It has a DC component that does not Therefore, it is understood that the potential of the ever-off point defect also has a certain DC component, and as a result, the charges in the liquid crystal 5 gather at the ever-off point defect.
本発明はエバーオフ点欠陥に起因する表示欠陥の拡大を
防止することを目的とする。An object of the present invention is to prevent the expansion of display defects caused by ever-off point defects.
本発明は、画素電極と書き込みバスとを、少なくとも一
方側から導出した接続部により一部オーバラップさせ、
且つこのオーバラップ部に絶縁膜を介在させたものであ
る。The present invention partially overlaps the pixel electrode and the write bus by a connection portion led out from at least one side,
Moreover, an insulating film is interposed in this overlap portion.
上記画素電極または書き込みバスより導出された接続部
の対応部位に、例えばレーザビームを照射すると、該接
続部は絶縁膜とともに溶融するこ走により、L下の導電
層つまり画素電極と書き込みバスを電気的に導通状態に
変換できる。When a corresponding part of the connection part led out from the pixel electrode or the write bus is irradiated with a laser beam, for example, the connection part melts together with the insulating film, thereby connecting the conductive layer under L, that is, the pixel electrode and the write bus, with electricity. can be converted into a conductive state.
従ってエバーオフ点欠陥画素を検出した場合には、上述
のようにしてその画素の画素電極を書き込みバスに電気
的に7接続することによって、エバーオフ点欠陥画素の
画素電極の電位を正負対称になるようにすることができ
、上記表示欠陥の拡大を防止することができる。Therefore, when an ever-off point defective pixel is detected, the pixel electrode of that pixel is electrically connected to the write bus as described above, so that the potential of the pixel electrode of the ever-off point defective pixel becomes symmetrical in positive and negative. This makes it possible to prevent the display defects from expanding.
以下本発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図(a)は上記一実施例の一画素分を示す要部平面
図、同図(b)は上記(a)のB−B矢視部の断面図で
ある。FIG. 1(a) is a plan view of a main part showing one pixel of the above-described embodiment, and FIG. 1(b) is a sectional view taken along the line B-B in FIG. 1(a).
本実施例では同図(a)に示す如く、走査ハスSBから
選択信号を受けてTFT3がオンとなり、書き込みバス
WB上の表示データを画素電極Eに送り込む点は従来と
何ら変わりないが、書き込のハスWBの一部をその延長
方向と直交する方向に導出するとともに、この導出され
た延長部11を絶縁膜9により被覆し、かつ画素電極E
をこの絶縁膜9を介して積層形成した点が異なる。ごご
で延長部11の画素電極Eとオーバラップする部分を接
続部8とするる。In this embodiment, as shown in FIG. 5A, the TFT 3 is turned on in response to a selection signal from the scanning bus SB, and the display data on the write bus WB is sent to the pixel electrode E, which is no different from the conventional method. A part of the lotus WB including the lotus WB is led out in a direction perpendicular to its extension direction, and this led out extension part 11 is covered with an insulating film 9, and the pixel electrode E
The difference is that they are formed in layers with this insulating film 9 interposed therebetween. A portion of the extension portion 11 that overlaps the pixel electrode E is defined as a connection portion 8 .
第1図(b)は上記接続部8の断面構造を示し、書き込
みバスWBの延長部11上に絶縁膜9(例えば約110
0nの厚さのSiN膜)を介して画素電極Eが積層され
ている。この接続部8の大きさは、本実施例では約20
μmX20 umとした。なお図示の4は配向膜である
。FIG. 1(b) shows a cross-sectional structure of the connection portion 8, in which an insulating film 9 (for example, approximately 110 mm
A pixel electrode E is laminated via a SiN film (SiN film with a thickness of 0 nm). The size of this connecting portion 8 is approximately 20 mm in this embodiment.
The size was μm×20 um. Note that 4 in the drawing is an alignment film.
書き込みバスWB即ち延長部11は、図示したように、
Cr(クロム)膜12とAffi膜13との積層した膜
を用いた。The write bus WB, that is, the extension part 11, as shown in the figure,
A laminated film of a Cr (chromium) film 12 and an Affi film 13 was used.
以上述べたTFT3.画素電極E、走査ハスSB、書き
込みハスWB、接続部8等は、ガラス基板1−1−に形
成され、TPT基板Pを構成する。TFT3 mentioned above. The pixel electrode E, the scanning lotus SB, the writing lotus WB, the connecting portion 8, and the like are formed on the glass substrate 1-1-, and constitute a TPT substrate P.
TFT3の構造は特に図示はしていないが、動作半導体
層としてa−3i(アモルファスシリコン)層を、ゲー
ト絶縁膜としてSiN膜を用いて、ガラス基板1上に画
素電極Eに対応して、960×240画素分形成した。Although the structure of the TFT 3 is not particularly shown in the figure, a 960-diameter layer is formed on the glass substrate 1 corresponding to the pixel electrode E using an a-3i (amorphous silicon) layer as an active semiconductor layer and a SiN film as a gate insulating film. x240 pixels were formed.
このように形成したTPT基板Pと、前述の対向基板P
′との間に、液晶を充填して液晶表示装置を構成した。The thus formed TPT substrate P and the above-mentioned counter substrate P
'A liquid crystal display device was constructed by filling the space between the two and the liquid crystal.
本実施例では、上記液晶表示装置に全部で6点のエバー
オフ点欠陥が存在したが、このうち任意の3点につき、
画素電極Eと書き込みハスWBとの接続部8にレーザ光
(ビーム径約10μm)を照射して絶縁膜9を破壊し、
上下の画素電極Eと書き込みバスWBとを電気的に接続
した。このパネルをランニング試験にかけたところ、レ
ーザ照射しない3点のエバーオフ点欠陥の周辺には10
時間以内に上記表示欠陥が現れたのに対し、レーザ照射
により画素電極Eと書き込みバスWBとを電気的に接続
した3点には、200時間経過しても表示欠陥の発生は
見られなかった。In this example, there were a total of six ever-off point defects in the liquid crystal display device, and for any three of these,
The connecting portion 8 between the pixel electrode E and the writing lotus WB is irradiated with a laser beam (beam diameter of about 10 μm) to destroy the insulating film 9.
The upper and lower pixel electrodes E and the write bus WB were electrically connected. When this panel was subjected to a running test, it was found that there were 10
While the above display defects appeared within 200 hours, no display defects were observed at the three points where the pixel electrode E and write bus WB were electrically connected by laser irradiation even after 200 hours had passed. .
第2図は本発明の変形例を示す図であって、これは画素
電極Eを一部延長し、この延長部11を接続線を挾んで
書き込みバスWBと対向さセ接続部8とした例である。FIG. 2 is a diagram showing a modification of the present invention, in which a part of the pixel electrode E is extended, and this extension part 11 is arranged as a connection part 8 facing the write bus WB with the connection line in between. It is.
本変形例においても、その効果は前述の一実施例と全く
同じである。The effect of this modification is exactly the same as that of the above-mentioned embodiment.
なお、上記一実施例および変形例の接続部8において、
画素電極Eと書き込みバスWBとの間に介在する絶縁膜
9として、デー1〜絶縁膜と同じ材質の絶縁膜、或いは
配向膜と同じ材質の絶縁膜を使用することが実用上望ま
しい。その理由は、これらの材料は、従来より実際の製
品に使用されている材質であるので、製造工程上および
特性上全く問題を生じるおそれがないことによる。In addition, in the connection part 8 of the above-mentioned embodiment and modification,
As the insulating film 9 interposed between the pixel electrode E and the write bus WB, it is practically desirable to use an insulating film made of the same material as the insulating films from Day 1 to 1, or an insulating film made of the same material as the alignment film. This is because these materials have been conventionally used in actual products, so there is no risk of any problems occurring in the manufacturing process or in terms of properties.
また、上記絶縁膜9としてゲート絶縁膜と同じ材質1例
えばSiN膜を用い、その膜厚をゲート絶縁膜等TPT
部では約3000人、絶縁膜9は約500人とすれば、
エバーオフ点欠陥画素では絶縁膜9に書き込みバスWB
と画素電極Eとの間の電圧約30Vが印加されるのに対
し、正常画素ではTFT3がオン状態では画素電極Eは
書き込みハスWBと同電位であるので、この電圧差を利
用して画素電極Eと書き込みバスWBとを電気的に接続
できる。Further, the insulating film 9 is made of the same material 1 as the gate insulating film, for example, a SiN film, and the film thickness is set to be the same as that of the gate insulating film.
Assuming that there are approximately 3,000 people in the department and approximately 500 people in the insulation film 9,
In the ever-off point defective pixel, the write bus WB is written to the insulating film 9.
A voltage of about 30V is applied between the pixel electrode E and the pixel electrode E. However, in a normal pixel, when the TFT 3 is on, the pixel electrode E has the same potential as the writing lot WB, so this voltage difference is used to connect the pixel electrode E. E and write bus WB can be electrically connected.
即ちSiN膜の絶縁耐圧は、膜厚約500人で凡そ20
V1約3000人で凡そ100■であるので、−[ユ述
したように、ゲート絶縁膜を含むTFT部の絶縁膜の膜
厚を約3000人、接続部8の絶縁膜9の膜厚を約50
0人としておき、すべてのゲート電極に電圧を印加して
TFT3を全部オンとし、すべての書き込みバスWBに
凡そ30Vの交流電圧を印加すれば、接続部8において
絶縁膜9にかかる電圧は、正常画素では上述したように
OVであるので何の変化も生じないが、エバーオフ点欠
陥画素では約30Vの電圧がかかるので、絶縁膜9の絶
縁が破壊され、画素電極Eと書き込みバスWBとが電気
的に接続される。In other words, the dielectric strength voltage of the SiN film is approximately 20
Since V1 is about 3,000 people, it is about 100cm, so - [As mentioned above, the thickness of the insulating film in the TFT section including the gate insulating film is about 3,000 people, and the thickness of the insulating film 9 in the connection part 8 is about 100cm. 50
0, apply voltage to all gate electrodes to turn on all TFTs 3, and apply an AC voltage of approximately 30 V to all write buses WB, the voltage applied to the insulating film 9 at the connection part 8 will be normal. As mentioned above, since the pixel is OV, no change occurs, but since a voltage of about 30V is applied to the ever-off point defective pixel, the insulation of the insulating film 9 is broken, and the pixel electrode E and write bus WB are electrically connected. connected.
このように絶縁膜9の材質とその膜厚を選択することに
より、接続部8における画素電極Eと書き込みバスWB
とを、レーザビーム照射により接続する以外に、電気的
に接続することもできる。By selecting the material and thickness of the insulating film 9 in this way, the pixel electrode E and the write bus WB at the connection part 8 can be
In addition to being connected by laser beam irradiation, they can also be electrically connected.
以上説明した如く本発明によれば、薄膜トランジスタ駆
動液晶表示装置において、エバーオフ点欠陥が存在した
場合でも周辺画素に広がる表示欠陥の発生を防ぐことが
できる。As described above, according to the present invention, even if an ever-off point defect exists in a thin film transistor-driven liquid crystal display device, it is possible to prevent the display defect from spreading to peripheral pixels.
第1図(a)、 (b)は本発明一実施例の構成説明図
、第2図は本発明の詳細な説明図、
第3図(a)、 (b)は従来の問題点説明図である。
図において、■、1°はガラス基板、3はTPT(Fi
膜トランジスタL4,4”は配向膜、5は液晶、8は接
続部、9は絶縁膜、SBは走査ハス、WBは書き込みバ
ス、Eは画素電極を示す。Figures 1 (a) and (b) are diagrams explaining the configuration of one embodiment of the present invention, Figure 2 is a detailed diagram explaining the present invention, and Figures 3 (a) and (b) are diagrams explaining the problems of the conventional technology. It is. In the figure, ■, 1° is a glass substrate, 3 is TPT (Fi
Film transistor L4, 4'' is an alignment film, 5 is a liquid crystal, 8 is a connecting portion, 9 is an insulating film, SB is a scanning bus, WB is a write bus, and E is a pixel electrode.
Claims (3)
複数個の画素電極(E)と、該画素電極に対応付けて配
置された薄膜トランジスタ(3)と、該薄膜トランジス
タに選択信号を印加する走査バス(SB)と、前記薄膜
トランジスタを介して前記画素電極(E)に表示データ
を供給する書き込みバス(WB)を有する構成において
、 前記画素電極(E)と書き込みバス(WB)とを、少
なくとも一方側から導出した接続部(8)により一部オ
ーバラップさせ、且つこのオーバラップ部に絶縁膜(9
)を介在させたことを特徴とするアクティブマトリクス
型液晶表示装置。(1) A plurality of pixel electrodes (E) arranged in a matrix on an insulating substrate (1), thin film transistors (3) arranged in correspondence with the pixel electrodes, and a selection signal applied to the thin film transistors. In the configuration, the pixel electrode (E) and the write bus (WB) are connected to the pixel electrode (E), and the write bus (WB) supplies display data to the pixel electrode (E) via the thin film transistor. The connection part (8) led out from at least one side overlaps the part, and the insulating film (9) is formed in this overlap part.
) is used as an active matrix liquid crystal display device.
)のゲート絶縁膜(2)と同一材質の絶縁膜であること
を特徴とする請求項1記載のアクティブマトリクス型液
晶表示装置。(2) The insulating film (9) is connected to the thin film transistor (3).
2. The active matrix liquid crystal display device according to claim 1, wherein the insulating film is made of the same material as the gate insulating film (2) of the active matrix type liquid crystal display device.
絶縁膜であることを特徴とする請求項1記載のアクティ
ブマトリクス型液晶表示装置。(3) The active matrix liquid crystal display device according to claim 1, wherein the insulating film (9) is an insulating film made of the same material as the alignment film (4).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63278193A JPH02124538A (en) | 1988-11-02 | 1988-11-02 | Active matrix type liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63278193A JPH02124538A (en) | 1988-11-02 | 1988-11-02 | Active matrix type liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02124538A true JPH02124538A (en) | 1990-05-11 |
Family
ID=17593890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63278193A Pending JPH02124538A (en) | 1988-11-02 | 1988-11-02 | Active matrix type liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02124538A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0461417A2 (en) * | 1990-05-16 | 1991-12-18 | Hosiden Corporation | Liquid crystal display element and method for treating defective pixels therein |
JPH0416930A (en) * | 1990-05-11 | 1992-01-21 | Sharp Corp | Active matrix type display device |
JPH0419618A (en) * | 1990-05-14 | 1992-01-23 | Sharp Corp | Production of active matrix type display device |
EP0512840A2 (en) * | 1991-05-08 | 1992-11-11 | Sharp Kabushiki Kaisha | An active matrix display device |
WO1996007122A1 (en) * | 1994-08-30 | 1996-03-07 | Hitachi, Ltd. | Method of production of active matrix type liquid crystal display device |
JP2007256919A (en) * | 2006-03-23 | 2007-10-04 | Genta Kagi Kogyo Kofun Yugenkoshi | Electronic ink display device and method for repairing the same |
-
1988
- 1988-11-02 JP JP63278193A patent/JPH02124538A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0416930A (en) * | 1990-05-11 | 1992-01-21 | Sharp Corp | Active matrix type display device |
JPH0419618A (en) * | 1990-05-14 | 1992-01-23 | Sharp Corp | Production of active matrix type display device |
EP0461417A2 (en) * | 1990-05-16 | 1991-12-18 | Hosiden Corporation | Liquid crystal display element and method for treating defective pixels therein |
EP0512840A2 (en) * | 1991-05-08 | 1992-11-11 | Sharp Kabushiki Kaisha | An active matrix display device |
US5434686A (en) * | 1991-05-08 | 1995-07-18 | Sharp Kabushiki Kaisha | Active matrix display device |
WO1996007122A1 (en) * | 1994-08-30 | 1996-03-07 | Hitachi, Ltd. | Method of production of active matrix type liquid crystal display device |
JP2007256919A (en) * | 2006-03-23 | 2007-10-04 | Genta Kagi Kogyo Kofun Yugenkoshi | Electronic ink display device and method for repairing the same |
JP4515466B2 (en) * | 2006-03-23 | 2010-07-28 | 元太科技工業股▲分▼有限公司 | Electronic ink display device and repair method thereof |
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