JPH02123843A - Delay insertion and removal system - Google Patents

Abstract

PURPOSE:To make the size of the device small by using a phase difference of 180 deg. between an odd number order pulse and an even order number pulse so as to write a write reset pulse into an elastic memory thereby applying delay insertion removal of a transmission data. CONSTITUTION:A monitor circuit 22 switches a write reset pulse extracted by a frequency division circuit 20 between a pulse of an odd number order and an even order number when a phase difference between a write reset pulse and a read reset pulse reaches a prescribed value or below. The system consists of a frame synchronization and clock extraction circuit 11, the frequency divider circuit 20, an elastic memory 21 and the monitor circuit 22 and only the frequency divider circuit 20 is enough in place of a delay circuit and a selector in a conventional system, and then the quantity of the hardware is reduced.

Description

[Detailed Description of the Invention] [Regarding the delay insertion/extraction method for performing delay insertion/extraction of transmission data supplied to the elastic memory of a synchronous terminal device, the hardware complexity is reduced compared to the conventional one, and the size is reduced to 1ilN. In a delay insertion/removal method that performs delay insertion/removal of transmission data supplied to the elastic memory of a synchronous terminal device,
A frame synchronization and clock extraction circuit that extracts transmission data, a frame pulse, and a clock from a transmission signal coming from a transmission line, and a write reset pulse that extracts either an odd-numbered pulse or an even-numbered pulse of the frame pulse. A frequency divider circuit that outputs the output data as a clock, and a write reset pulse that resets the write address, and a frame synchronization and output clock extraction circuit that uses the output clock as a write clock to change the write address and write the transmission data. an elastic memory that resets a read address with a read reset pulse supplied from inside the terminal station 8 device and reads data by changing the read address with a read clock supplied from inside the synchronous terminal station wttaff; a monitoring circuit that switches the write reset pulse taken out by the frequency dividing circuit between the odd-numbered pulse and the even-numbered pulse when the phase difference between the write reset pulse and the read reset pulse becomes a predetermined value (iQ or more); and is configured to perform delayed insertion/removal of transmission data stored in the elastic memory using the 180 degree phase difference between the write reset pulse and the odd numbered pulse and the even numbered pulse. do.

(Field of Application on Jiffi) The present invention relates to a delay insertion/removal method, and pertains to a delay insertion/removal method for performing delay insertion/removal on transmission data supplied to the elastic memory of the synchronous terminal vR1a.

At the synchronous terminal *e, jitter and wander in the transmission path are removed,
Elastic memory is used to match the transmitted signal with the frequency and phase within the device.

Elastic memory can be controlled separately by being given separate clocks and resets for writing and reading, and performs sequential reading and sequential writing. This allows for speed conversion between writing and reading transmission data in transmission signals. It is necessary to provide a write-inhibited area or a read-inhibited area to prevent written transmission data from disappearing before it is read out. If an attempt is made to write transmission data into this write-protected area, a delay is inserted or explained to avoid writing to the write-protected area.

[Conventional technology]

FIG. 4 shows a block diagram of an example of a conventional delay insertion/extraction method.

In the figure, the transmission signal input from the transmission l110 is supplied to a frame synchronization and clock extraction circuit, where the frame synchronization signal is detected from the transmission signal to generate a frame pulse FP, and the transmission data (DATA) and clock (
CLK) are extracted. The frame pulse and transmission data are supplied to the d delay circuit 1112 and the selector (SEL) 13, and the clock is supplied to the delay circuit 12 and is supplied as a write clock (WCLK) to the elastic memory (ES) 14.

The delay circuit 12 has a delay m (for example, several tens of bits) that is sufficient to prevent delay insertion/removal from occurring again once delay insertion/removal occurs,
The frame pulse and data are shifted and delayed by a clock and then supplied to the selector 13. The selector 13 is a frame synchronization and clock extraction circuit 11 or a delay circuit 12
Data and frame pulses supplied by either are selected and taken out and transferred to the elastic memory (DA
TAIN) and write reset pulse (WR>).

The elastic memory 14 has its write address reset by a write reset pulse, and writes data by incrementing the write address each time a write clock is supplied. Also, a read reset pulse is supplied from inside the device via a terminal 16. After resetting the read address with a pulse (RR), the read address is incremented every time a read clock (RCLK) is supplied from inside the device via the terminal 17, and the data is output as data (DATAOUT).
is supplied to the inside of the @box through the readout terminal 18.

Surveillance [11815 is II! 4. Generate a positive write inhibit pulse as shown in Figure (C) from a negative read reset pulse as shown in Figure (B), and a positive write reset pulse as shown in Figure (A) to inhibit writing. When the pulse enters the H level period, it generates a switching control signal and selector 1
3, switches the data and frame pulse selection of the selector 13, inserts a delay (selection of the data and frame pulse of the output of the 1 extension path 12), or inserts a delay (selection of the data and frame pulse of the output of the frame synchronization and clock extraction circuit 11). data and frame pulse selection).

(A! Problem to be solved by the invention) Frame II and clock extraction circuit 11 shown in FIG.
．． ! ! Extension circuit 12. Selector 13. The elastic memory 14 and the monitoring circuit 15 are required for one transmission line 10ffl, which requires a large amount of hardware, and the number of transmission lines connected to the same 11 terminal equipment is usually multiple (for example, 8), so the amount of hardware is small. There was a @thesis that 1aIl will increase in size and 1aIl will become larger.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a rolling and sharpening method in which the amount of hardware is reduced compared to the conventional method, and the device can be downsized.

(Means for Solving Problem A) FIG. 1 shows a block diagram of the principle of the delayed insertion/extraction method of the present invention. In Figure Ia1, the same parts as in Figure 4 are given the same symbols,
The explanation will be omitted.

In FIG. 1, frame synchronization and clock extraction circuit 1
1 extracts transmission data, frame pulses, and signals from the transmission signal coming from the transmission path.

The frequency dividing circuit 20 extracts either the odd-numbered pulse or the even-numbered pulse of the frame pulse and outputs it as a write reset pulse.

Elastic memory (ES) 21 has 2 frames and 1n
It has a memory capacity sufficient to write the transmission data for 1 minute, and the write address is reset by the write reset pulse, and the clock from the frame synchronization and clock extraction circuit 11 is used as the self-written clock, and the write address is changed and transmitted. Write data, reset the read address using the read reset pulse supplied from the inside of the II terminal station i* via the terminal 16, and read the read clock supplied from the inside of the synchronous terminal unit via the terminal 17. The data is read by changing the read address at terminal 18.
The signal is supplied to the inside of the synchronous terminal j1 device.

The monitoring circuit 22 outputs a pulse to the write reseller which is taken out by the frequency dividing circuit 20 when the phase difference between the write reset pulse and the read reset pulse becomes equal to or less than a predetermined value. Switch.

(Function) The system of the present invention is composed of a frame WIII, a clock extraction circuit 11, a frequency dividing circuit 20, an elastic memory 21, and a monitoring circuit 22, and the frequency dividing circuit replaces the delay circuit 12 and selector 13 of the conventional system. Only 20 is required, which reduces the amount of hardware.

(Embodiment) FIG. 2 shows a circuit diagram of an embodiment of the frequency dividing circuit 20 and the monitoring circuit.

In the figure, the frame pulse (as shown in FIG. 3A) output from the frame synchronization and clock extraction circuit 11 is connected to the terminal 29.
FP) is input to the clock input terminal of the JK type rough flip-flop 30 in the frequency divider circuit 20 and one input terminal of the NAND circuit 31 and 32. flip 70 tube 3
0 has the J input terminal and the input terminal fixed at the H level, and operates as a T-type flip-flop to divide the frequency of the frame pulse into 1/2. Flip Flop 30 Q
The terminal output is supplied to the other input terminal of the NAND circuit 31, and the σ terminal output whose phase is 180[IIJ'l with respect to the Q terminal output is supplied to the other input terminal of the NAND circuit 32.

As a result, the NAND circuit 31 extracts, for example, only odd-numbered frame pulses from the frame pulses input to the terminal 29, the NAND circuit 1i32 extracts only even-numbered pulses, and the pulses output from each of the NAND circuits 31 and 32 are sent to the selector. (S
EL) 33. The output pulse of the NAND circuit 31 or 32 selected and taken out by the selector 33 (Fig. 3(B)
The pulse shown in FIG. 1) is supplied to the elastic memory 21 from the terminal 34 as a write reset pulse (WR>), and is also supplied to the inverter 35 of the monitoring n-path 22.

The monitoring channel 22 is connected to the terminal 36 from inside the device as shown in FIG.
) is supplied with a read reset pulse (RR) as shown in FIG. The read reset pulse is supplied to a write inhibit pulse generator 37, where a write inhibit pulse (PC) shown in FIG. 3(D) is generated and supplied to one input terminal of an ANDRO path 38. A write reset pulse of positive polarity inverted by the inverter 35 is supplied to the input terminal of the AND circuit 38, and the AND circuit 38 receives a write reset pulse of positive polarity during the H level period of the write inhibit pulse. Take this out as a trigger pulse
It is supplied to the clock input terminal of the K-type flip-flop 39.

The flip-flop 39 operates as a T-type flip-flop with its J input terminal and input terminal fixed at the torque level, and when a trigger pulse is supplied from the AND circuit 38, the output level of its Qll child is switched. This Q terminal output is supplied as a switching control signal to the selector 33, and the selector 33 selects the NAND circuit 31 output when the switching control signal is at the torbel level, and selects the NAND circuit 32 output when the switching control signal is at L level.

The pulses output from each of the NAND inner paths 31 and 32 have a 180 degree phase difference, and by switching the level of the switching control signal, the phase of the write reset pulse output from the terminal 34 changes by 180 rR, and the elastic memory 21 Delay of transmission data written to Mll! I2 is performed.

(Effects of the Invention As described above, according to the delay insertion/removal method of the present invention, the amount of hardware for a single transmission line is reduced compared to the conventional method, and the synchronous terminal B to which multiple transmission lines are connected is The total amount of hardware in the installation is greatly reduced, making it possible to downsize the device and reduce costs, making it extremely useful.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the system of the present invention, Fig. 2 is a circuit diagram of an embodiment of the four branch stations and the monitoring U path, and Fig. 3 is the I! No. Timing Chi! -G, 4th
The figure is a block diagram of an example of a conventional system, and FIG. 5 is a signal timing chart of the section shown in FIG. In the figure, 10 is a transmission path, 11 is a frame synchronization and link extraction a path, 20 is a branch four path, 21 is an elastic memory, and 22 is a monitoring n path.

Claims (1)

[Claims] In a delay insertion/extraction method that performs delay insertion/extraction for transmission data supplied to an elastic memory (21) of a synchronous terminal device, transmission data, frame pulses, and clocks are extracted from a transmission signal coming from a transmission path. a frame synchronization and clock extraction circuit (11) that extracts each of the frame pulses; a frequency dividing circuit (20) that extracts either the odd-numbered pulse or the even-numbered pulse of the frame pulse and outputs it as a write reset pulse; and the write reset pulse. The write address is reset with a pulse, the write address is changed using the clock from the frame synchronization and clock extraction circuit (11) as the write clock, the transmission data is written, and the read reset pulse is supplied from inside the synchronous terminal device. an elastic memory (21) that resets a read address with a read address and reads data by changing the read address with a read clock supplied from inside the synchronous terminal device; and the write reset pulse and the read reset pulse. a monitoring circuit (22) that switches the write reset pulse taken out by the frequency dividing circuit (20) between the odd-numbered pulse and the even-numbered pulse when the phase difference of , performing delayed insertion/extraction of transmission data written in the elastic memory (21) by using a 180 degree phase difference between the write reset pulse and the odd numbered pulse and the even numbered pulse. Delayed insertion/removal method.