JPH02123641U - - Google Patents
Info
- Publication number
- JPH02123641U JPH02123641U JP3059089U JP3059089U JPH02123641U JP H02123641 U JPH02123641 U JP H02123641U JP 3059089 U JP3059089 U JP 3059089U JP 3059089 U JP3059089 U JP 3059089U JP H02123641 U JPH02123641 U JP H02123641U
- Authority
- JP
- Japan
- Prior art keywords
- section
- memory
- refresh
- abnormality detection
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Dram (AREA)
Description
第１図は本考案によるリフレツシユ異常検出用
ボードの一実施例を示す系統図、第２図はその動
作を説明するためのフローチヤート、第３図はア
ドレスとデータの流れを示す説明図、第４図はリ
フレツシユ異常検出のフローチヤートである。
１……インタフエース部、２……メモリ部、３
……リフレツシユ異常検出部、３ａ……ＬＥＤ、
４……外部インタフエース部、５……強制リード
用信号生成部、６，７……ラツチ。
FIG. 1 is a system diagram showing an embodiment of the refresh abnormality detection board according to the present invention, FIG. 2 is a flowchart for explaining its operation, FIG. 3 is an explanatory diagram showing the flow of addresses and data, and FIG. Figure 4 is a flowchart of refreshing abnormality detection. 1...Interface section, 2...Memory section, 3
...Refresh abnormality detection section, 3a...LED,
4... External interface unit, 5... Forced read signal generation unit, 6, 7... Latch.
Claims (1)
エースを行なうインタフエース部と、前記本体の
メモリと同一容量のメモリを有するメモリ部と、
リフレツシユ異常を検出するリフレツシユ異常検
出部と、前記メモリ部を監視するための外部イン
タフエース部とを備えたリフレツシユ異常検出用
ボード。 an interface section for interfacing with a main body such as a personal computer; a memory section having a memory having the same capacity as the memory of the main body;
A refresh abnormality detection board comprising a refresh abnormality detection section for detecting a refresh abnormality, and an external interface section for monitoring the memory section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3059089U JPH02123641U (en) | 1989-03-17 | 1989-03-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3059089U JPH02123641U (en) | 1989-03-17 | 1989-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123641U true JPH02123641U (en) | 1990-10-11 |
Family
ID=31255781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3059089U Pending JPH02123641U (en) | 1989-03-17 | 1989-03-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123641U (en) |
-
1989
- 1989-03-17 JP JP3059089U patent/JPH02123641U/ja active Pending
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