JPH02123440A - Buffer storage device - Google Patents

Abstract

PURPOSE:To effectively utilize the data of an entry held at a multi-hit state by reading out address data from a main storage device at the time of detecting parity errors in all data respectively read out from plural storage areas. CONSTITUTION:A multi-hit detecting counter 7 detects multi-hit states from address tag comparators 5a, 5b, outputs the detected result to a data source selector 8, counts up the number of times of detection, and outputs a mulit-hit interruption signal 113. The selector 8 decides the validity of the data, outputs decided results to valid bit memories 3a, 3b and outputs also a way selecting signal 112 to a way selector 9. In addition, the selector 8 forms and outputs a main storage access instruction 114 in accordance with the data validity deciding result. The selector 9 selects one of block data inputted from data memories 4a, 4b inputted through data parity checkers 6a, 6b in accordance with the signal 112 and transfers read data 115 to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer storage device, and more particularly to a buffer storage device that is disposed between a central processing unit and a main storage device and is capable of high-speed access to the central processing unit.

Conventionally, in this type of buffer storage device, if the contents of the same address are stored in multiple entries, if a multi-hit state is detected during a read operation to that address, it will be treated as an error within the device. At the same time, the corresponding entry is cleared unconditionally and switched to bypass mode, allowing direct access to the main memory.

After that, an interrupt was generated to the software as a multi-hit error, and the interrupt processing was executed.

In such a conventional buffer storage device, Marzihi, ・1・
When the condition is detected, the data in the device is checked 1-2) and the cribbing is performed on the 1''1!1,
Then t')! (-Because the Liakuhi people have direct access to the above-mentioned Sui bag side 6, the speed of the raccoon epidemic decreases rapidly.) There is a point X.

Also, Mano L, = 71, 1~state (,, 2, tt, etc.) is valid for the probability that 1 is stored. Who can't make effective use of the gain to -fl- by clearing -n'1:, 1. ', -i, or there is.

Furthermore, after the rough 1-Uko, γ-＼ interrupt, the instruction will be re-executed, or an error will be displayed and the system will become an idiot. The disadvantage is that a large number of steps are required for recovery if the

The present invention eliminates the drawbacks of the conventional ones as described above. We aim to provide a buffer storage device that can effectively utilize the data of the mano [nahi l-state] l' knee one-point without incurring a negative slowdown in processing speed. shall be.

The buffer memory/unique device 6” according to the present invention stores the data in the above-mentioned fault bag surface and transfers it to the medium-heat barrel processing device according to the above-mentioned number. - a buffer storage device having a plurality of memory ffi areas for sending gate data to the central processing unit, wherein one data of the same address is stored in the plural memory/pupil areas; 1111, a detection means for detecting a state in the first stage, and a plurality of parity check means for detecting a parity cooler of data from each of the plurality of registers. When a state is detected in the multi-layer 1, one of the data read from each of the plurality of storage areas is selected according to the detection results of the plurality of parity check means. When the pariday error is detected in all of the data read from the sending means for sending to the processing device and each of the plurality of storage areas, the corresponding node I of the main storage device is sent.
The device is characterized in that it has a reading means for reading out the data of the bus.

1 Example Next, an embodiment of the present invention will be described with reference to the drawings.8 Figure 1 shows the configuration of an embodiment of the present invention. -72
It is a diagram. In the figure, the address tough register 1 stores the tough part information of the address requested by the central processing unit Z: (1; 24 not shown); the address tough memory 2a; 2b has data memory 1d
, 11) Attachment of the program data stored in
The female 9th part is accommodated, and the valid part).
Memories 3a, 3b have data memory 1a1.
1t] bit information indicating the validity of the block gater stored in the address tough memories 2a, 2b 8i
It is accommodated in a 9-5cm space corresponding to the 9th part of the female body.

Ato1. The stuff comparators 5a, 5b are respectively address tough 1. The address tag 100 sold by Sister J and the address 9ri 101, 102 sold from Atto I/stack memory 2a, 2b are compared, and those addresses
, Susuri h-When it matches, Hee Sol ~ Iha No. 103
104 is output to the multi-hit detection counter 7 and the gator source selector 8.

The data parity checkers 6a, 6l) are read from the data memories 4a, 4b and block data 1 is read out from the data memories 4a, 4b.
10111 is performed, and the check results are output to the data source selector 8 as data parity signals 108 and 109.

In the buffer storage device according to the embodiment of the present invention, the memory section is composed of two sub-memory sections (ways), including address tag comparators 5a, 5b and data parity checkers 6;, 1. ．． 6b is placed in the way contest position.

The multi-hit detection counter 7 is an address tag comparator 5a.
A multi-hit state is detected by the hit signals 103 and 104 from 5b, and the detection result is sent to the multi-hit
It outputs a signal 105 to the data source selector 8, counts the number of times the multi-hit state has been detected, and outputs a multi-hit interrupt signal 113 indicating that the multi-hit state has occurred multiple times.

Data source selector 8 is address tag comparator 5a, 5
hit signals 103, 104 from data parity checkers 6a, 6b, and data parity signals 108, 108 from data parity checkers 6a, 6b.
109 and the multi-hit signal 105 from the multi-hit detection counter 7, valid pit invalidation signals 106 and 107 are output to the valid bit memories 3a and 3b, and a data way selection signal 112 is output. is output to the way selector 9. Furthermore, it generates and outputs a main memory access instruction 114 according to the determination result of data validity.

The way selector 9 selects the data memories 4a, 4 input via the data parity checkers 6a, 6b in accordance with the way selection signal 112 from the data source selector 8.
One (way) of the block data from b is selected and the block data is transferred as read data 115 to the central processing unit.

Next, the operation of one embodiment of the present invention will be explained using FIG.

When a memory access instruction is output from the central processing unit,
The tag part information of the requested address is set in the address tag register 1, and is compared with the address tag in the address tag memories 2a, 2b in the address tag comparators 5a, 5b.

If a match (hit) of these address tags is detected in either of the address tag comparators 5a and 5b,
Block data is read from the data memories 4a, 4b corresponding to the address tag memories 2a, 2b containing address tags for which a match has been detected and transferred to the central processing unit.

However, if address tag comparators 5a and 5b simultaneously detect address tag matching and multi-hit detection counter 7 detects a multi-hit state,
Block data is read from both data memories 4a and 4b, and data parity checker 6a is applied to these block data.

6b performs a parity check.

At this time, if the data parity checkers 6a, 6b detect parity errors in the block data from the data memories 4a, 4b, the valid bits of the valid memories 3a, 3b corresponding to the block data in which the parity errors have been detected are detected. are reset by valid bit invalidation signals 106 and 107 from data source selector 8.

When the multi-hit detection counter 7 detects a multi-hit state and the data parity checker 6a6b detects a parity error in both the block data from the data memories 4a and 4b, the data source selector 8 detects the valid parity of the valid memories 3a and 3b. It resets the pit and outputs a main memory access instruction 114 to reload data in blocks from the main memory (not shown).

Furthermore, even if the multi-hit detection counter 7 detects a multi-hit state, the data parity checkers 6a, 6
When it is detected that parity is incorrect in only one of the data source selectors b, the data source selector 8 sends a way selection signal 112 to the way selector 9 so that the data parity checkers 6a and 6b select the block data for which parity is not detected to be incorrect. Output. Therefore, way selector 9
Then, the data parity checkers 6a and 6b select the block data in which no parity error has been detected and transfer it to the central processing unit as read data 115.

Furthermore, even if a multi-hit state is detected by the multi-hit detection counter 7, the data parity checker 6a,
When no parity error is detected in 6b, the way selection signal 112 is activated so that the data source selector 8 compares the data in the main storage device with the block data from the data memories 4a and 4b and selects the correct block data. is output to the way selector 9.

When it is determined that both block data from the data memories 4a and 4b are correct through this comparison, a way selection signal 112 is sent from the data source selector 8 to the way selector 9 so that any block data among these block data is selected. The block data is selected by the way selector 9 and transferred to the central processing unit as read data 115.

Through the above-described processing, when the multi-hit detection counter 7 first detects the number and is in the zero-hit state, the data is determined to be incorrect.1. transfer the data to a central processing unit or
When the detection counter 7 detects the multi-shot state multiple times, the interrupt signal 113 is output from the detection counter 7 to the multi-shot 1, since the subsequent operation of the device is in question. Multi-hit interrupt signal 1
13, software processing is performed.

In this way, when the multi-history = detection power T is detected by the multi-tap 11 state, the data source 71. The data memory ia, 4 is controlled by the controller 8.
Data parity checker 6 (i
, , (') When a parity error is detected in (b), the corresponding data in the storage device is set to 1 without being reloaded. Be able to effectively utilize the data in the buffer storage device that you were focusing on at times.

As a result, when a multi-hit state is first detected by the multi-hit detection counter 7, all processing is performed in hardware without generating an interrupt to the software, and the multi-hit state is detected only when the multi-hit state is detected multiple times. Multi-hyphen 1 from detection counter 7
Rough 1 in the interrupt routine in response to the interrupt signal 113
- It becomes possible to perform software processing.

Furthermore, even if the multi-hirer I/detection counter 7 detects the state of the multi-hiller 1, there is no need to bypass the buffer storage device or re-execute the command.
Data processing can be performed without reducing processing speed due to bypass processing or re-execution of instructions.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, a plurality of storage areas respectively store data in the main memory and send the data to the central processing unit in response to an add/s signal from the central processing unit. If a multi-shut state is detected indicating that data at the same address is stored in the multiple storage areas, the data from each storage area is -1: When a parity error is detected in all the data read from each of these multiple storage areas when one of the ~gators is sent to the central processing unit, the data at the corresponding address in the storage device will not be read. By doing so, even if a multi-hit state is detected, the data of the engine in the multi-hit state can be effectively used without reducing the processing speed due to bypass processing or instruction re-execution. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1 Explanation of codes for important parts 2a, 2b... Address tough memory 1a4.
11]...Gator Memory a 6a. 51) Address tag comparator 6 b...
...Data parity checker 7...Multi-hirer 1 to detection counter 8...Data source selector 9...Way selector

Claims (1)

[Claims] (1) A buffer storage device having a plurality of storage areas each storing data in a main storage device and transmitting the data to the central processing unit in response to an address signal from the central processing unit, a detection means for detecting a multi-hit state indicating that data at the same address is stored in a storage area; a plurality of parity check means for detecting a parity error in data from each of the plurality of storage areas; When the multi-hit state is detected by the detection means, one of the data read from each of the plurality of storage areas is sent to the central processing unit according to the detection result of each of the plurality of parity check means. A buffer comprising: a sending means; and a reading means for reading data at a corresponding address of the main storage device when the parity error is detected in all the data read from each of the plurality of storage areas. Storage device.