JPH04248644A - Cache memory control circuit - Google Patents

Abstract

PURPOSE:To eliminate the need of a microprogram for initialization to quickly perform initialization by providing a validity indicating register which is invalidated at the time of initialization, a detection suppressing means which suppresses hit detection with respect to an invalidated compartment, a block load means, and a validity indication update means. CONSTITUTION:Validity indicating registers 1-13 to 1-16 indicating whether respective compartments are effective or not are '0' to indicate that compartments are ineffective, but they are '1' to indicate that compartments are effective. If validity indicating registers 1-13 to 1-16 are '0' at the time of cache indexing, outputs of AND gates 1-21 to 1-24 go to '0' unconditionally, and the output of a NOR gate 1-25 goes to '1', and erroneous hit detection is suppressed. Meanwhile, a block load control part 1-33 performs relief at the time of block load if registered compartments are invalidated by contents of validity indicating registers 1-13 to 1-16.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a cache memory used in an information processing apparatus.

0002

[Prior Art] Conventionally, in the control of cache memory,
In particular, the initialization of the cache memory is controlled by providing means for writing arbitrary data into the cache memory using a microprogram, and by using the microprogram to write "0" to the valid bits of all words in all compartments.

[0003] In another method, by instructing initialization of the cache memory using a microprogram, hardware generates all patterns of cache memory addresses and writes "0" to the valid bits of all compartments. This is done by

0004

[Problems to be Solved by the Invention] In the conventional cache memory control circuit described above, when a microprogram writes one word at a time, hardware is required to write data to the cache memory from the microprogram, and furthermore, it requires initialization. The problem is that it takes too much time.

[0005]Also, in the case of a circuit in which all address patterns are generated by hardware according to instructions from a microprogram, it takes less time compared to a circuit in which the microprogram writes one word at a time; There is a problem in that the next process cannot proceed until the writing is completed.

[0006] The increase in initialization time not only increases the initialization time of the information processing device, but also makes it difficult to temporarily stop processing and collect failure information when a failure occurs, such as in recent pipeline processing information processing devices. If the cache memory is then initialized and retried for the failed process, the retry time will increase, which may affect other normal devices as well.

Furthermore, since the cache memory is invalidated by initialization, there is a problem that it takes time to bring out the original performance of the cache.

[0008]

[Means for Solving the Problems] The cache memory control circuit of the present invention includes a validity display register that indicates validity/invalidity of the memory contents of each compartment and is invalidated at the time of initialization, and a cache memory index. hit detection suppressing means for suppressing hit detection regardless of read contents for compartments that are invalidated by the contents of the validity display register; block loading means for performing block loading on all words of the compartment, and content indicating that the contents of the compartment are valid by changing the contents of the validity display register when the loading of all blocks is completed. The invention is characterized by having a validity display updating means for updating the validity display.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an address array section in a case where the number of compartments of a cache memory is four, showing one embodiment of the present invention. It should be noted that the data array section is not particularly illustrated because it has no difference from the conventional configuration.

In the figure, 1-1 to 1-4 are respective compartments of an address array constituting the cache memory, and the address array stores the upper bits of addresses registered in the cache memory and the valid bits of each word. It's memory.

1-5 to 1-8 and 1-9 to 1-12 are
A data register and a validity bit register each store the upper bits and valid bits of the registered address among the data read from the address array memories 1-1 to 1-4.

1-13 to 1-16 are validity display registers that indicate whether each compartment is valid or invalid, which is one feature of the present invention; if the content of this register is "0", the compartment is Invalid, “1” indicates valid.

1-17 to 1-20 are data registers 1-
a comparator 1-21 that compares the contents of 5 to 1-8 with the contents of the cache index upper address register 1-28;
1-24 are AND gates, and 1-25 are NOR gates. If the output of NOR gate 1-25 is “0”,
Indicates a cache memory hit.

1-26 to 1-28 are a cache index upper address register, a cache index lower address register, and a cache registration address register, respectively, 1-29 and 1-30 are selectors, and 1-31 is a cache index lower address register. Comparator 1-32 for comparing register 1-27 and cache registration address register 1-28
is a counter that increments the contents of the cache registration address register 1-28 by one.

Reference numeral 1-33 is a block load control unit, which also determines the registration compartment at the time of block loading. The block load control unit 1-33 outputs a set signal 1-34 for the validity bit registers 1-9 to 1-12 and a block load request signal 1-35. Among the circuits explained above, data registers 1-5 to 1-8, validity bit registers 1-9 to 1-1
2. Validity display registers 1-13 to 1-16, cache index upper address register 1-26, cache index lower address register, and cache registration address register 1-28 are reset by a reset signal (not shown) immediately after power is turned on. It is initialized, but here it is assumed that it is initialized to "0". Address array memory 1-1 to 1-4
The content of is indeterminate.

The operation of the present invention will be explained below.

When the need to index the cache occurs for the first time immediately after power is turned on, address array memories 1-1 to
Although 1-4 is undefined, it is exactly the same as the normal operation, that is, the cache index operation in a state where the contents of address array memories 1-1 to 1-4 are fixed by writing all words once. Similarly, the upper cache index address,
The cache index lower address register 1-27 is selected by the selector 1-29, and the address array memory 1-1 corresponding to the cache index lower address is stored.
~ Read the contents of 1-4 and write data registers 1-5 to 8
and stored in validity bit registers 1-9 to 1-12.

At this time, address array memory 1-1 to
Since the contents of 1-4 are undefined, data registers 1-5 to
8 and the contents stored in the validity bit registers 1-9 to 1-12 are also undefined, and the comparators 1-17 to 1-2
A normal hit detection function using 0 cannot be expected. However, since the contents of the validity display registers 1-13 to 1-16 are initially set to "0", the AND gate 1-2
The outputs of 1 to 1-24 are unconditionally “0”, so N
When the output of OR gate 1-25 becomes "1",
Erroneously detecting hits is suppressed.

The output of the NOR gate 1-25 is sent to the block load control section 1-33, and block load processing is started. When the block load control unit 1-33 detects a cache mishit, that is, any compartment does not match the index address, the block load control unit 1-33 outputs the block load request address, that is, the cache index lower address register 1-27 and the cache registration address register 1. Block load request signal 1-3 along with the address indexing the cache stored in -28
5 to main memory (not shown) to index the cache and request the data stored at the miss-hit address.

On the other hand, the block load control section 1-33
It determines in which compartment of the cache memory the data requested from the main memory is to be registered, and when the data is received from the main memory, it is registered in that compartment.

[0022] When the registered compartment is determined, the corresponding bit of the validity display register 1-13 to 1-16 indicating whether the compartment is valid or invalid is referred to, and if the value is "1", block load processing is performed. exit,
If it is "0", the selector 1-30 selects an address obtained by adding 1 to the lower order of the block load request address, and transmits the block load request signal 1-35 again.

Since the initial values of the validity display registers 1-13 to 1-16 are all bits "0", the block load request is issued again and registration is performed for the previously registered address. Issuance of the block load request is repeated until a match is detected by the comparator 1-31 that compares the cache index lower address register 1-27 and the cache registration address register 1-28. That is, the first transmitted block load request address is incremented by 1, and this continues until one cycle is completed.

When a match is detected by the comparator 1-31, the validity display registers 1-13 to 1-16 corresponding to the corresponding compartment are set to "1" by the set signal 1-34, thereby enabling and blocking. Finish the loading process. Therefore, if a block load process is performed on an invalid compartment, when all block loads are completed, valid data will be stored in all words of the compartment, so the compartment will be validated.

Although not shown in this embodiment, if it is possible to return data to the cache index source even if the block load processing is not completely completed, performance degradation due to continuous issuance of block load requests can be minimized. It is also possible to suppress it.

[0026]

[Effects of the Invention] As explained above, according to the cache memory control circuit of the present invention, it is possible to initialize the cache memory at high speed without preparing a special microprogram for initializing the cache memory. .

Furthermore, in order to store valid data in addition to initialization, especially in the case of a cache memory dedicated to instructions, the cache index address has high continuity, so it is shorter than the conventional circuit. This has the effect that it is possible to bring out the performance of the cache memory in a short amount of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address array of a cache memory.

[Explanation of symbols]

H~1~4 Address array memory 1-5~1-
8 Data registers 1-9 to 1-12 Validity bit registers 1-13 to 1-16 Validity display registers 1-17 to 20 Comparators 1-21 to 1-24 AND gates 1-25
NOR gate 1-26 Cache index upper address register 1-27 Cache index lower address register 1-28 Cache registration address register 1-
29, 1-30 Selector 1-31 Comparator 1-32 Counter

Claims (1)

[Claims] 1. A validity display register that indicates whether the contents of the memory of the compartment are valid or invalid for each compartment, and which is invalidated at the time of initialization, and a validity display register that is invalidated by the contents of the validity display register when the cache memory is indexed. A hit detection suppressing means for suppressing hit detection regardless of the content read for a compartment in which a block is loaded, and a hit detection suppressing means for suppressing hit detection for a compartment in which a block is loaded, if the registered compartment is invalidated by the contents of the validity display register at the time of block loading. It is characterized by comprising block loading means for all words, and validity display updating means for updating the contents of the validity display register to indicate that the contents of the compartment are valid when the loading of all blocks is completed. Cache memory control circuit.