JPH0212330A - Microprocessor control system - Google Patents

Abstract

PURPOSE:To diversify the start addresses in a reset state by starting the processes at the different addresses of a machine word instruction program according to the combination of plural signals applied to plural reset terminals. CONSTITUTION:The reset signal terminals 108-1 and 108-2 are connected to a microsequencer 103 via the signal lines 109-1 and 109-2. At the same time, the lines 109-1 and 109-2 are inputted to an OR gate 110 and the output 111 of the gate 110 is turned into an internal reset signal of the processor 101. Then the processes are started at the different addresses of a machine word program according to the combination of plural signals applied to both terminals 108-1 and 108-2. As a result, a microprocessor can be initialized into a desired state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a microprocessor, and in particular to a method for resetting a microprocessor. This was done by applying an active pulse of a certain length to a single reset terminal. When an active pulse is input from the reset terminal, the microprocessor initializes each internal block and gate and starts a new process by issuing a reset address to the memory.

For example, a case will be explained in which a microprocessor executing microprogram control is reset.

First, at the microprogram level, when the micro sequencer recognizes a reset signal, it forcibly branches to the reset micro address and executes the microprogram reset routine. Next is resetting the microprogram.

In the reset routine, a machine language instruction level reset address is issued to the memory, and processing of machine language instructions is started from the reset address. In an information processing system centered on a microprocessor such as a personal computer, checks of the system configuration, memory and Ilo tests, etc. are generally performed in the machine post-instruction program from the reset address. Checks and tests on the controller 3 are always performed at every reset.

[Problem to be solved by the invention]

As explained above, in the conventional microprocessor reset method, system configuration checks and tests are always executed at each reset.
Considering the high reliability of parts used in current information processing systems, checking the configuration and testing memory and Ilo every time a reset is performed is extremely disadvantageous in terms of time efficiency. There are drawbacks. The reason for this is that in the conventional microprocessor reset method, there is only one starting address at the time of reset.

[Differences between the invention and the prior art]

The present invention differs from the conventional microprocessor reset method described above in that processing is started from different addresses in the machine language instruction program by a combination of a plurality of signals applied to each of a plurality of reset terminals.

[Means to solve the problem]

An information processing device typified by a microprocessor includes a plurality of reset input terminals and a decoding means that inputs signals from the plurality of reset terminals, and a plurality of signals applied to each of the plurality of reset terminals. By decoding a combination of the following by the decoding means, a different address of the machine language instruction program is output after reset.

[Example 1] FIG. 1 is a diagram showing one embodiment of the present invention.

Reference numeral 101 denotes a microprocessor or CPU implementing the present invention, which employs a microprogram control system. 102 is a control memory of the processor 101;
103 is a micro sequencer that controls the control memory 102;
104 is an address register that stores the reset address of the machine post-instruction program; 105 is the processor 10;
1 is an external address bus, 106 is a data bus external to the processor 101, and 107 is a memory.

108-1 and 108-2 are 2 newly provided in the present invention.
two reset signal terminals, respectively, on signal paths 109-1 and 109-1;
It is connected to the micro sequencer 103 by 109-2. 109-1.109-2 is also input to the OR gate 110, and the output 111 of the OR gate 110 is
becomes an internal reset signal of the processor 101. 108
The input signal from -1° 108-2 defines the operation of processor 101 as shown in FIG. That is, 108-
When 1,108-2 is (00), there is no reset, and therefore the internal reset signal 111 of the processor 101 is inactive. 108-1, 108-2 is (01)
When , it is an internal reset.

The gate signal 111 becomes active and initializes each gate inside the processor 101, and at the same time, the micro sequencer 103 resets URAl in the control memory 102 in response to the fact that 108-1 and 108-2 are (01). - Performs control such as starting microprogram processing from an address. Also, 108-1 and 108-2 are (
10), at the same time that each gate inside the processor 101 is initialized, the micro sequencer 103 receives that 108-1 and 108-2 are (10), and stores the URA2 in the control memory 102. Performs control such as starting microprogram processing from the reset address. Similarly, when 108-1.108-2 is (11), reset address U is sent to control memory 102.
It is controlled to start microprogram processing from the reset microroutine from RA3. FIG. 2 is a schematic diagram of the address map of control store 102.

A machine language instruction level reset address MRAI is loaded into the address register 104 by the microphone program starting from the reset address of URAI, and MRAI is loaded via the address bus 105 as the address of the first instruction fetch after the reset. and is supplied to the memory 107.

Similarly, when microprogram processing is started from URA2, MRA2 is stored in address register 104, and MRA2 becomes the address of the first instruction fetch after reset. When microprogram processing is started from URA3, MRA2 is stored in address register 104. MRA3 is stored in , and MRA3 becomes the address for the first instruction fetch after reset. That is, 108-1, 108-2 are (0
1) from MRAI, and (lO) from MRA2.
In the case of (11), a program at the machine language instruction level is started from MRA3. FIG. 3 is an example of an address map of the memory 107 in which a program at the machine language instruction level is stored. For example, the reset routine ■ starting from MRAl checks the system configuration, and the reset routine starting from MRA2 checks the configuration of the system.
Routine (2) tests the memory and Ilo in the system, and reset routine (2) starting from MRA3 mainly branches the application program.

Immediately after the power is turned on, 108-1 and 108-2 are (01)
When you reset as, reset routine ■,■,
All processing is performed in the order of (2). 108-1,10
When 8-2 is (01), the reset routines ① and ② are performed in this order. Also, 108-1 and 108-2 are (
11), only the reset routine (2) is processed.

[Embodiment 2] FIG. 4 shows a second embodiment of the present invention. This embodiment differs from the first embodiment in the method of loading the reset address into the address register 104. In the first embodiment, the control of the microprogram is changed by changing the entry address of the microprogram for three types of reset,
Although different data were loaded into the address register 104 by the microprogram, in this second embodiment, three types of reset signals directly set three different data into the address register 404.

In FIG. 4, 404 is an address register that stores the reset address of the machine language instruction program, and 410 is a decoder that inputs 109-1 and 109-2 and decodes them according to Table 1, and outputs 411, 412°413. be. When 108-1 and 108-2 are (01), the signal 411 becomes active and the MRA is stored in the register 404.
Similarly, when (10), 412 becomes active and MRA2 is set in register 404, and when (11), 413 becomes active and MRA3 is set in register 404.

Therefore, when 108-1 and 108-2 are (01), MR
From AI, a machine language instruction level program is started from MRA2 in case of (10), and from MRA3 in case of (11). In the second embodiment, the same effects as in the first embodiment can be obtained even when the processor 101 does not perform microprogram control.

〔Effect of the invention〕

As explained above, the present invention enables a microprocessor to be brought into a desired state by starting processing from a different address in a machine language instruction program using a combination of a plurality of signals applied to each of a plurality of reset terminals. There is an effect that can be initialized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention. 101 is a microprocessor or CPU implementing the present invention; 102 is a processor 1010 control memory; 10
3 is a microphone 4 which controls the control memory 102 and a sequencer; 10
4 is an address register that stores the reset address of the machine language instruction program, 105 is an address bus external to the processor 101, 106 is a data bus external to the processor IO1, and 107 is a me%! J, 108-1゜10
8-2 is two reset signal terminals newly provided in the present invention, 109-1 and 109-2 are signal paths, 110 is an OR gate, and 111 is the output of the OR gate 110, inside the processor 101t7)! J upper set issue. FIG. 2 is a schematic diagram of the address map of control memory 102. FIG. 3 is an example of an address map for memory 107. FIG. 4 is a diagram showing a second embodiment of the present invention. 404 is an address register that stores the reset address of the machine language instruction program; 410 is a decoder; 41
1, 412, 413 are output signals of the decoder 410. FIG. 5 is a diagram showing the relationship between the operation of the preset and the input signal. Agent: Susumu Uchihara, patent attorney [Figure 2

Claims (1)

[Claims] The information processing device includes a plurality of reset input terminals and a decoding means that inputs signals from the plurality of reset terminals, and the decoding means receives a combination of a plurality of signals applied to each of the plurality of reset terminals. A microprocessor control method characterized by outputting a different address of a machine language instruction program after reset by decoding it with a .