JPH02123180U - - Google Patents

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Publication number
JPH02123180U
JPH02123180U JP3190789U JP3190789U JPH02123180U JP H02123180 U JPH02123180 U JP H02123180U JP 3190789 U JP3190789 U JP 3190789U JP 3190789 U JP3190789 U JP 3190789U JP H02123180 U JPH02123180 U JP H02123180U
Authority
JP
Japan
Prior art keywords
control device
memory control
field memory
horizontal period
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3190789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3190789U priority Critical patent/JPH02123180U/ja
Publication of JPH02123180U publication Critical patent/JPH02123180U/ja
Pending legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は実施例の要部を示すブロツク図、第2
図は波形図である。第3図、第4図は従来例の問
題点を説明するための説明図である。 1……メモリセル、2,3……アドレスカウン
タ、4……入力シリアルバツフア、8……ライン
カウンタ、9……フレームカウンタ、10……2
62Hデコーダ、11……524Hデコーダ、1
2……525Hデコーダ。
Figure 1 is a block diagram showing the main parts of the embodiment, Figure 2 is a block diagram showing the main parts of the embodiment.
The figure is a waveform diagram. FIGS. 3 and 4 are explanatory diagrams for explaining the problems of the conventional example. 1...Memory cell, 2, 3...Address counter, 4...Input serial buffer, 8...Line counter, 9...Frame counter, 10...2
62H decoder, 11...524H decoder, 1
2...525H decoder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力シリアルバツフアのビツト数が、入力され
る映像信号の1水平期間の整数分の1とは異なる
フイールドメモリの制御装置において、書き込み
リセツトパルスとして、nH,n+1H(nは自
然数で、2n+1が1フレームの水平期間に相当
する)周期を交互に有するパルスを作成する手段
と、読み出しリセツトパルスとしてnH,nH,
1H周期のパルスを作成する手段を備えることを
特徴とするフイールドメモリの制御装置。
In a field memory control device where the number of bits of the input serial buffer is different from one integer fraction of one horizontal period of the input video signal, the write reset pulse is nH, n+1H (n is a natural number, and 2n+1 is 1). means for generating pulses having alternating periods (corresponding to the horizontal period of a frame);
1. A field memory control device comprising means for creating a 1H period pulse.
JP3190789U 1989-03-20 1989-03-20 Pending JPH02123180U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3190789U JPH02123180U (en) 1989-03-20 1989-03-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3190789U JPH02123180U (en) 1989-03-20 1989-03-20

Publications (1)

Publication Number Publication Date
JPH02123180U true JPH02123180U (en) 1990-10-09

Family

ID=31258122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3190789U Pending JPH02123180U (en) 1989-03-20 1989-03-20

Country Status (1)

Country Link
JP (1) JPH02123180U (en)

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