JPH02120797A - Display device - Google Patents

Abstract

PURPOSE:To remarkably shorten the processing time by operating simultaneously an image controller and a bit mover unit by an arbiter controller, developing to a bit map memory by the bit mover unit and executing an image display. CONSTITUTION:An access request to an extended memory 7 is executed by generating a request signal as an access request from a main controller 1, an image controller 4, a video controller 5 and a bit mover unit 6, respectively. Also, by an arbiter controller 10, the prescribed priority of each request signal of them is arbitrated, and by applying selectively an acknowledge signal corresponding to the request to each controller and unit, an access to the memory 7 is permitted. Subsequently, the controller 10 generates an acknowledge signal against the request from the unit 6, and at the time of an access to the memory 7, a 1/2 period of an operation cycle becomes a priority of other controller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a display device that can efficiently display and control image data that is expanded and compressed by an image controller.

(Prior Art) With the development of image processing technology, various image data have been expanded and compressed using image controllers for image editing.

Such image data expansion/compression and image display generally uses an expanded memory built into the device as a common memory, and an image controller performs expansion/compression processing on the expanded memory and then expands it. The image data drawn in the bitmap memory is drawn on a bitmap memory by a bitmover unit having a bitblit function, and the image data drawn on this bitmap memory is displayed on a predetermined display device (CRT display, etc.). This is done by displaying an image using

Incidentally, accesses from the image controller, bit mover unit, etc. to the extended memory for writing image data into the extended memory and reading this image data from the extended memory are arbitrated and controlled by the arbiter controller. .

However, in order to display the image data expanded and compressed by the image controller on the display device, the image data is first written from the image controller to the extended memory, and then the bit mover Since it is necessary to draw the image data from the extended memory to the bitmap memory using the unit, there is a problem that the processing time is extremely long.

(Problem to be Solved by the Invention) As described above, in the conventional device, the image controller writes the image data to the extended memory, and the bit mover unit reads the image data from the extended memory. Since this is done asynchronously and with a time lag under the arbitration control of the arbiter controller, there is a problem in that it takes time to display the expanded/reduced image data.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a display device that can efficiently display image data expanded and compressed by an image controller in a short time. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) The present invention uses an extended memory to control the expansion and compression of image data with an image controller and a bit blit function. The image
A display device includes a bit mover unit that draws data on a bitmap φ memory and displays an image, and an arbiter controller that arbitrates access to the expanded memory, A mode switching control means is provided to operate the bit mover unit in synchronization with the bit mover unit, and when the synchronous mode is set, the bit mover unit is set to, for example, write inhibit, so that the image controller operates in the expanded memory. The present invention is characterized in that data is latched, and the latched image data is drawn in the bitmap memory by the bitmover unit.

(Function) According to the present invention, when the arbiter controller sets the synchronous operation mode between the image fist controller and the bit mover unit, the image that is expanded and compressed by the image controller and written to the expansion unit. - Data is latched, for example, word by word in a latch circuit, and is sequentially drawn in a bitmap memory by a pip and mover unit in synchronization with the latch of the image data.

Therefore, while expanding and compressing the image data using the Image Fist Controller, the bit mover unit can immediately draw the image data in the bitmap memory and display the image.
It becomes possible to significantly shorten the processing time required from the expansion φ reduction process on data to the display of the image data.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of the configuration of the apparatus according to the embodiment, and (2) is a main controller that controls the entire apparatus. This main controller has data bus 2 and address bus 3.
An image controller 4, a video controller 5, a bitmover unit 6, and an expansion memory 7 are respectively connected through the memory.

The image controller 4 executes expansion and compression processing on image data, and the video controller 5 controls display of the image data. Also bit mover unit 6
The main function is to draw character fonts, graphic images, etc. in a bitmap memory 8, and to display the images on a display device 9 such as a CRT display.

The extended memory 7 is used as a common H memory that is accessed by each of these units and used in common throughout the device, and access from each unit to the extended memory 7 is controlled by a predetermined method by the arbiter controller IO. Arbitration control is performed according to the priority order.

Here, the feature of this device is that the expansion memory 7
an arbiter controller that arbitrates and controls access to
The bit mover unit 6 has a function of switching the operation mode of the image controller 4 and the bit mover unit 6 between an asynchronous mode and a synchronous mode, and a function of setting the bit mover unit to write inhibit when setting the synchronous mode. It is characterized by the fact that it is equipped with When the synchronous mode is set, the image controller IO transfers the image data developed into the extended memory 7 to the latch circuit 1.
1. 12, and this latch circuit 11, 1
Flip-flop 13 for indicating the state as data enable when image data is latched in 2.
It is characterized by being configured with the following.

Figure 2 is a diagram showing the operation timing when the asynchronous mode is set in this device configured as described above, Figure 3 is a diagram showing the operation timing when the synchronous mode is set, and Figure 4 is a diagram showing the operation timing when the line inhibit is set. FIG. 4 is a diagram showing operation timing in synchronous mode when

The operation of this device will be explained with reference to these operation timing charts.

An access request to the extended memory 7 is made by the main controller! , image controller 4° video controller 5. and request and strike signals (CMCPRQ) from bit mover unit 6, respectively.

CAIPl? Q.CVCP)? Q, 13MREQ
) by issuing each as an access request. The arbiter controller IO arbitrates these request signals in a predetermined priority order and sends them to the main controller.
Controller l, image controller 41. Video controller5. and bitmover unit 6
Acknowledge signals (CMCPAC, CAIPAG, CVC) corresponding to each of the request signals
PAG, DMACK) are selectively given to permit access to the extended memory 7.

However, the arbiter controller 10
When an acknowledge signal (DMACK) is issued in response to a request signal (BMREQ) from unit 6 to permit access to extended memory 7 by bit mover unit B, the operation cycle is divided into two, and the first half is 1/2. The extended memory 7 is accessed from the main controller 1, image controller 41, and video controller 5 in priority order for the cycle period, and the bit mover unit is used for the remaining half cycle period. Control is performed so that B can access the extended memory 7 with the highest priority. Under such control of the arbiter controller IO, image data can be selectively transferred between the image controller 4 and the bit mover φ unit 6 in a synchronous or asynchronous manner.

That is, when the asynchronous mode is set, the arbiter controller 1O performs an image process as shown in FIG.
Request signal from controller 4 (CA I PR
Q) returns an acknowledge signal (CAIPAG). At the same time, address enable (No. 6 (φ)) and data enable (No. 15 (φ)) are issued. The image controller 4 issues this access signal (CA I
Knowing that access to extended memory 7 has been granted in response to address bus No. 15 (BMAD)
X) and data bus signal (BMDTX)
is output, the extended memory 7 is accessed, and the expanded/reduced image data is transferred to the extended memory 7.

Thereafter, in the next cycle, the arbiter controller 10 sends an acknowledgment signal (BMAC) in response to a request signal (BMREQ) from the bit mover unit 6.
) and simultaneously returns the address enable signal (BMA
EN) and data enable signal (nMI) IEN
) is emitted. Then, the bit mover unit 6 receives this access signal IM (〇K) and knows that access to the expansion memory 7 is permitted, and transmits the address bus signal (〇Y■) and data bus signal (13MDTX
) to access the extended memory 7 and transfer the image data stored in the extended memory 7 to the previous bitmap φ memory 8.

Note that φWEN is a write enable signal, and φVA
STB is a signal indicating the access state of the extended memory 7.

When the asynchronous mode is set, the access to the extended memory 7 is arbitrated by the arbiter controller 10, and after the image data is transferred to the extended memory 7 by the image controller 4, the bit mover unit 6 is transferred in the next cycle. The image data stored in the extended memory 7 is transferred to the bitmap memory 8 by
The image is then displayed on the display 9.

On the other hand, when the synchronous mode is set, the operation is controlled as shown in FIG. 3 under the control of the arbiter controller 10.

That is, in this case, the arbiter controller lO returns an acknowledge signal (CA I PAG) in response to the request signal (r) from the image controller 4, and also sends an address enable signal (φm) and a data enable signal (φDIEN). ) is emitted.

The image controller 4 receives this access signal (CA
IPAG), the address bus signal (8%^D
XX) and a data bus signal (eclipse η1]) to access the extended memory 7 and transfer the expanded/reduced image data to the expanded memory 177. At this time, the image processor 4 outputs the write enable signal (φME) during its data enable (φDISIN) period.
N), and outputs the above-mentioned acknowledge signal (CA I P
AG) and a write enable signal (φMEN) to set the data enable flip-flop 13. By setting this flip-flop 13, (+
! DTI:NO) is provided to the arbiter controller IO.

Through this processing operation, the image data from the image controller 4 is written into the extended memory 7, and at the same time, the image data is latched into the latch circuit 11.

A data set signal (PDTENB) is output from the flip-flop 13 to indicate the latched state of the image data by the latch circuit H.

In this state, when a request signal (BMREQ) is issued from the bit mover unit 6, the arbiter controller! 0 is given the data set signal (PDTENB) from the flip-flop 13, so the access signal (13MA) is sent to the mover unit 6.
CK) and resets the flip-flop 13. However, the above acknowledge signal (BMACK)
The bit mover unit 6, which operates in response to this, reads the image data set in the latch circuit 11 and writes it into the bitmap memory 8.

Note that during this period of time, during the operation period of the bit mover unit 6, the (φVASTBBMAI signal) is
B, BMDEN) is never emitted.

As described above, when the synchronous mode is set, one cycle period is divided into two under the control of the arbiter controller IO, and the image data transferred and written from the image controller 7 to the extended memory 7 is transferred to the latch circuit. 1
1, and in synchronization with this, the bit mover unit 6 transfers and writes the latched image φ data to the bitmap memory 8.

On the other hand, even when the same synchronous mode is set, if the line inhibit is set, the operation is as shown in FIG. 4. This operation is basically performed in the same manner as in the synchronous mode shown in FIG. 3 above, but
The difference is that when the image controller 4 accesses the extended memory 7, the arbiter type controller 1O does not output a signal (φVASTB) indicating the access state to the extended memory. That is, the extended memory 7 converts the signal (φ〒[]) into the signal (RAS),
(daytime) and controls writing of data to the extended memory 7. Therefore, since the line inhibit is set and the output of the signal (φVASTB) is stopped, in this case, the image data output from the image controller 4 is latched when the image controller 4 accesses the extended memory 7. It is latched by the circuit 11, and the upper self-image data is only transferred to the bitmap memory 8 by the bit mover unit 6, but the above-mentioned image data is not written to the extended memory 7. ing.

As a result, when the line inhibit is set, the image data processed by the image controller 4 can be transferred to the bit mover without wasting the extended memory 7 to write the image data. It will be transferred and written directly to the bitmap memory 8 via the unit 6.

According to the present apparatus, which not only operates the image controller 4 and the pim-mover unit 6 asynchronously as described above, but also operates the image controller 4 and the pim-mover unit 6 synchronously by setting the synchronous mode. The goal is to significantly shorten the processing time when displaying image data that has been expanded and compressed.

In other words, the processing time in the image controller 10 is practically the same, and the transfer period to the memory 7 is effectively used to expand the image data, and the image data is converted into bitmap data in synchronization with the transfer operation. It becomes possible to develop the image in the memory 8 and display it as an image.

As a result, it becomes possible to effectively solve the problems with conventional devices and to perform expansion/compression processing on image data and displaying the image in a short time and efficiently.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, the arbiter controller causes the image controller and the bit mover unit to operate synchronously, and the image controller latches the image data expanded to the extended memory. In synchronization with this, the bitmap ψ memory is expanded into the bitmap ψ memory and displayed as an image, resulting in many practical effects such as being able to significantly shorten the processing time.

[Brief explanation of the drawing]

The figures show a display device according to an embodiment of the present invention. FIG. 1 is a schematic configuration diagram of the embodiment device, FIG. 2 is a diagram showing the operation timing when setting the asynchronous mode, and FIG. 3 is a diagram showing the synchronous mode. FIG. 4 is a diagram showing the operation timing at the time of setting. FIG. 4 is a diagram showing the operation timing when the synchronous mode is set and two line inhibits are set. l...Main controller, 4...Image controller
Controller, 5... Video controller, 6
... Bit mover unit, 7... Expansion memory,
Death: Bitmap number memory, 9: Display unit, 10:
...Arbiter controller, I+, +2...Latch circuit, 13...Flip-flop. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] An image controller that controls the expansion and compression of image data using an extended memory and a bit blit function, and draws the image data written in the extended memory to a bitmap memory. In the display device, the arbiter controller controls the image controller and the bit mover unit between a synchronous mode and an asynchronous mode. and means for setting the bit mover unit to write inhibit when setting the synchronous mode, the image controller latches the image data to be developed in the extended memory, and A display device characterized in that the latched image data is drawn in the bitmap memory by the bitmover unit.