JPS6391787A - Graphic processor - Google Patents

Abstract

PURPOSE:To permit the same basic information to be shared, by controlling connection or disconnection between a first address bus and a first data bus connected to a main processor, and a main memory, and between a second address bus and a second data bus connected to a frame buffer. CONSTITUTION:A bus switch 20 switches the supplying of the address buses of the main memory 12 and the frame buffer 14 from which address bus connected to a graphic processor 10, or a central processor 11. The graphic processor 10 which becomes a second processor means receives a command, and a bit of parameter information transferred from the central processor 11 which becomes a first processor means, or a main memory 12, and accesses to the frame buffer 14, or the main memory 12, and generates a character, or a graphic data. Also, the graphic processor 10 can read out the command, or the bit of parameter information also from the frame buffer 14.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a graphic processing device that displays and prints characters and figures, and particularly relates to a graphics processing device that displays and prints characters and figures, and in particular, it can be used not only on the frame buffer but also on the system memory (main memory) at high speed. The present invention relates to a graphics processing device that can perform drawing processing.

[Conventional technology]

As a method for displaying characters and figures on a CRT using the Rask scan method, there is a method (referred to as the bitmap method) that has a memory (bitmap memory) that stores information corresponding to each pixel of the display device. Also.

This method of having a bitmap memory is also used when controlling output to a printer. Conventional.

The process of generating character and graphic data in the bitmap memory was mainly performed using liftware, but there was a problem in that it was slow due to the large amount of data being handled. on the other hand,
Particularly in the field of generating graphics figures at high speed, some methods using dedicated hardware have been used, but the disadvantage is that they are expensive.

In response to this, functions for generating character and graphic data are now being built into LSIs.For example, a well-known document states, ``Kazuo Gohoyou?'' The drawing position can be specified by coordinates, and the "CRT Controller 1 Herola with a wealth of commands such as and copy" Nikkei Electronics 19
May 21, 1984 issue, PP, 221-254J.

If this LSI is used, graphic processing can be greatly accelerated at a relatively low cost.

[Problem that the invention seeks to solve]

According to the above-mentioned literature, although it is possible to perform drawing on a frame buffer at high speed, it is not possible to perform drawing on a system memory connected to a cPU.

For example, other output means, such as a printer control circuit, are often connected to the system bus, and in this case, a buffer for print output is secured on the system memory. However, when trying to print out the graphic data,
Since drawing cannot be executed with the CRT controller mentioned above,
Currently, drawing is performed using software. For this reason, there has been a problem in that although graphic data to be displayed on a CRT screen can be drawn at high speed, graphic data to be printed out is drawn at low speed.

On the other hand, as a means to improve processing performance, the frame buffer is divided into color planes and multiple graphics
It is conceivable to perform parallel processing using processors. In the CRT controller method described in the above-mentioned literature, in order to copy the same basic information (for example, character font data) to multiple planes, the basic information must be stored in the frame buffer corresponding to each plane. It is necessary to memorize it in advance. That is, since the same information is placed in multiple memories, there is a problem of poor memory efficiency.

As described above, with the conventional technology, in addition to slowing down the drawing speed on the system memory, when the frame buffer is divided into color planes and processed in parallel by multiple processors, There is a problem in that it is necessary to have multiple pieces of basic information.

An object of the present invention is to enable access to system memory from a graphics processor, thereby speeding up drawing processing in the system memory, and, when parallel processing is performed by multiple processors, to access commonly used basics such as character fonts. Information is placed on system memory so that it can be shared.

[Means for solving problems]

A feature of the present invention for achieving the above object is to interpret commands transferred from a first data bus connected to a main processor (CPU) and transfer commands to a second address bus connected to a frame buffer. A first address bus and a first data bus are connected to the main processor and main memory, and a second bus is connected to a frame buffer.
The present invention provides bus connection control means capable of controlling connection or disconnection between the second address bus and the second data bus.

[Effect]

In order to enable drawing from the graphics processor onto the system memory, the address sent to the second address bus connected to the frame buffer is connected to the bus connection control means and the first address bus to the system memory. Perform reading and writing of data.

Additionally, in systems with multiple graphics processors and frame buffers per color plane, basic information on the system memory is read using the address supplied by one of the graphics processors, and the read data is loaded into multiple processors simultaneously. The bus connection control means is controlled as follows.

〔Example〕

Preferred embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 shows an example of an overall configuration overview of a graphic display device embodying the present invention. A graphics processing unit (GDP) 10 serving as a second processor means, a central processing unit 51 (CPU) 11 serving as a first processor means, a main memory 12 serving as a first storage means, and a direct memory access controller (DMAC) 13 , a frame buffer 14 as a second storage means, a parallel-to-serial conversion circuit 15, a display device (CRT) 16 as an output means, an address decoder 17, and a bus switch 20 as a bus connection control means. Although not shown, other input/output means such as other display devices and printing devices are connected to the system bus connected to the central processing unit 11 to perform display, printing, etc. using pixel information in the main memory 12. It is possible to perform other input and output.

The central processing unit 11 executes programs stored in the main memory 12 or programs transferred from other external devices (not shown) and manages and controls the entire system.

Direct memory access controller 13 controls direct memory access between main memory 12, graphics processing device 10, and frame buffer 14 or other input/output devices (not shown). The graphic processing device 10 is the central processing unit 1
1 or from the main memory 12 through a data bus connected to the central processing unit 11, and according to a predetermined processing procedure, the frame buffer, -.

14 or main memory 12 to frame buffer 14
It generates character and graphic data by accessing it from the address/data bus connected to it. The graphic processing device 10 can also read commands and parameter information from the frame buffer 14. Further, the graphic processing device 10 includes a display device 1
It also controls the generation of a synchronization timing signal to control the frame buffer 6 and the readout of information to be displayed sequentially from the frame buffer 14 in synchronization with a predetermined timing. The graphic processing device 10 also includes a bus switch 2 for controlling direct memory access between the central processing unit 11 or the direct memory access controller 13 and the frame buffer.
0 and generates control signals for the graphic processing device 10 to access the main memory 12 and generate characters and graphics. Address decoder 17 decodes an address on an address bus connected to central processing unit 11 and generates a frame buffer bus request signal to bus switch 20. The bus switch 20 switches from which of the free buses the water is supplied.

Alternatively, the bus switch 20 also switches whether the address of the main memory 12 is supplied from the address bus connected to the central processing unit 11 or the address of the graphic processing device 10. That is, the bus switch 20 has a function as a bidirectional switch, and is controlled by a control signal from the graphic processing device 10.

Other configuration examples are shown in FIGS. 2, 3, and 4. These components are CRT and liquid crystal displays.

Display devices such as EL displays, plasma displays, and ECD displays, as well as thermal printers.

It can also be applied to printing devices such as liquid crystal printers, LED printers, and laser beam printers, in which case the portion corresponding to the display device 16 becomes the printing device.

FIG. 2 shows the configuration of a graphic display device in which a bus connected to the central processing unit 11 and a bus connected to the frame buffer 14 are separated.

Graphics processing unit (GDP) 10, central processing unit (CPU)
11. Main memory 12. Direct memory access controller (DMAC) 13. Frame buffer 14, parallel/serial conversion circuit 15, display device (CRT) 16. Consists of.

The second configuration is a simple configuration suitable for small devices.

FIG. 3 shows an example of the configuration of a graphic display device having a bus switch 21 for switching whether the address of the frame buffer 14 is supplied from an address bus connected to the graphic processing unit 10 or the central processing unit 11.

Graphic processing unit (GDP) 10, central processing unit (C:PU
) 11, main memory 12, direct memory access controller (DMAC) 13, frame buffer 14, parallel/serial conversion circuit 15, display device (CRT) 16, address decoder 17, and bus switch 21.

In the configuration example shown in FIG. 1 or 3, the central processing unit 11
data is transferred between the central processing unit 11 or the direct memory access controller 13 and the frame buffer 14 without going through the AT processing unit 10. As a result, the central processing unit i! ! This has the advantage that the frame buffer 14 can be arbitrarily accessed from the frame buffer 11.

FIG. 4 shows the address bus connected to the central processing unit 11 or the graphic processing unit 1 connected to the main memory 12.
This is an example of the configuration of a graphic display device having a bus switch 22 that switches from which address 0 the data is supplied.

Graphics processing unit (GDP) 10, central processing unit (CPU)
11. Main memory 12. Direct Memory Access Controller (DMAC)13. It consists of a frame buffer 14, a parallel/serial conversion circuit 15, a display device (CRT) 16, and a bus switch 22.

In the configuration example shown in FIG. 1 or 4, character fonts are placed in the area of the main memory 12, and the graphic processing device 10 can perform bitmap character color development processing.

In addition, the graphic processing device 1o executes pattern development processing by arranging pattern information composed of binary information or multi-value information in the area of the main memory "1'2". Bitmaps can be copied to and from the buffer 14. Copying can also be performed between bitmaps with different memory widths or different numbers of bits per pixel.

Details of a control example when the central processing unit 11 directly accesses the frame buffer 14 without going through the graphic processing unit 10 will be described below. however.

This method allows direct access to the frame buffer 14 not only to the central processing unit 11 but also to all semiconductor devices with a data transfer function, such as the direct memory access controller 13 connected to the address and data bus of the central processing unit 11. is applicable.

FIG. 5 shows a sequence when the central processing unit 11 accesses the frame buffer 14 via the bus switch 20 or the bus switch 21. The address decoder 17 decodes the address of the address bus connected to the central processing unit 11 and asserts a signal requesting the bus switch 20 or 21 to take over the frame buffer 14. The bus switch 2o or the bus switch 21 receives the bus request signal and asserts a stop signal HALT to the graphic processing device 10. The graphic processing device 1o executes drawing 9 display, refresh control, and attribute output for the frame buffer 14, but the priority for the HALT input can be set independently in advance, and a BUSY signal indicating a period in which the HALT does not stop is used. Assert externally. (Outside the BUSY period) In response to the i ALT input, the graphic processing device 1o stops its internal operation, and the address bus and data bus are tristated. The bus switch 20 or the bus switch 21 connects the system bus outside the BUSY period and the frame buffer bus, and the central processing unit 11 accesses the frame buffer 14.
inputs the ACK signal to the central processing unit, and the series of operations is completed.

The above is the operation when there is only one graphic processing device 10, but
When a plurality of graphic processing devices 10 or other graphic processing devices with different functions are connected to the same frame buffer bus, the graphic processing device outputs a drawing request signal DRREQ to enable bus arbitration.

FIG. 6 shows an example of a sequence when the graphic processing device 10 accesses the main memory 12 via the bus switch 20 or the bus switch 22.

The command MMA is sent to the graphic processing device 10 in advance.
(Main Memory Access Mode)
By setting , the addresses of the upper 256 Mbytes (512 Mbytes in total) of the address space of the graphic processing device 10 can be allocated as the main memory 12 space. In this case, the graphic processing device 10 asserts the system bus request signal BREQ.

The bus switch 20 or 22 that receives the bus request signal asserts the BR multiplication signal to the central processing unit 11 (assuming a Motorola CPU here). At the same time, HALT is input to the graphic processing device 10,
Stop the drawing processor. The bus switch 2o or bus switch 22 connects the central processing unit 11 to the BG.
When the double signal is received, confirm that the system bus is released.

Assert BGACK to the central processing unit 11.

At the same time, HALT is negated for the graphic processing bag [10, allowing access to the system bus.

When the graphics processing device 10 enters the drawing period, it outputs a HOLD signal to indicate the access execution period to the system bus. The bus switch 20 or 22 accesses the main memory 12 during the HOLD period.

If drawing to the main memory 12 is not completed in one cycle, the bus switch 20 or bus switch 22 asserts the RETRY signal to the graphics processing device to cause the graphics processing device to execute drawing again. An example is shown. n (n≧2) graphic processing devices 10
-1.10-2゜...10-n, central processing unit 11, main memory 12, direct memory access controller 13, frame buffer 14-1 divided into n pieces
．． 14-2. 14-n, n parallel-to-serial conversion circuits 15-1, 15-2, --15-n, display device CRT (not shown), n bus switches 20-1
゜20-2. ...consisting of 20-n.

In the embodiment shown in FIG. 7, the frame buffer 14
is divided into color plane units, and multiple graphic processing devices 1
By arranging 0's, parallel processing is possible.

Each graphic processing device 10-1.10-2. ...10
-n is bus switch 20-1.20-2.・・・・・・
The main memory 12 can be accessed by the effect of 20-n. Therefore, commonly used basic information such as character fonts can be stored in the main memory 12, improving memory efficiency. Add one character font to each frame buffer 14-1.14-2°...
When performing common processing such as expanding to 14-n, the command processing can be synchronized using the EXEC signal, and the data read from the main memory 12 is transferred to each graphic processing bag [10-1 ,10-2,...10-n
can be imported at the same time.

As a result, the same data only needs to be read once, and processing efficiency can be improved.

Next, the internal configuration of the graphic processing device (GDP) will be explained in detail.

FIG. 8 shows the internal configuration of the graphic processing device 10, which includes a drawing processor 101, a display processor 102, a timing processor 103, a CPU interface 106, an interrupt control circuit 105, a DMA control circuit 104. It consists of a display interface 108 and a bus control circuit 107. The drawing processor 101 generates figures such as lines and planes, and
It controls data transfer etc. between U and display memory.
Outputs the drawing address and reads and writes the display memory. The display processor 102 outputs display addresses of the display memory to be displayed sequentially according to rask scanning. A timing processor 103 generates various timing signals such as a CRT synchronization signal, display timing, and a display/drawing switching signal.

The CPU interface 1o6 is a central processing unit (CPU) for synchronization between the CPtJ data bus and the graphic processing device 10.
Controls the interface with 11. Interrupt control circuit 105
generates an interrupt request signal (IRQ) to the CPU. Direct memory access (hereinafter referred to as DMA) control circuit 1
04 is a DMA controller (hereinafter referred to as DMAC) 13
The 6-display interface 108 controls the exchange of control signals with the display memory and the display device, such as address switching control between display and drawing. The bus control circuit 107 controls access rights to the frame buffer bus, and controls whether to permit use of the bus for externally requested signals. In this graphic processing device 1o, processing efficiency is improved by distributing the functions of three processors for drawing, display, and timing and operating in parallel.

Next, the functions of each input/output terminal of the graphic processing device 10 will be explained in detail.

(1) Bidirectional data bus (Do to D15 dual output) This is an input/output signal used for data transfer between the system bus and the graphic processing device 10. This terminal is a three-state buffer and is in a high impedance state except when the internal register of the graphic processing device 10 is read from the central processing unit 11 side.

(2) Reset (RES: input) This is a human signal for resetting the internal state of the graphic processing device 10 from the outside. 0 to this terminal. When an I+ level signal is input, the internal state is reset and the display,
Drawing operation stops.

(3) Read/write (R/W: input) central processing unit 1
This is an input signal that controls the direction of data transfer between the system bus on the first side and the graphic processing device 10. When the level is "High", it is a read (data transfer from the graphics processing unit 10 to the central processing unit 11 side), and when it is "Low", it is a write (data transfer from the central processing unit 11 side to the graphics processing unit 110). However, in DMA transfer mode, 1
1. When the level is High II', the data is transferred from the main memory side to the graphic processing device 10. When the level is "Low", the data is transferred from the GDPIO to the main memory 12 side.

(4) Chip select (τ = input) This is a selection input when the central processing unit 11 accesses the graphic processing device 10. In other words, illO to v-cho
Graphic processing device 1 only when wI+ level is input.
It is possible to read/write to the internal register of 0.

(5) Register select (R31-2: input) This is an input signal for selecting an internal register of the graphic processing device WIO.

When both R31 and R82 are "LO", the address register is selected for writing, and the status register is selected for reading. R3I is “Low”, R52 is 1111
4 When ghIj, FIF○ is selected and RS 1
When RS2 = "High" and RS2 = "Low", the control register specified by the address register is selected.

(,6) Chi'1 transfer acknowledge (DTACK: output) This is an output signal indicating completion of data transfer. This signal is used to control data transfer when interfacing with an asynchronous bus.

(7) Interrupt request (LRQ: output) This is an output signal of an interrupt request that notifies the central processing unit 11 of command completion, detection of an undefined command, etc. This terminal is an open drain output, and can be wired ORed with the interrupt request output from another device.

(8) DMA transfer request (DREQ: output) When performing data transfer in DMA transfer mode, the DMA controller 13
This is an output signal for requesting data transfer.

Two DMA transfer methods can be selected: cycle steal mode and burst mode.

(9) DMA transfer acknowledge (DACK: input) DR
This is a response input from the DMA controller 13 to the EQ signal. Data access is performed when a 1'Low'' level is input to this terminal.

(10) Horizontal synchronization/external horizontal synchronization (H5YNC/EXH
5YNC: input/output) When this terminal is set to output, it outputs a horizontal synchronization signal for the CRT display device 16.

If it is set to input, a horizontal synchronization signal is input from an external device such as a TV, and the internal horizontal synchronization operation is synchronized with this input signal.

(11) Vertical synchronization (USYNC: output) This is an output signal for applying vertical synchronization to the CRT display device 16.

(12) Vertical external synchronization (EXVSYNC: input/output) multiple graphic processing devices 10-1.10-2.・・・・・・１
This is an input/output signal for performing 0-n parallel operation or synchronous operation with other external equipment. At mass time, VSYN
The synchronization operation is performed using the same signal as C, and in the interlace mode, a signal separated from VSYNC for only odd fields.

(13) Display timing 1/2 (DISPI, DISP
2: Output) 6DISP which is an output signal indicating the screen display timing
I is O of the display period of each drawing set as the base screen
This is the signal output with R.

DISP2 outputs a signal indicating the display period of the superimpose screen.

(14) Cursor display (CUD: output) This is an output signal for displaying a cursor on the screen of the CRT display device 16. By controlling the cursor definition register, you can select either a graphref cursor or a crosshair cursor.

(15) Memory data (MDO to 31: input/output) This is a 32-bit input/output terminal for transferring data between the graphic processing device 10 and the frame buffer 14. Also, during the display cycle period, it serves as an output terminal for attribute signals.

(16) Memory address (MAO~27: output) This is a terminal that outputs the address of the frame buffer 14. When using dynamic RAM for the frame buffer 14,
A refresh address can be output to this terminal during the horizontal synchronization period.

(17) Memory address strobe (MAS: output)
6 (18) Frame buffer bus status (FBSO
~3: Output) This is a signal output indicating the state of each memory cycle of the frame buffer bus. By decoding this signal externally, the type of bus cycle can be known.

Details are shown in the table below.

(I9) Execute (EXEC: input/output) n graphic processing devices 10-1.10-2. ...10-n
This is an input/output signal for synchronizing drawing operations on a command-by-command basis when a plurality of are used in each color plane. This terminal is an open drain, and the signals of each graphic processing device 10-1, 10-2, . . . 10-n are wired OR-connected. Graphic processing bag v110-1
．． 10-2. ...10-n sets this terminal to l1lo and II while the command is being executed, and when the command is finished, #
Make it lighl+. Therefore, this wired OR-connected terminal is connected to all graphics processing devices 10-1.1.
0-2. ...6 graphic processing device 10-1.1 that becomes "high" when 10-n finishes the command
0-2.・・・・・・10-n is this terminal II 1o
ν” period, you cannot move on to the next command execution, but #H
Immediately after detecting ighIt, it is possible to move on to executing the next command.

(20) Clock 1.2 (CLKI, 2: Input) A clock signal serving as a reference for the internal operation of the graphic processing device 10 is input. Clock signal CLK2 is clock signal CLK
A signal whose phase is delayed by 90' with respect to I is input.

(21) 2 clocks (2CLK: output) clock signal C
Outputs a clock signal obtained by dividing LKI by two.

(22) Memory cycle (MCYC: output) A signal output indicating the memory access timing of the frame buffer 14. This signal is a clock obtained by dividing 2CLK by two.

(23) Pass refresh request (BREQ: output) This is a request signal for the right to use the bus when the graphic processing device 10 accesses the system memory 12.

(24) Hold (HOLD: Output) After the graphics processing device 10 outputs a bus request to the system bus and becomes the bus master, it is a drawing access that outputs “High” to this terminal during the period in which the bus is exclusively occupied. When the graphics processing device 10 accesses the system memory 12 and the cycle time of the system memory 12 is longer than the memory cycle time of the graphics processing device 10, this terminal is input with 11 Hjg h.
By inputting #, the same memory access can be re-executed in the next drawing cycle.

(26) Busy (BUSY: Output) II Hjgh IT level is output during the refresh address output period or the display memory cycle period in display priority mode, which indicates a memory cycle period during which the graphic processing device 10 cannot release the frame buffer 14. be done.

(27) HALT (input) This is an input signal for prohibiting frame buffer access of the graphic processing device 10. When BUSY is "Low", a halt is accepted and the graphic processing device 10 does not perform memory access. Signal BUSY is “High”
In this case, this signal input is ignored. Therefore, this signal can inhibit drawing memory cycles in display priority mode, and both drawing and display memory cycles in drawing priority mode. Furthermore, when the graphic processing device 10 accesses the system memory 12, the signal BREQ
After output, input HH''ghII to the external circuit terminal, and then output signal HA according to the system bus use permission signal.
Permission to use the bus is notified by inputting "lO,II" to LT.

(28) Draw request (DRREQ: output) This is a drawing request signal to the frame buffer 14. When a plurality of graphic processing devices 10 share the frame buffer 14, this signal is determined by an external bus arbitration circuit to allocate the right to use the bus.

FIG. 9 shows a drawing processor 10 in the graphic processing device 10.
This figure shows the internal configuration of 1. Drawing processor 10
1 is a PIFO 101 for receiving commands and parameters from the central processing unit 11, etc., and for data transfer.
5. Command register 1014 for setting commands;
A logical address calculation unit 1013, a first microprogram ROM10II and a first microinstruction decoder 1012 that control the logical address calculation unit 1013, a second microprogram ROM 1016 and a second microprocessor that control the physical address calculation unit 1019 and the color data calculation unit 1020. Instruction decoder 1017. Internal R that stores line type information, bell information, etc.
It is composed of AM101g.

When a command is received from central processing unit i (CPU) 11, the command is set in command register 1o15, and the corresponding microprogram is read from first microprogram ROM 101.1. 1st
The microinstruction decoder 1012 decodes it and controls the logical address calculation unit 1o13. On the other hand, some of the micro instructions are stored in the second micro program ROM 101.
This is the address for reading 6. The read microprogram is sent to the second microinstruction decoder 1o1.
A physical address calculation unit 1019 for calculating a memory address of the frame buffer 14 corresponding to a logical address decoded by 7 and a color data calculation unit 1020 for calculating one graphic data are controlled.

Further, the internal RAM 1018 has internal RAM-specific addressing and frame buffer addressing that can be accessed as part of the frame buffer space. The internal RAM is suitable for storing frequently accessed information because it can be accessed faster than the frame buffer. This information includes line type information that specifies the line type when drawing a line segment, bell information that specifies the thickness of the line segment, pattern information that specifies the pattern when drawing a surface, and internal information. Stacks, etc. to be temporarily saved are raised. In this embodiment, line type information and bell information are managed using internal unique addressing, and pattern information and stack are managed using frame buffer addressing. This is because when accessing the internal RAM 1018, unique addressing allows faster access than frame buffer addressing. on the other hand,
Since the pattern information and stack cannot be limited to 8 frames, in a situation where the pattern information and stack cannot be set in the internal RAM 1018, the area is managed by frame buffer addressing so that the area can be expanded to the frame buffer.

However, there are ways to use the internal RAM 1018 other than in this embodiment, such as having only internal addressing unique to the internal RAM and accessing patterns and stacks faster, and having only frame buffer addressing and having 8 views of line type and bell information. There are also ways to enable expansion.

Next, frame buffer addressing of internal RAM 1018 will be explained.

FIG. 10 shows a block diagram of a portion of the drawing processor 101 in the graphics processing device (GDP) 10 related to the interface to the frame buffer 14 and the bus control circuit 107. The bus control circuit 107 provides control signals for accessing the frame buffer 14 connected to the system bus of the central processing unit 11 and the graphic processing unit 10.
generates a control signal for accessing system memory 12 from.

Internal RAM 1018 for frame buffer addressing)
When accessing by programming, first write the frame buffer 1 to the internal RAM address register (IRAR) 2006.
Store the starting address to be placed on 4. Of the 32 bits of the register 2006, the lower 12 bits are not set. The drawing processor 101 uses the frame buffer 14
When accessing, the address is set in the memory address register (MAR) 2004 in bit units.

At this time, a coincidence detector (IRCMP) 2007 compares the contents of the register 20o4 and the above register.

The comparator 2007 does not compare the lower 12 bits of the 32 bits. Therefore, if the comparator 2007 outputs a match signal, the address set in the memory address register 2004 is the address for accessing the internal RAM 1018. Therefore, in order to access the internal RAM 101g using the above coincidence signal, the internal RAM
Instead of address information for unique addressing,
The internal RAM 101g is accessed using the lower 12 bits of the address value of the memory address register 2004. On the other hand, the draw request generator 2013 is instructed not to access the frame buffer 14.

FIG. 11 shows a list of control registers and RAM inside the graphic processing unit (GDP) 10 that can be accessed from the central processing unit (CPU) 11. There are two ways to access these internal registers:

(1) Registers that can be accessed directly from the central processing unit (CPU) 11 FIG. 12 summarizes the detailed configuration of the registers and RAM that can be accessed directly from the central processing unit 11. In the address register, a condition of "[, Ov" can be written for both R3I, R82°C5, and R/W. The address/write FIFO counter registers are R3I, R
S2. C3 is both 11LOwII and R/W is “l(ig
The address register and write FIFO counter can be read under the condition "h".

The status register can be read when R81 is "Low" and R32 is low. In the status register clear register, R8I is 'Loν' and R82 is 'old g'.
It can be written when CS is “Low” and R/W is “Low”. FIFO is R3I
gh”, RS 1 is “Low”, CS is (ILO,
It can be accessed on Fl. For other registers, specify the register number with the address register, then R8I.

R32 is both ")light", CS is "LOν"
It can be accessed under the following conditions.

(2) Registers that can be accessed via FIFO The registers and RAM that control drawing are FIFO (First I
n First 0ut).

The write FIFO has 32 words and the read FIFO has 8 words. Internally, each time one command is processed, the next command is transferred to the command register. FIG. 13 shows the detailed configuration of the drawing parameter register.

Next, the functions of each register will be explained based on FIG. 12. 6 (1) Address register (AR: Address
The address register (AR) is a register for specifying the address ($OOO to $IFF) of a control register inside the graphics processing device (GDP) 10. When writing to or reading from a control register, it is first necessary to write the address of the corresponding control register to the AR. Also, the I of this register
When the NC bit is set to 0, the address register is not updated, but when set to 1, the address register is updated by +2 each time the control register is accessed. As a result, when accessing the control registers continuously, it is only necessary to set the address registers first.

(2) Address/Write FIFO counter register (A
W F CR: Address/Write FI
FOCounterRegister) This register is an address register and a write FIFO.
This register reads the contents of the number of free words. The central processing unit 11 can use this register to know the set value of the address register, and by knowing the number of free words in the write FIFO, it can continuously transfer commands and parameters for that number of words to the write FIFO. I can do it big.

(3) Status register (S R: 5 status
The status register (SR) is a register that indicates the internal status of the graphic processing device 10.

The meaning of each bit is as follows.

◎Indicates the update (tJDT) timing and display control register rewriting permission period.

O Command DMA Complete (CD C: Command DMA Complete
te) In command DMA mode, command DMA
◎DMA error (
DER: DMA Error) Command DM
This flag is set when a GET or RD command is executed in A mode, indicating that the command DMA mode cannot be continued.

O Memory Protection Violation (MPV
: Memory Protection Viol
ation) When accessing the stack area of the frame buffer with the PAINT command, this indicates that the access has exceeded the stack area.

@Stop (STP: 5top) Indicates that the STOP command has been executed.

O Command error (CE R: Command Er
ror) An undefined command was executed, or there was an error between the coordinate space indicated by binary information and the coordinate space indicated by color information.
Indicates that the 00M command or ROT command was executed.

O area detection (ARD: Area Detect
) Indicates that the area was detected according to the drawing area test mode specification.

O Command end (CE D: Command En
d) Indicates the end of command execution or that the command is not being executed.

O Read FIFO Full (REF: Read FIFOFoil) Indicates that the read FIFO contains 8 words (16 bytes) of data and that it is impossible to execute any more data read commands.

When the data in the read FIFO is read, the RFP is cleared.

O Read FIFO Ready (RE F 2 Read FIFO Ready
) Indicates that data has been prepared in read FIF○. When all read FIFO data is read, RFR is cleared.

◎Write 1-PIF'O Ready (WFR: Write FIFOReady) Indicates that writing to the write FIF○ is possible. When 32 words (64 bytes) of data are written to the write FIF○, the VFR is cleared.

@Write FIFO Empty (WFE: Write FIFO Empty
; bit O) Indicates that the write FIFO is empty.

When data is written to the write FIF○, the WFE is cleared.

(3) Status register clear register (SRCR
: 5tatus Register C1ear R
egj, 5ter) The status register clear register (SRCR) is a register that clears each bit of the status register. By setting the bit corresponding to the bit that clears the status register to 1,
Each bit of the status register is reset. However, the status register RFF.

The RFR, WFR, and WFE bits cannot be reset using this register.

(4) FIFO entry (FE: FIFOEnt
ry) FIFO entry (FE) is a graphic processing unit (G
This is a register for writing commands/parameters to the DP) 10 and reading data from the graphic processing device 10. Each graphic processing device (GDP) 10 has a built-in 16-byte read FIFO and a 164-byte write FIFO, and the read FIFO is selected for reading, and the write FIFO is selected for writing. Commands are sequentially executed by writing commands/parameters to the write FIFO, and after the read commands are executed, read data is sequentially prepared in the read FIFO.

(5) Command Control Register (CCR)
ister) The command control register (CCR) is a register that controls command processing, and the meaning of each bit is as follows.

◎Abort (ABorT) O pose (
PSE: PauSE)O data DMA mode (DDM: Date Dn+a Mode)◎
Command DMA Mode (CDM)
◎DMA Transfer Request Control (DRC)
l) Graphic Bit Mod (GBM)
e) Graphic bit mode (GBM) is a bit that sets the bit configuration of pixel data handled by Graphic Processing Unit (GDP) 1.0. Six types of bit configurations can be selected, and a color (gradation) configuration suitable for the system can be easily realized.

◎Area mode (ARE A: Area Det
eet Mode) A mode for managing the drawing area.
It has the modes shown in Figure 4.

◎Continue mode (CN T: Comtin
ue Mode)O Main Memory Access Mode (MMA: Main Memory Access
Mode) O Data configuration conversion (DCT: Data Confil<ulati
on Transform) central processing unit 11 and graphic processing bag! This is a bit that specifies the conversion of the data structure when transferring data between 10 and 10 bits. By selecting this setting, various central processing units 11 and graphic processing device i\10 can be connected. FIG. 15 shows the types of conversion.

◎/J) Fraction setting (FRS: Fraction
5et) This is a bit that sets the fixed point position of the current pointer. The position of the decimal point can be set in the following four ways, allowing you to easily select the drawing accuracy of the figure.

@Write Only Mode (WTM: υrite 0nly Mode) When rewriting a single pixel in a system that has multiple pixels in one word, it is possible to rewrite one pixel by write operation only without performing a read/modify/write operation. This is a bit that specifies the mode in which it can be performed. This makes it possible to update one pixel in one memory cycle, thereby improving the drawing speed.

◎Memory data size (MDS)
) This is a bit that sets the data bus width of the frame buffer 14. By being able to independently set the frame buffer 14 side and the main memory 12 side when a part of the address space of the frame buffer 14 is allocated to the main memory 12, it is possible to cope with diversification of system configurations.

◎Timing control registers These registers are a group of registers that define the output conditions of synchronization signals, cursor display control signals, and two-screen control signals.

◎Display control registers These registers are a group of registers that control memory address output for one display.

Next, the function of the drawing parameter register will be explained based on FIG.

O color 〇 register (CL O: Co1or Reg
ister O) A register used when converting binary information such as pattern, line type, font data, etc. into color data, and sets the color data corresponding to "0" of the binary data.

◎Color Register (CL 1: Co1or Reg
ister 1) Similar to the color register, this register is used when converting binary information to color data.
Set color data corresponding to value data ``1''.

0 color comparison register (CCM P: Co1or CompariSon
Register) Defines the evaluation color for drawing operations. By selecting a color comparison mode, which will be described later, the specific color specified by this register can be set as a drawing-prohibited color or a changeable color.

@Edze Co1or Regis (EDG: Edze Co1or Regis
ter) Define the border color to limit the area in the PAINT condo. There are cases in which the color specified in this register is determined as the boundary color, and there are cases in which a color other than the color specified in this register is determined as the boundary color.

◎Read Mask Register (RMASK: Read Mask Rc4
ister) This is a register that specifies a color plane when only data of a specific color plane is selected from color data and binarized.

◎Write Mask Register (WMASK: Write Mask Re
gister) This is a register that specifies a color plane that will not be rewritten when drawing. It is possible to specify multiple planes for planes that cannot be rewritten. By using it in combination with the above-mentioned read mask register, copying between planes can be performed.

◎Patten Control Register (PTNC)
(Register) This is a register that defines an area for storing the fill pattern of the PAINT command and the fill command. Since it can be set on the frame buffer, the size of the area can be set freely.

This register consists of the following register groups.

(i) Pattern pointer (PPX, PPY) Indicates the reference point of the pattern area. The pattern area has its own pattern coordinate system relative to the drawing coordinate system.

(5) Pattern start position (FSX, PSY) The start point coordinates of the pattern area are expressed in the pattern coordinate system.

(iii) Pattern end position (PEX, PEY
) The end point of the pattern area is expressed in the pattern coordinate system.

(~) Pattern enlargement counter (PZCX.

pzCY) Indicates the count value of magnification when referring to the pattern.

This count value is determined as follows: 0≦p zcx≦pzx
, o≦pzcy≦PZY, and when the enlargement coefficient is reached, the pattern pointer moves.

(v) Pattern enlargement coefficient (pzx, pzy) Define an enlargement coefficient when referring to a pattern. 1 according to the designation from 0 to 15
~16x magnification.

◎Area Definition Register (A RD: Area Definition R
egister) Define the drawing area. Area management is performed according to the area mode described above.

O Drawing Mode Register (DMR: Drawing Mode RcHi
stsr) Specify the calculation mode, color comparison mode, color mode, and bell drawing mode for performing drawing calculations.

41"= of the drawing mode register in FIGS. 16 to 20,
Show the board. DMO is a register that is referenced by drawings other than the MC0PY command, and DMI is a register that defines an operation between transfer source data and pattern data in the MC0PY command. The DMO is referred to for calculation between the calculation result and the transfer destination data.

With these two registers, 256 logical operations can be defined in the M COP Y command.

CMWO and CMWI are registers that define the memory widths of the two drawing coordinate systems. Figure 21 shows the graphic processing bag h'
! 10 shows that by managing two coordinate systems, it is possible to transfer data between coordinate systems with different screen sizes. This allows systems that manage multiple windows to easily transfer data between windows.

◎Pattern Definition (PDR)
n Register) This is a register that defines the memory width of the pattern area. When the most significant bit is O, the pattern area is treated as color data, and when it is 1, it is treated as binary data.

0 pattern memory address register (PTNA: Pattern Memory
Address Register) This is a register that manages the memory address of the frame buffer for the pattern pointer (PPX, PPY) described above.

O Pel Memory Address Register (PLA: Pel Memory Address Register)
ss Register) When performing line drawing, the graphic processing device 1o can have a bell area that defines a shape corresponding to one pixel. Using this bell function, you can easily draw thick lines. FIG. 22 shows the definition of the bell region. Set the address corresponding to the bell origin in this register.

O Pel Control Register (PLC)
ter) This is a register that defines the size of the bell area.

The bell origin in Figure 22 is a point corresponding to the current pointer on the drawing coordinates, and the PLX
I, PLX2. PLYI, PLY2 define the size,
The shape of one pixel is defined within this range. 1 of this data
A bit corresponds to one pixel of the frame buffer 14. 0
The part marked 1 is ignored, and the part marked 1 is drawn based on line type information, which will be described later. That is, one bit of line type information selected for drawing one pixel is drawn in correspondence with the '1'' portion of the bell. Fig. 23 shows the relationship between the bell and the line type.

Since the current pointer moves in units of one pixel regardless of the shape and size of the bell, multiple overwriting is performed depending on the shape.

O line type control register (LSC: Line 5style control register)
l Register) This is a register that defines the line type information area when performing line drawing. Dotted lines etc. can be defined by changing the line type.

(i) Line type pointer (LSP) A pointer that indicates the reference point of the line type and moves in accordance with the current pointer.

(ii) Line type starting point (LSS) Indicates the starting point of the line type.

(iii) M type end point (LSE) Indicates the end point of a line type.

(ilI/) Line type enlargement counter (LSZC) Indicates the count value of the enlargement magnification when referring to the line type. This count value is counted in the range O≦LSZC≦LSZ as drawing is performed, and when the enlargement factor is reached, the line type pointer moves.

(v) Line type enlargement coefficient (LSZ) Defines the enlargement coefficient when referring to line types. Depending on the designation from 0 to 15, the magnification will be 1 to 16 times.

OFont Area Definition Register (FADR: Font Area Definition Register)
tion Register) This is a register that defines a character font area for bitmap character drawing.

Character fonts are defined in the address space of the frame buffer, so in addition to being placed on the frame buffer, the character font is also placed in the M M of the command control register (CCR) mentioned above.
By setting the A bit to "1", it is possible to arrange the font on the main memory.

(i) Font base address (FBAH).

FBAL) Define the memory address of the reference point of the font area.

(ji) Font bit number (FBN) Defines the total number of bits of the font for one character.

(iii) Font memory @ (FAMW) Defines the memory width of the font area.

(f-) Character spacing (DX, DY) Define character spacing.

(v) Character enlargement coefficient (ZX, ZY) Defines the enlargement/reduction ratio of one character when drawing one character with the CHR command. DX.

If it is larger than DY, it will be enlarged, and if it is smaller, it will be reduced. Since the X and Y directions can be defined independently, it is possible to draw characters that are enlarged in the X direction and reduced in the Y direction.

(vi) Font slant coefficient (XX) Defines the slant rate of a character when drawing one character using the CHR command 6. See the explanation of the CHR command below.

C internal RAM address (IRA R: Internal RAM Add
ress Register) Graphic processing bag F! 11. o
has an internal RAM of 512 bytes, and this R
AM can be accessed as a frame buffer address space.

The internal RAM address register is set with the starting address to be placed on the frame buffer. The internal RAM can be accessed faster than the frame buffer. Therefore, when the pattern area is small, processing speed can be improved by arranging the pattern in the internal RAM. On the other hand, when it is desired to expand the pattern area, all that is required is to change the pattern memory address (PTNA) mentioned above, and the use can be easily changed using only software. FIG. 24 shows the frame buffer 14, internal R
It shows the relationship between AMl0II, main memory 12, and frame buffer address space.

◎Stack start address (S S A R: 5tack 5tart Add
(res Register) When executing the PAINT command, the coordinate points that are being processed are stacked in the frame buffer. This register is a register that defines the start address of the stack area.

O stack area definition (S ADR: 5tack Area Definition)
(register) A register that defines the size of the stack area and can be set in units of 2n.

◎Stack pointer (SP: 5tack Po
1nter) Set the address for stacking.

◎Drawing Pointer O
) This is a register indicating the drawing memory address of the coordinate system O.

O Current pointer 0 (CPOX, CPOY: Current Po1n
ter O)O Drawing Pointer 1 (D P 1 : Drawing Pointer
1) This is a register indicating the drawing memory address of coordinate system 1.

◎Current pointer 1 (CP I X + CP I Y: Current
Po1nter 1) Indicates the drawing coordinates of coordinate system 1, D
These are the coordinates corresponding to Pl.

◎Drawing start coordinates (DSP: Drawing 5tart Po
1nt) Indicates the coordinate on the circumference at which drawing started in the ARC and EARC commands.

◎Drawing End Coordinates (DEP: DrawingEnd Point
) Indicates the coordinates on the circumference at which drawing has ended in the ARC and EARC commands.

Next, commands of the graphic processing device (GDP) 10 will be explained. 25 to 28 show a list of commands. Graphic processing bag! (GDP) 110 is, for example, Nikkei Electronics May 21, 1984 issue, p22.
Some of the commands mentioned on pages 1 to 254, some of the commands mentioned in Japanese Patent Application No. 60-201549 previously proposed by the applicant, and commands described later can be executed.

FIG. 29 shows an example of the operation of the PLINE command.

PLINEm? The command draws the section indicated by the parameters Zs, Ze, and Z of the straight line connecting the point indicated by the parameters Xt, Yt and the point indicated by the parameters Xz, Yz. Parameters Zs and Ze are
The value of the coordinate or the Y coordinate is restricted, and which coordinate value is restricted is set by parameter 2. Z=0
In the case of , the section whose X coordinate is from Zs to Ze is drawn,
When Z=1, the section whose Y coordinate is from Zs to Ze is drawn. By using this command, graphics processing devices (G
DP) 10.

Further, as the coordinate system for drawing, one of two coordinate systems can be specified by the parameter D.

", ', i'+ FIG. 30 shows an example of the operation of the FTRAP command.

"The F'TRAR command creates a line segment connecting the point indicated by parameters XI and Y1 and the point indicated by parameters X2 + YZ, the point indicated by parameters Xa and Ya,
Parameter X4. Fill in the area surrounded by a total of four straight lines: the line segment connecting the point indicated by Y4, the horizontal line indicated by the parameter Ys, and the horizontal line indicated by the parameter Ya using the figures stored in the pattern RAM. It is a command. By using these commands in combination, a figure made up of any polygon group can be filled with a pattern. Further, as the coordinate system for drawing, one of two coordinate systems can be specified by the parameter D.

FIG. 31 shows an example of the operation of the FARC-LN command. F
The ARC-LN command creates a quarter circular arc centered on the point indicated by parameters Xc, Yc, having a radius specified by parameter r, included in the area specified by parameter Z one, and parameter X1. The point indicated by Yl and the parameter X 2 .

The line segment connecting the point indicated by Y2 and the parameter Ys′
The area surrounded by a total of four lines, the horizontal line shown and the horizontal line shown by parameter Y6, is stored in the pattern RAM.
This is a command that fills in using shapes stored in . As the coordinate system for drawing, one of two coordinate systems can be specified by the parameter D.

FIG. 32 shows an example of the operation of the FPCRCL command.

The FPCRCL command calculates the area between the horizontal line indicated by the parameter Ys and the horizontal line indicated by the parameter Ye within a circle whose center is the point indicated by the parameters Xc and Yc and the radius specified by the parameter r. This is a command that fills in using the figures stored in the pattern area. As the coordinate system for drawing, one of two coordinate systems can be specified by the parameter D.

FIG. 33 shows an example of the operation of the FEARC-LN command.

The FEARC-LN command has parameters Xc, Yc
Centered on the point indicated by , X specified by parameter A
4 that has an axis radius, has a Y-axis radius specified by parameter B, and is included in the area specified by parameter Zone.
A line segment connecting the 1/1 elliptic arc, a point indicated by parameters XL and Yl, and a point indicated by parameters Xz and Yz,
This is a command to fill in the area surrounded by a total of four lines, the horizontal line indicated by the parameter Ys and the horizontal line indicated by the parameter Ye, using the graphic stored in the pattern area. As the coordinate system for drawing, one of two coordinate systems can be specified by the parameter D.

FIG. 34 shows an example of the operation of the FPELPS command.

The FPELPS command selects the horizontal line indicated by the parameter Ys within an ellipse centered on the point indicated by the parameters Xc and Yc, having the X-axis radius specified by the parameter A, and the Y-axis radius specified by the parameter B. 6 Drawing is a command that fills the area between the horizontal lines indicated by the parameter Ye and the horizontal line using the figures stored in the pattern area. Can be specified.

The above FTRAP, FARC-LN, FPCRCL.

By using the five commands FE ARC-L N and FPELPS in combination, a figure made up of arbitrary line segments, circular arcs, and elliptical arcs can be filled with a pattern.

FIG. 35 shows an example of the operation of the TEXT command. In a system where part of the frame buffer 14 is used as a character font area, the TEXT command transfers character font data corresponding to the input command code to the parameter X in the display area of the frame buffer 14.
This is a command that expands to the position indicated by Y. This is an internal register of the graphics processing device (GDP) 1o. Register FSAH that sets the start address of the font area.

FSAL, register FAMW that sets the memory width of the font area, registers FSX and FSY that sets the actual character width to be expanded, register FBN that sets the total number of bits for one character, and character spacing in the X direction. The register DX to be set and the register DY to set the character spacing in the Y direction are set in advance. After that, the central processing unit (CPU) 1
1 sequentially transfers the character code CN for n characters following this command and the coordinates X and Y to be expanded, followed by a parameter n that sets the number of characters to be expanded. Then, the graphic processing device (GDP) 10 calculates the address of each character font and develops the font.

Furthermore, this command can also change the expanded size on a character-by-character basis by specifying specific bits of the command code. An example of this operation is shown in FIG. 36. In the frame buffer 14, a font table and a table specifying the development size of each character are set. The table has
FSA indicating the number of bits in the left margin in the X direction of each character, and FSB indicating the number of bits from the left edge to the right edge of the character
have. The difference from the character development method described above is that the parameter FSX is not used for the development size in the X direction.

X-direction expanded size = FSB-FSA That is to say.

FIG. 37 shows a method of converting into color data in a TEXT command. Graphic processing equipment (GDP
) Color register 0, which is an internal register of 10, is set with color data corresponding to font data O, and color register 1 is set with color data corresponding to font data 1. The graphic processing device (GDP) 1.0 sequentially searches the read font data and writes the corresponding color data to the frame buffer 14.

FIG. 38 shows an example of the operation of the CHR command. In a system where a part of the frame buffer 14 is used as a character font area, the CHR command transfers character font data corresponding to the input command code to the position indicated by parameters X and Y in the display area of the frame buffer 14. This is a command to expand to . The rotation of characters can be set in 90'' units using the parameter SD.

This is an internal register of the graphics processing device (GDP) 10.

Register YRIF to set the start address of the font area
SAH, FSAL, register FAMW that sets the memory width of the font area, registers FSX, FSY that sets the actual character width to be expanded, register FBN that sets the total number of bits for one character, and the register FAMW that sets the memory width of the font area. buffer 1
4.Preset registers zx and zy to set the size of the actual characters to be expanded on the dots, and register XX to set the slant of the characters in the number of dots.0Setting whether the character is slanted to the right or to the left. is determined by the sign of Xx. Thereafter, the central processing unit (CPU) 11 transfers this command and the coordinates X and Y to be developed, followed by the character code CN to be developed. Then it's a graphic processing device! (GDP) 10 is
Calculate the address of each character font and expand the font. Further, the color development in the CHR command can be performed, for example, in the same manner as the color development in the T E 'X T command described above.

FIG. 39 shows an example of the operation of the MC0PY command.

The MC0PY command sets an absolute coordinate position from the origin indicated by parameters Xs and Ys and a relative coordinate position from that point indicated by parameters LX and L7 as two diagonal points in the frame buffer 14. After performing a logical operation on the data in the rectangular area parallel to the coordinate axes and the data stored in the pattern area, the data is further converted to the coordinate axes starting from the absolute coordinate position from the origin indicated by the parameters Xa and Ya. This command transfers data to parallel rectangular areas while performing logical operations on the data in the same area. FIG. 40 shows the scanning direction of the transfer source area of the MC0PY command. The scanning direction of the transfer source area is set using the signs of the parameters LX and LY and the parameter S.

FIG. 41 shows the scanning direction of the transfer destination area of the MC0PY command. Setting the scanning direction of the transfer destination area is parameter D.
This is done by SD. As the coordinate system of the transfer destination, one of the two coordinate systems is specified by the parameter D. Furthermore, the coordinate system of the transfer source may be either a different coordinate system than the transfer destination or a coordinate system the same as the transfer destination, using the parameter S. Specified by.

The graphic processing device 10 in this embodiment can process the highly functional command system as described above, and can significantly reduce the processing load on the central processing unit (CPU) 11.

As a result, it becomes possible to improve the performance of the graphic display device. Also, this graphic processing device! r! By providing ZIO as an LSI, it is also possible to reduce the cost of the graphic processing device.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that drawing can be performed at high speed even on the main memory using the second processor having a dedicated drawing function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 4 are block diagrams of other system configurations, FIGS. 5 and 6 are operation flow diagrams of memory access, and FIG. 7 is a block diagram of the present invention. 8 to 10 are block diagrams showing the internal configuration of the graphic processing device. FIGS. 11 to 24 are explanatory diagrams of functions of internal registers of the graphic processing device. 25
41 are explanatory diagrams of command functions of the graphic processing device. 10... Graphic processing device, 11... Central processing unit, 1
2... Main memory, 14... Frame buffer,
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Claims (1)

[Claims] 1. A first device that stores a program and information corresponding to pixels.
storage means; first processor means for executing the program transferred from the first storage means or the program transferred from another external device and managing and controlling the entire device; arranged in a multi-dimensional manner; an output means for outputting image information by controlling the pixels, a second storage means for storing information corresponding to the pixels output by the output means, and the first storage means or the second storage means for storing information corresponding to the pixels output by the output means; 1 receives commands and parameter information transferred from the first processor means, generates character and graphic data according to a predetermined processing procedure, and transfers the data to the first storage means or the second storage means. A graphics processing device comprising: second processor means for controlling; 2. connected to first and second address buses, first and second data buses, the first address bus and the first data bus, and stores programs and information corresponding to pixels; a first storage means connected to the first address bus and the first data bus to execute the program transferred from the first storage means or the program transferred from another external device; a first processor means for processing and managing and controlling the entire device; an output means for outputting image information by controlling pixels arranged in a plurality of dimensions; the second address bus and the second address bus; a second storage means connected to a data bus and storing information corresponding to pixels outputted by the output means;
and a bus connection control means for connecting or disconnecting the data bus and the second data bus; and commands and parameters transferred from the first storage means or the first processor means via the first address bus. information, and according to a predetermined processing procedure, controls the bus connection control means to connect the first and second address buses and the first address bus.
and the second data bus to access the first storage means, or between the first and second address buses and between the first and second data buses. A graphics processing device comprising: second processor means that accesses the second storage means by cutting off communication with the bus. 3. connected to first and second address buses, first and second data buses, the first address bus and the first data bus, and stores programs and information corresponding to pixels; a first storage means connected to the first address bus and the first data bus to execute the program transferred from the first storage means or the program transferred from another external device; a first processor means for processing and managing and controlling the entire device; an output means for outputting image information by controlling pixels arranged in a plurality of dimensions; the second address bus and the second address bus; a second storage means connected to a data bus and storing information corresponding to pixels outputted by the output means;
and a bus connection control means for connecting or disconnecting the data bus and the second data bus; and commands and parameters transferred from the first storage means or the first processor means via the first address bus. information, generates character and graphic data according to a predetermined processing procedure, controls the bus connection control means, and connects the first address bus with the second address bus.
and the second data bus, and the above characters,
Transferring the graphic data to the first storage means, or cutting off between the first and second address buses and between the first and second data buses, A graphics processing device comprising: second processor means for transferring graphic data to the second storage means. 4. Claim 2, comprising a plurality of sets consisting of a second processor means, a second address bus, a second data bus, a second storage means, and a bus connection control means, A read access from the first storage means may be performed by address information supplied from one of the plurality of second processor means, and the read data may be read into the plurality of second processor means in parallel. 1. A graphic processing device characterized in that said plurality of bus connection control means are controlled. 5. A storage means for storing information on a pixel basis, and a processor means for sequentially generating addresses corresponding to pixels and accessing the storage means to generate graphic information decomposed on a pixel basis, the processor means It has an auxiliary storage means for storing pattern information consisting of a plurality of pixels, and each time the address of each pixel obtained by dividing a line into pixel units is calculated in sequence, the auxiliary storage means stores information in an area based on the pixel address. 1. A graphic processing device characterized in that a thick line is drawn by drawing pattern information stored in the drawing and repeating this process. 6. A first storage means for storing information in pixel units, and a processor means for sequentially generating addresses corresponding to pixels and accessing the storage means to generate graphic information decomposed into pixel units. , The processor means includes an auxiliary storage means for storing pattern information to be referred to when drawing is executed, a drawing pixel address generation means, and a signal for decoding part of information of the pixel address and selecting the auxiliary storage means. a decoding means for outputting a drawing address, and when the auxiliary storage means is selected, outputting the drawing address to the first storage means is prohibited. 7. A storage means for storing information in units of pixels, and a processor means for accessing the storage means to perform graphical processing, and for defining at least two X-Y coordinate spaces in the storage means. - has two types of parameters that define the correspondence between the Y coordinate origin and the pixel address of the storage means;
A graphic characterized in that the processor means generates an address in order to transfer area data defined within an X-Y coordinate space of a second X-Y coordinate space to an area defined within a second X-Y coordinate space. Processing device 8 A graphic processing device according to claim 7, characterized in that the number of horizontal pixels for the first and second X-Y coordinate spaces can be independently defined. 9. The graphic processing device according to claim 7, wherein the number of bits per pixel can be independently defined for the first and second X-Y coordinate spaces. . 10. A storage means for storing information in pixel units, and a processor means for sequentially generating addresses corresponding to pixels and accessing the storage means to generate graphic information decomposed into pixel units, the processor means The method is characterized in that a straight line is defined by two X-Y coordinate parameters, and the drawing is controlled only in the section defined by two parameters, a drawing start pixel number and a drawing end number, in the straight line. A graphics processing device. 11. It has a storage means for storing information in pixel units, and a processor means for accessing the storage means to generate graphic information, and the processor means generates two lines according to four X-Y coordinate parameters. An arbitrary straight line parallel to two X-axes is defined by two Y-coordinate parameters, respectively, and drawing is performed in an area surrounded by the four straight lines. graphics processing unit. 12. It has a storage means for storing information in pixel units, and a processor means for accessing the storage means to generate graphic information, and the processor means generates a right semicircular arc or a left semicircular arc based on the center coordinates and the radius. Define a semicircular arc, one straight line by two X-Y coordinate parameters, and two straight lines parallel to the X axis by two Y coordinate parameters, and define the semicircular arc and three straight lines. 1. A graphic processing device characterized in that drawing is performed within an area surrounded by . 13. Comprising a storage means for storing information in units of pixels, and a processor means for accessing the storage means to generate graphic information, the font pattern of the characters, the horizontal reference start position and the horizontal reference end position for each character. Information consisting of a position is stored in the storage means, and the processor means draws only the section sandwiched between the horizontal reference start position and the horizontal reference end position of the font pattern of the specified character. A graphics processing device characterized by: