JPH01241619A - Multi-window processor - Google Patents

Abstract

PURPOSE:To apparently improve a multi-window display speed by using two-port memory as a window memory and executing the transferring of multi-window data from the window memory through an exclusively used bus to a picture memory. CONSTITUTION:When a window data transferring control signal is supplied from a control means to a window memory 3, the window data of a designated RAM area 3R are internally transferred to an SAM area 3S and after that, the data can be transferred through an exclusively used bus 6 to the prescribed area of the picture memory. Namely, the two-port memory is used as the window memory 3 and the window data are transferred from the window memory 3 through the exclusively used bus 6 to the picture memory. Thus, even while the transferring operation of the window data is executed, the picture data to be outputted from a processor 1 can be written to the window memory 3 and the apparent multi-window display speed can be extremely improved.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a multi-window processing device, and more specifically, the present invention relates to a multi-window processing device that processes multi-window image data by transferring image data stored in a window memory to an image memory. The present invention relates to a multi-window processing device that generates a multi-window processing device.

<Prior art> Conventionally, in graphic display devices,
There is a strong demand for multi-functionality, and as part of this multi-functionalization, graphic display devices equipped with multi-window functions are becoming widely available.

FIG. 4 is a block diagram showing the schematic configuration of such a graphic display device, which includes a processor (31) that generates control data, image data, address data, etc.
Image data can be transferred to a window memory (33) consisting of a random access memory (hereinafter referred to as RAM) through a processor bus (32) connected to the image memory (hereinafter referred to as RAM). Image data can also be transferred to (34) (referred to as frame memory). Then, a controller (35) which receives the address data and control data supplied from the processor (31) as input supplies sequentially changing address data and control signals to the window memory (33), and Address data and control signals are also supplied to the frame memory (34).

Note that (3B) is a cathode ray tube display device (hereinafter abbreviated as CRT display device) that performs visual display by being supplied with image data stored in a frame memory (34).

To explain in more detail, the window memory (33
) is supplied to the processor (31).
It consists of a write control signal that controls the operation when writing image data supplied from the window memory (33), and a transfer control signal that controls the operation when reading the image data from the window memory (33). The signal is output selectively.

Further, the control signals supplied to the frame memory (34) include a write control signal for controlling the operation when writing image data supplied from the processor (31) or the window memory (33); Frame memory (34
), and a transfer control signal for controlling the operation when reading image data from ), and one of the signals is selectively output.

FIG. 5 is a block diagram schematically showing the main parts of the controller (35), in which the parameter register (37) receives parameter data supplied from the processor (31) and outputs read start address data and read size data. ), a size counter (38) which receives read size data as input and sequentially outputs access pulse signals of a number corresponding to the size, and receives the read start address data and access pulse signal as input and outputs sequentially changing access address data. It consists of an address counter (39) and an access controller (40) which receives the access pulse signal as input and outputs a transfer control signal. The access address data and transfer control signal are then supplied to the window memory (33).

The operation when visually displaying a multi-window image using the graphic display device having the above configuration is as follows.

When writing window data to the window memory (33), the controller (35) is sent from the processor (31) to the window memory (33).
) by supplying control data and window data write address data to the controller (3).
5) supplies a data write control signal and data write address data to the window memory (33). Then, the window memory (33) is passed from the processor (31) to the processor bus (32).
), the window data can be written into a predetermined memory area.

When reading the window data written in the window memory (33) to perform multi-window display, the necessary parameter data can be supplied from the processor (31) through the processor bus (32), and then the controller Under the control of (35), window data is transferred as follows.

That is, the address counter (39) is initialized by the read start address output from the parameter register (37), and the size counter (38) is initialized by the read size data.

The size counter (38) outputs an access pulse signal at predetermined time intervals until the initialized size data becomes 0, and the address counter (38) outputs an access pulse signal at a predetermined time interval until the initialized size data becomes 0.
In step 9), the read start address data is set as an initial value, and access address data that changes each time an access pulse signal is supplied is output.

Therefore, the window data read address of the window memory (33) is specified by the access address data, and since the access pulse signal is input and the transfer control signal is supplied from the access controller (40), the data can be stored in the desired window area. It is possible to read out the window data continuously.

Since the window data that is continuously read out is transferred to the frame memory (34) through the processor bus (32), the contents of the frame memory (34) are then transferred to the CRT display device (3B). , it is possible to visually display multi-windows.

<Problems to be Solved by the Invention> In the graphic display device having the above configuration, a window memory (33) and a frame memory (34) are used.
), the window data is transferred while occupying the processor bus (32), so no other processing involving data exchange can be performed until the transfer operation is completed. There is a problem in that the operating efficiency of the processor (31) is significantly reduced.

To explain in more detail, in a graphic display device, while image data is visually displayed on the CRT display device (3B), the next image data is generated and stored in the window memory (33) or frame memory. (34
), the overall apparent display speed is improved. However, when performing multi-window display, the window memory (3
When the window data is transferred from 3) to the frame memory (34) while occupying the processor bus (32), new image data is transferred to the window memory (33) or frame memory (34) during that time. Since the window data cannot be transferred and is transferred only after the window data has been transferred, the overall apparent display speed is reduced.

Also, the window memory (33) is the frame memory (33).
Unlike 4), the entire image data is not read out continuously, but only the window data stored in a predetermined window area is read out continuously, so it is composed of one boat of RAM. .

As a result, there is a problem in that the window data write operation and the window data read operation to the window memory (33) cannot be performed simultaneously. Even if a dedicated bus is provided to transfer window data from the window memory (33) to the frame memory (34), new window data cannot be written until after the window data transfer is completed. There is a problem in that the apparent multi-window display speed cannot be improved.

Furthermore, the above controller (35) not only needs to generate access address data that changes sequentially, but also needs to generate a transfer control signal, so the overall configuration is extremely complicated. The problem is that it becomes

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a multi-window processing device that can improve the apparent multi-window display speed and simplify the configuration.

Means for Solving the Problems> To achieve the above object, the multi-window processing device of the present invention has a window memory configured as a two-port memory cell, and a sequential access port of the window memory and an image memory. A dedicated bus connects the two, and a control means is provided for supplying a window data transfer control signal to the window memory.

However, it is preferable that the control means also outputs a control signal to a selector for selecting the state of image data transfer by the processor bus and the dedicated bus, and a control signal to the image memory.

Preferably, the window data transfer control signal is a transfer start address signal and an access control signal from the random access section to the sequential access section of the window memory, and in this case, the control means includes a transfer start address signal and an access control signal. It is preferable to have a register that outputs the window size data and a size counter that outputs the number of access pulse signals corresponding to the window size by holding window size data.

Function> With the multi-window processing device having the above configuration, window data can be stored in a predetermined RAM area of the window memory through the processor bus. When a window data transfer control signal is supplied from the control means to the window memory, the window data in the designated RAM area is internally transferred to the SAM area, and then transferred to a predetermined area in the image memory through the dedicated bus. be able to.

That is, since a 2-port memory is used as the window memory and the window data is transferred from the window memory to the image memory through a dedicated bus, while the window data is being transferred, Also, the image data output from the processor can be written into the window memory, and the apparent multi-window display speed can be significantly improved.

If the control means outputs a control signal to a selector for selecting the state of image data transfer by the processor bus or dedicated bus, and a control signal to the image memory, it is possible to display not only a multi-window display but also a normal one. It is also possible to display images, and
When performing multi-window display, the apparent multi-window display speed can be significantly improved in the same manner as above.

Furthermore, if the window data transfer control signal is a transfer start address signal and access control signal from the random access section to the sequential access section of the window memory, the address counter for sequentially changing the access address data may be omitted. The configuration of the control means can be simplified. In this case, if the control means has a register that outputs a transfer start address signal and a size counter that holds window size data and outputs access pulse signals of a number corresponding to the window size, A similar effect to that described above can be achieved.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram schematically showing the configuration of a graphic display device incorporating the multi-window processing device of the present invention.

Image data can be transferred to the RAM section (3R) of a window memory (3) consisting of a two-port memory through a processor bus (1) connected to a processor (1) that generates control data, image data, address data, etc. At the same time, image data can also be transferred to a frame memory (4) consisting of a RAM. The controller 6), which receives the address data and control data supplied from the processor (1), supplies sequentially changing address data and control signals to the window memory (3), and Address data and control signals are also supplied to the memory (4). In addition, the window data read from the SAM section (3S) of the window memory G) is sent to the frame memory (4) through the dedicated bus (6).
I am trying to transfer it to.

Note that (7) is a selector for selecting image data transferred through the processor bus (2) and window data transferred through the dedicated bus (6), and (8) is a selector that is stored in the frame memory (4). A CRT display device performs visual display by being supplied with image data. The selection state of the selector σ) is controlled based on a control signal supplied from the controller (5).

To explain in more detail, the above window memory (3)
The control signals supplied to the processor (1) include a write control signal that controls the operation when writing the image data supplied from the processor (1), and a write control signal that controls the operation when reading the image data from the window memory (3). It consists of a transfer control signal and a transfer control signal.

Further, the control signal supplied to the frame memory (4) is also sent to the processor (1) or the window memory (
It consists of a write control signal that controls the operation when writing the image data supplied from the frame memory (4), and a transfer control signal that controls the operation when reading the image data from the frame memory (4). This signal is selectively output.

FIG. 2 is a block diagram showing the main parts of the controller (5), which holds parameter data supplied from the processor (1) and outputs read start address data and read size data based on the parameter data. It consists of a register (9) and a size counter 00 which is initialized by read size data and sequentially outputs access pulse signals of the number corresponding to the read size data at predetermined time intervals.

The operation of the graphic display device having the above configuration is as follows.

When performing normal image display operations, use the controller
By controlling the selector so that the image data is transferred to the frame memory (4) through the processor bus ■, and sequentially writing the image data output from the processor (1) to the frame memory (4), Usually, by transferring the image data written in the frame memory (4) to the CRT display device [F]), normal image display can be performed.

When performing multi-window display, the controller (5) should control the selector (7) so that the window data is transferred to the frame memory (4) through the dedicated bus (6), as shown below. You can use it to display multiple windows.

That is, in the state where the selector is controlled as described above, the necessary parameters etc. have been supplied to the controller 6) from the processor (1) in advance, so the read start address data is output from the parameter register (9). By supplying the data to the RAM section (3R) of the window memory C3), the RAM section (3R) and the SAM section (3S
) can perform internal data transfer between the two. Since the size counter () is initialized based on the read size data output from the parameter register (9), access pulse signals are sequentially output at predetermined time intervals, and the S of the window memory (3) is initialized.
Each time the data is supplied to the AM section (3S), the internally transferred data is sent out to the dedicated bus (e).

As a result, the window data output from the SAM section (3S) is transferred to the frame memory (4) through the dedicated bus (6) and the selector. Based on the contents of the frame memory (4), multi-window visual display can be performed by the CRT display device (8).

Furthermore, while the above series of operations is being performed, the processor bus (2) is not occupied at all, and since the window memory G) is a 2-port memory,
Window data generated in the processor (1) is stored in the window memory G) without interfering with window data transfer to the frame memory (4).

Therefore, the apparent multi-window display speed when changing the contents of multi-window display can be significantly improved. Furthermore, the configuration of the controller (2) for controlling window data reading from the window memory (3) can also be simplified.

FIG. 3 is a block diagram showing another embodiment of the main part of the controller (5), in which a coordinate value latch circuit holds the coordinate value of the read start address in the scan line direction (hereinafter abbreviated as the X coordinate value). (11) and the scan line direction (
A size latch circuit (12) that holds read size data in the X-axis direction (hereinafter abbreviated as the X-axis direction), and a size latch circuit (12) that holds the read size data held in the size latch circuit (12) and the direction perpendicular to the scan line (hereinafter referred to as the Y-axis direction). A size counter (ta) (14) whose readout size data (abbreviated as "direction") is set as an initial value and whose contents are decremented by 1 each time a timing signal is supplied, and a coordinate in a direction perpendicular to the scan line. A coordinate value counter (15) whose value (hereinafter abbreviated as y-coordinate value) is set as an initial value and whose contents are incremented by 1 each time a timing signal is supplied, and both size counters (1B) (14) The size 0 signal output from the processor (1) and the parameter latch signal supplied from the processor (1) are used as input to generate a timing signal to be supplied to the size counter (14) and coordinate value counter (15), and this timing signal is input to the size counter (14) and the coordinate value counter (15). (13) as a load signal, and a parameter latch signal supplied from the processor (1) and window data supplied from the window memory port) to process continuous data. and a continuous data processing section (17) that generates a timing signal to be supplied to the size counter (13) at a predetermined timing.

The operation when performing multi-window display using the controller 6) having the above configuration is as follows.

When window data is stored in the window memory (3), the processor (1) sends the X-coordinate value and y-coordinate value of the read start address, the read size data in the X-axis direction, the read size data in the y-axis direction, and By supplying the parameter latch signal, window data can be read from the corresponding area of the window memory and transferred to the frame memory (4) through the dedicated bus (6) and selector (2) as follows.

That is, by supplying the parameter latch signal,
The X coordinate value of the above read start address and the read size data in the X axis direction are respectively stored in the coordinate value latch circuit (11).
, is held in the size latch circuit (12), and a coordinate value counter (15) is initialized based on the y-coordinate value of the read start address, and the size counter (15) is initialized based on the read size data in the y-axis direction. (14) is initialized. Furthermore, since the control signal generation section (1B) supplies a load signal to the size counter (13), initial settings are performed based on the data held in the size latch circuit (12). Note that since a timing signal is supplied to the coordinate value counter (15) and size counter (14), the contents of each are increased or decreased by 1.

Then, the contents of the coordinate value counter (15) are supplied to the window memory G) as the upper data of the read address, and the contents of the coordinate value latch circuit (11) are supplied to the window memory G) as the lower data of the read start address. By supplying the pulse signal output from the size counter (13) as an access pulse signal to the window memory (3), a predetermined number of bits of data are read out, and the continuous data processing unit (17), dedicated It is supplied to the frame memory (4) through the bus (6) and the selector.

When the above operation is performed, a timing signal is supplied from the continuous data processing unit (17) to the size counter (13), so the size data is decreased by 1 and the pulse signal is output again. Then, the next predetermined number of bits of data are read out. Thereafter, by repeating the above operations, necessary data on the same scan line can be read.

When all the necessary data on the same scan line is read out, the contents of the size counter (13) become 0, so a signal indicating that the size data has become 0 is sent to the control signal generation unit (1B). Supply and size counter (13
) and supplies the load signal to the coordinate value counter (
15) and a size counter (14). As a result, the size counter (13) is again initialized with the same size data as the previous time, the contents of the coordinate value counter (15) are incremented by 1, and,
The contents of the size counter (14) are decremented by one.

Then, a series of window data read operations are performed again based on the same X-coordinate value and size data in the X-axis direction as before, the X-coordinate value increased by 1, and the size data in the y-axis direction decreased by 1. will be carried out.

Thereafter, window data corresponding to the required number of scan lines are similarly read from the window memory (3) and transferred to the frame memory (4) in the order of reading.

Then, when the window data corresponding to all the necessary scan lines is read out, the size counter (1
Since a signal indicating that the content has become 0 is also supplied from 4) to the control signal generation unit (1B), the subsequent sending operation of the load signal and timing signal is stopped and preparation is made for the next window data read operation. .

As is clear from the above explanation, when reading window data for multi-window display, the processor (1) only needs to read the X coordinate value of the read start address, the X coordinate value, and the X axis direction. It is only necessary to supply the size data and the read size data in the y-axis direction, and then the coordinate value latch circuit (11) and the size latch circuit (
12), window data can be read out based on the contents of the size counter (14) and coordinate value counter (15). Since the read window data is transferred to the frame memory (4) through the dedicated bus (6) and selector (7), the processor (1) can perform arbitrary processing without being affected by the window data transfer. Processing can be performed, and data can also be sent and received through the processor bus (2). Therefore, while any window data is being transferred to the frame memory (4), other window data can be generated by supplying necessary data to the window memory (3) through the processor bus ■. As a result, the time required for multi-window processing can be significantly reduced.

It should be noted that the present invention is not limited to the above-mentioned embodiments. For example, by providing a coordinate value counter that is initially set based on the contents of the coordinate value latch circuit (11), X coordinate data that is sequentially changed can be used. In addition to being able to generate and supply write address data to the window memory (3) and frame memory (4), conventional multi-window processing It is possible to employ the same access address data generation means as the device, and various other design changes can be made within the scope of the invention.

<Effects of the Invention> As described above, the first invention has two functions as a window memory.
In addition to using port memory, window data is transferred from window memory to image memory through a dedicated bus, so even while window data is being transferred,
Image data output from the processor can be written into the window memory, and the apparent multi-window display speed can be significantly improved, which is a unique effect.

The second invention can perform not only multi-window display but also normal image display, and when performing multi-window display, the apparent multi-window display speed is the same as in the first invention. can be significantly improved.

The third invention has the unique effect that an address counter for sequentially changing access address data can be omitted, and the configuration of the control means can be simplified.

The fourth invention is to simply hold the transfer start address signal in a register and initialize the size counter with window size data, and then output an access pulse signal from the size counter to sequentially read out the window data. This can improve the apparent multi-window display speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram schematically showing the configuration of a graphic display device incorporating the multi-window processing device of the present invention, Fig. 2 is a block diagram showing the main parts of the controller, and Fig. 3 is the main part of the controller. FIG. 4 is a block diagram showing a schematic configuration of a conventional graphic display device; FIG. 5 is a block diagram schematically showing main parts of a controller. (1)...Processor, ■...Processor bus, G
)...Window memory, (4)...Frame memory, ■...Controller, (6)...Dedicated lotus, (
7)...Selector, ■)...Parameter register,
■)...Size counter, (3R)...RAM section,
(3S)...SAM Department Patent Applicant Daikin Industries, Ltd.

Claims (1)

[Claims] 1. A multi-window processing device that generates multi-window image data by transferring image data stored in a window memory to the image memory, wherein the window memory is configured with a two-port memory, and A multi-window processing device, characterized in that a sequential access port of a window memory and an image memory are connected by a dedicated bus, and furthermore, a control means is provided for supplying a window data transfer control signal to the window memory. . 2. The control means sends a control signal to a selector that selects the state of image data transfer by the processor bus or dedicated bus;
The multi-window processing device according to claim 1, wherein the multi-window processing device also outputs a control signal for the image memory. 3. The multi-window processing device according to claim 1 or 2, wherein the window data transfer control signal is a transfer start address signal and an access control signal from a random access section to a sequential access section of the window memory. 4. The above claims, wherein the control means includes a register that outputs a transfer start address signal and a size counter that holds window size data and outputs a number of access pulse signals corresponding to the window size. The multi-window processing device according to item 3.