JPH02119173A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the leakage current of a p-n junction and save the power consumption and realize high speed operation by a method wherein a first buried impurity layer of p-type which is the conductivity type of a substrate and an n-type second buried impurity layer are formed and the higher maximum impurity concentration is given to the second impurity layer. CONSTITUTION:After an element isolation oxide film 5 is formed on a substrate 4, boron B ions are implanted to form a B-implanted layer 6. Then a first buried impurity layer 7 of p-type which is the conductivity type of the substrate 4 is formed and, in a region deeper than the layer 7, a second buried layer 8 having the higher maximum impurity concentration is formed. If the impurity is activated by annealing in a nitrogen atmosphere, the layer 6, layer 7 and layer 8 are turned into a p-type layer, a p-type buried layer and an n-type buried layer respectively. Then As ions are implanted and a high impurity concentration n-type region 9 is formed in the surface of the substrate 4 by annealing to form a p-n junction. With this constitution, the surface integral of the leakage current of the p-n junction can be suppressed and the power consumption of an LSI can be saved and the high speed operation of the LSI can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor device and a method for manufacturing the same that reduce leakage current of a pn junction used by applying a reverse bias, such as a drain junction in a MOS-FET. It is related to.

[Conventional technology]

Traditionally, for example, Nuclear Instruments and Methods in Physics Research (Nucle
ar Instruments and Methods
es in Physics Research) B
21 (L 987), pages 163 to 167, in order to suppress the latch-up phenomenon in CMO8 elements and to prevent α-ray soft errors, a p-type semiconductor substrate similar to that of the substrate is installed inside the p-type semiconductor substrate. A buried layer of impurities was formed.

By providing a high-concentration impurity physical layer inside the substrate and lowering the resistivity of the substrate, it is possible to suppress the parasitic thyristor that occurs in the CMO8 element, and to suppress the latch-up. Since electrons generated by the incidence of α-rays are blocked by the highly concentrated buried layer and cannot reach the active region on the substrate surface, soft errors are less likely to occur.

In addition, I.E.E.
On own electron e device ease.

E.D.-29 (1982) pp. 725-731 (
IEEE Trans, Electron D
evices ED29 (1982) pp, 725-7
As described in 31), soft errors can be suppressed more effectively by providing a grid-shaped buried layer on the n-type opposite to the substrate. That is,
Excess electrons generated deep in the substrate by α rays are collected in the n-type grid portion and do not reach the active region on the substrate surface, thereby suppressing soft errors.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology was developed to suppress soft errors and latch-up, and no consideration was given to reducing the leakage current of the pn junction, such as the drain, included in the device. current,
It was difficult to achieve the same level or less compared to the case where a buried impurity layer is not formed. If the leakage current at the junction cannot be reduced, problems such as slowing down the operating speed of the large-scale integrated circuit will occur.

An object of the present invention is to provide a semiconductor device that suppresses soft errors and latch-up while simultaneously reducing pn junction leakage current, and thereby enables high-speed operation of large-scale integrated circuits. It is in.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as shown in FIG. Forming a second buried layer 3 of the opposite conductivity type 6 Also, in the present invention, the buried impurity layer is formed in a planar shape, and the maximum impurity concentration of the second buried impurity layer 3 is set to be the same as that of the first buried impurity layer. It is important that the impurity concentration be equal to or higher than the maximum impurity concentration of No. 2.

Such first and second buried impurity layers 2.3 can be formed using ion implantation.

[Effect]

The reason why the problem is solved by using the above method will be described below.

By providing a second buried impurity layer of a conductivity type opposite to that of the substrate inside the substrate, a shallower region near the substrate is electrically insulated from the lower layer of the substrate, resulting in a substantially thinner substrate. It becomes equivalent to that. By forming the second buried impurity layer to an appropriate depth, the thickness of this substrate surface layer can be made shorter than the diffusion length of minority carriers in the substrate.

As a result, the diffusion current flowing through the pn junction formed on the substrate surface at the time of reverse bias is smaller than the diffusion current when the substrate is sufficiently thick, which has the effect of reducing the leakage current of the pn junction. When the second buried impurity layer is formed in a grid shape.

Since carriers flow to the lower layer of the substrate through the holes in the grid, the effect of forming the buried impurity layer is greatly reduced.Therefore, the second buried impurity layer must be formed in a planar shape.

In the present invention, a parasitic bipolar transistor is generated which is constituted by the substrate surface layer, the second buried impurity layer, and the substrate lower layer. When this parasitic bipolar transistor operates, it has an adverse effect on the device, so it is necessary to suppress its operation. To this end, as in the case of suppressing latch-up, the impurity concentration of the second buried impurity layer may be increased to lower the current amplification factor of the parasitic bipolar transistor. The impurity concentration may be equal to or higher than the impurity concentration of the first buried impurity layer.

Further, the second buried impurity layer is effective in suppressing soft errors, similar to the grid-shaped buried layer in the latter prior art described above.

By forming the first and second buried impurity layers by ion implantation, the first and second buried impurity layers can be formed precisely and easily.

Note that when ion implantation is performed in the present invention, damage caused during ion implantation can be recovered by subsequent annealing.
- When implantation is performed, the leakage current (which is an indicator of ion implantation damage) decreases as the annealing temperature increases, and at temperatures above 900°C, the amount of leakage current is equivalent to that without ion implantation. The annealing time is preferably about 30 minutes or more.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 2 to 7.

(Example 1) FIG. 2 shows an outline of the manufacturing process when the present invention is applied to a pn junction diode.

A well-known LOG is placed on a p-type Si substrate 4 with a resistivity of 10 Ωcm.
After forming the element isolation oxide film 5 by the O8 element isolation process, the implantation energy was 70°140.300 and 450°.
keV, implantation amount at each energy is 2.5
10”1.8 x 1011.4.5 x 1011.
and 3.5 x 10” and 3.5 x 1011 cm
-" multiple boron (B) ion implantations to a depth of 1
By implanting IX10"cm-" of B into an area of 1 μm or less in depth, IXl0"am-' of B implantation into an area of 1 μm or less in depth.
A implanted layer 6 was formed (FIG. 2a).

After that, B ion implantation was performed at 0.8 MaV and 2X10"am-" to achieve a maximum impurity concentration of 3XI Q17cm.
-'', a B buried layer 7 whose impurity concentration reaches its maximum at a depth of 1.5 μm was formed (FIG. 2b).

After that, the phosphorus (P) ion is given an energy of 3 M e
2x10"cm-" implanted with V, maximum impurity concentration is 8x1
011cm-'', a P buried layer 8 was formed in which the impurity concentration reached its maximum at a depth of 3 μm (FIG. 2G).

Next, annealing was performed at 950° C. for 30 minutes in a nitrogen atmosphere to activate the implanted impurities. At this time, the multiple B implantation layer 6 is implanted into the p-type layer, the B buried layer 7 is implanted into the p-type buried layer, and further P is implanted into the p-type buried layer, and annealing is performed at 950° C. for 10 minutes in a nitrogen atmosphere to form the substrate. A high concentration n-type region 9 was formed on the surface of 4 to form a pn junction (
Figure 2 d).

After that, a passivation film 10 is formed using a well-known method.
An AI2 electrode 11 was formed (FIG. 2e).

FIG. 3 shows the depth distribution of carrier concentration in this example.

FIG. 4 shows a comparison of the area components of leakage current (leakage current flowing through the lower surface of the junction) of the pn junction diodes formed according to this embodiment and the conventional technique.

It can be seen that the area component of leakage current is reduced by approximately 1/3, and that the present invention is effective in reducing leakage current.

The characteristics of the diode were investigated by changing the implantation energy of P ions and changing the depth at which the impurity concentration of the n-type buried layer 8 was maximum between 1.7 and 6 μm. the result,
It has been found that when the brightness is 2 μm or less, the breakdown voltage of the junction between the p-type buried layer 7 and the n-type buried layer 8 is reduced. Furthermore, at a depth of 4.5 μm or more, the formation of the n-type buried layer 8 was not very effective in reducing leakage current.

As a result, the n-type buried layer 8 can be formed so that the impurity concentration reaches its maximum in a region 0.5 to 3 μm deeper than the depth at which the impurity concentration of the p-type buried layer 7 reaches its maximum.
found to be the most effective.

(Example 2) Next, an example in which the present invention is applied to a CMO8 element will be described with reference to FIG.

A well-known LOG is placed on a p-type Si substrate 4 with a resistivity of 10 Ωcm.
After forming a pre-element oxide film 5 through an O8 element isolation process, P ions are implanted into a predetermined region of the Si substrate 4 at 100 keV with a thickness of 4 x 10 cm, and annealing is performed at 1150°C for 1200 minutes to form an n-type Region 12 was formed. Then,
A p-type Si region 6 and a p-type buried layer 7 are formed in the region of the Si substrate 4 where the n-type region 12 is not formed by a step using the same ion implantation conditions and annealing conditions as in Example 1. 8 was formed (Fig. 5a).

Thereafter, a 15 nm gate oxide film 13 was formed using a conventional thermal oxidation method, and a phosphorus-doped polycrystalline Si gate electrode 14 was formed using a vapor phase chemical growth method and a photoetching method. After that, As ions were applied to the p-type S↓ region 6 at 80 keV.
5XIQ am”-i implant, n-type Si region 1
2 with B ions at 20 keV.

After 5×10 cm implantation, annealing was performed at 900° C. for 10 minutes to form n-channel MO3FETs in each of the p-type and n-type Si regions at 6°12. After that, passivation film 10 and AQ wiring 11 are formed and 0M0
Eight circuits were created (Figure 5b).

According to this embodiment, the n-channel M formed in the region 6
The leakage current of the source and drain junctions of the O3FET was reduced to about 173, which was effective in reducing the power consumption of the circuit.

(Example 3) A third example in which a d-RAM was created using the present invention will be described using FIG. 6.

A p-type Si layer 6, a p-type buried layer 7, and an n-type buried layer 8 were formed on the p-type Si substrate 4 using the same steps as in Example 1 above. Thereafter, B ions were implanted at 150 kaV to a depth of 1 x 10 "am-" in the region where the charge storage capacitor was to be formed, and As ions were implanted to a depth of 5 x 10 "cm" at 50 keV, followed by annealing at 950°C for 30 minutes. A type layer 16 and an n-type layer 17 were formed. Thereafter, a 20 nm gate oxide film 13 and a 350 nm phosphorus-doped polycrystalline Si electrode 14 were formed, and a 5×10” c
As ion implantation was performed under the conditions of 950℃, 1
0/70 annealing was performed to form n-type source/drain regions 9. Thereafter, a passivation film 10 and AQ wiring 11 were formed to create a d-RAM.

According to this embodiment, it is possible to reduce the leakage current of the switching MO8FET and the pn junction of the capacitor, making it difficult for the charge stored in the memory cell to dissipate, and increasing the information retention time by about 20%. was completed.

This made it possible to lengthen the refresh cycle and increase the access speed of the circuit.

(Embodiment 4) An example in which the present invention is applied to a Schottky junction diode will be described using FIG. 7.

By the same process as in Example 1 above, a p-type Si layer 6, a p-type buried layer 7. An n-type buried layer 8 was formed. Thereafter, 900 nm of Sm was deposited to form a Schottky electrode 18. After that, 10.
AQ wiring 11 was formed and a Schottky junction diode was created.

This example is similar to Example 1 except that a Schottky electrode 18 is formed in place of the high concentration n-type layer 9 in Example 1.
This is exactly the same as in Example 1, and the area proportion of the junction leakage current was reduced to 1/3 as in Example 1.

〔Effect of the invention〕

According to the present invention, leakage current flowing through the bottom surface of a pn junction used with a reverse bias applied in a semiconductor device can be reduced to about 173. As a result, large-scale integrated circuits can achieve lower power consumption and higher speed.

Further, the present invention exhibits the effect of reducing leakage current also in Schottky junctions.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing the concept of the present invention, and FIG.
The figure shows an example of the present invention! 3 is a characteristic diagram showing the depth distribution of carrier concentration in Example 1, FIG. 4 is a characteristic diagram of leakage current of junctions according to Example 1 and the prior art, and 5. Figure 6.7 is a sectional view of a device according to another embodiment of the invention. Explanation of symbols 1.4...Si substrate, 2...first buried layer, 3
...Second buried layer, 5,13...Oxide film, 6,1
5゜17...p-type Si region, 7...p-type buried layer, 8...n-type buried layer, 9, 12, 16-n-type Si
Region, 10... Passivation film, 11... AQ
Wiring, 14... Polycrystalline silicon electrode, 18... Schottky - 7) 2 Ya 1 Kidney fold

Claims (1)

[Claims] 1. Inside a semiconductor substrate having a pn junction on its surface, which is used by applying a reverse bias, there is a semiconductor substrate of the same conductivity type as the semiconductor substrate, where the impurity concentration is maximum in a portion deeper than the pn junction. 1
, a second buried impurity layer of a conductivity type opposite to that of the semiconductor substrate in a region deeper than the first buried impurity layer, and a maximum impurity concentration of the second buried impurity layer. A semiconductor device characterized in that the maximum impurity concentration of the first buried impurity layer is the same as or higher than the maximum impurity concentration of the first buried impurity layer. 2. Claim 1, wherein the first and second buried impurity layers are formed by ion implantation.
A method for manufacturing a semiconductor device according to paragraph 1. 3. The semiconductor device according to claim 1, further comprising a Schottky junction in place of the pn junction on the surface of the semiconductor substrate.