JPH02118953U - - Google Patents
Info
- Publication number
- JPH02118953U JPH02118953U JP2686389U JP2686389U JPH02118953U JP H02118953 U JPH02118953 U JP H02118953U JP 2686389 U JP2686389 U JP 2686389U JP 2686389 U JP2686389 U JP 2686389U JP H02118953 U JPH02118953 U JP H02118953U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- cutoff voltage
- type
- small
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
第１図は本考案のデユアルゲート電界効果型ト
ランジスタを増幅回路に適用した一実施例の回路
図、第２図は本考案のデユアルゲート電界効果型
トランジスタを周波数混合回路に適用した他の実
施例の回路図、第３図はデユアルゲート型電界効
果トランジスタのゲート電圧に対するドレイン電
流の関係図、第４図は従来のデユアルゲート型電
界効果トランジスタを用いたバイアス回路の回路
図である。
１，１′……信号入力端子（ＩＮ）、２……Ａ
ＧＣ入力端子（ＶＡＧＣ）、３……信号出力端子
（ＯＵＴ）、４……給電端子（Ｖｃｃ）、Ｒ１〜
Ｒ８，ＲＳ……バイアス抵抗、ＲＦＣ１，２，３
……高周波チヨークコイル、Ｃ１〜Ｃ５……コン
デンサ。
Figure 1 is a circuit diagram of one embodiment in which the dual-gate field effect transistor of the present invention is applied to an amplifier circuit, and Figure 2 is another embodiment in which the dual-gate field-effect transistor of the present invention is applied to a frequency mixing circuit. 3 is a diagram showing the relationship between the drain current and the gate voltage of a dual gate field effect transistor, and FIG. 4 is a circuit diagram of a bias circuit using a conventional dual gate field effect transistor. 1, 1'...Signal input terminal (IN), 2...A
GC input terminal (VAGC), 3... Signal output terminal (OUT), 4... Power supply terminal (Vcc), R 1 ~
R 8 , RS...Bias resistance, RFC1, 2, 3
...High frequency chiyoke coil, C1 to C5 ...Capacitor.
Claims (1)
プレツシヨン型でかつ、第２ゲートのカツトオフ
電圧は正側のエンハンスメント型もしくは負側で
も小さいエンハンスメント型に近にゲート構造を
有することを特徴とするデユアルゲート型電界効
果トランジスタ。 A dual gate type, characterized in that the cutoff voltage of the first gate is a depletion type, which is large on the negative side, and the cutoff voltage of the second gate is an enhancement type, which is small on the positive side, or has a gate structure close to an enhancement type, where the cutoff voltage is small on the negative side. field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2686389U JPH02118953U (en) | 1989-03-08 | 1989-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2686389U JPH02118953U (en) | 1989-03-08 | 1989-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02118953U true JPH02118953U (en) | 1990-09-25 |
Family
ID=31248872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2686389U Pending JPH02118953U (en) | 1989-03-08 | 1989-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02118953U (en) |
-
1989
- 1989-03-08 JP JP2686389U patent/JPH02118953U/ja active Pending
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