JPH02118827A - Buffer circuit - Google Patents
Buffer circuitInfo
- Publication number
- JPH02118827A JPH02118827A JP27207688A JP27207688A JPH02118827A JP H02118827 A JPH02118827 A JP H02118827A JP 27207688 A JP27207688 A JP 27207688A JP 27207688 A JP27207688 A JP 27207688A JP H02118827 A JPH02118827 A JP H02118827A
- Authority
- JP
- Japan
- Prior art keywords
- buffers
- buffer
- information
- signal
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 72
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 101100075513 Oryza sativa subsp. japonica LSI3 gene Proteins 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 208000011580 syndromic disease Diseases 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、情報処理および通信システムなどで用いられ
る装置に利用される。特に、バッファ回路の続出手段に
関する。このバッファ回路は、エラーの種類（パリティ
エラー、訂正不能エラー、訂正可能エラーなど）やエラ
ー発生時の補助情報（エラー−発生時のアドレスなど）
および診断レジスタとして使用する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized in devices used in information processing and communication systems. In particular, the present invention relates to means for successively providing buffer circuits. This buffer circuit collects error types (parity errors, uncorrectable errors, correctable errors, etc.) and auxiliary information at the time of error occurrence (error - address at the time of occurrence, etc.)
and as a diagnostic register.
本発明は、複数の大規模集積回路に分割されたバッファ
回路の続出手段において、
分割された大規模集積回路間でバッファ内の情報を転送
してから読出すことにより、
簡単な構成の続出手段の実現を図ることができるように
したものである。The present invention provides a means for continuing a buffer circuit divided into a plurality of large-scale integrated circuits, which has a simple configuration by transferring information in the buffer between the divided large-scale integrated circuits and then reading it out. It is designed to make it possible to realize the following.
従来、この種のバッファ回路はＬＳＩの規模により複数
に分割する必要があった。従来例の構成を第３図に示す
。この従来例では、訂正可能エラーが発生したときに、
ＬＳＩＩのバッファ２に格納されたエラー情報（訂正可
能以外のエラー）や補助情報（アドレス）をＬＳＩ３の
バッファに転送し、ＬＳＩ３の以前から格納されていた
エラー情報（訂正可能エラーとそれ以外のエラー）や補
助情報（シンドロームなど）をＬＳＩＩから転送されて
きた情報とともに信号３００として出力する。Conventionally, this type of buffer circuit has had to be divided into multiple parts depending on the scale of the LSI. The configuration of a conventional example is shown in FIG. In this conventional example, when a correctable error occurs,
The error information (other than correctable errors) and auxiliary information (address) stored in the LSII's buffer 2 are transferred to the LSI3 buffer, and the error information (correctable errors and other errors) stored before the LSI3 is transferred. ) and auxiliary information (syndrome, etc.) are output as a signal 300 together with the information transferred from the LSII.
このように、バッファ回路を複数に分けた場合に、従来
の読出回路は構成が複雑でハード量が多い欠点がある。As described above, when the buffer circuit is divided into a plurality of parts, the conventional readout circuit has the disadvantage of a complicated configuration and a large amount of hardware.
本発明はこのような欠点を除去するもので、複数に分割
しても続出回路の構成が簡単なバッファ回路を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks, and aims to provide a buffer circuit whose successive circuits can be easily configured even when divided into a plurality of parts.
本発明は、ｎ個のバッファを有する第一大規模集積回路
と、ｍ個（ｍ ＞ ｎ ）のバッファを有する第二大規
模集積回路とを備えたバッファ回路において、起動信号
に応じて上記第一大規模集積回路内のｎ個のバッファお
よび上記第二大規模集積回路内のｎ個のバッファをシフ
トモードに設定し、上記第一大規模集積回路内のｎ個の
バッファに格納された情報を上記第二大規模集積回路内
のｎ個のバッファに転送する転送手段と、この転送手段
による転送終了後に上記第二大規模集積回路のｍ個のバ
ッファに格納された情報を並列に読出し、この読出した
並列情報を直列情報に変換する並列直列変換手段とを備
えたことを特徴とする。The present invention provides a buffer circuit including a first large-scale integrated circuit having n buffers and a second large-scale integrated circuit having m buffers (m > n), in which the first large-scale integrated circuit The n buffers in the first large-scale integrated circuit and the n buffers in the second large-scale integrated circuit are set to shift mode, and the information stored in the n buffers in the first large-scale integrated circuit is set to shift mode. a transfer means for transferring the information to the n buffers in the second large-scale integrated circuit; and after the transfer by the transfer means finishes, reading the information stored in the m buffers in the second large-scale integrated circuit in parallel; The present invention is characterized by comprising a parallel-to-serial conversion means for converting the read parallel information into serial information.
エラーの検出信号を含む起動信号に応じて分割された二
つの大規模集積回路内のｎ個のバッファはシフトモード
に設定されバッファのｎ個分の情報がシリアルに一方の
大規模集積回路に転送される。転送終了後に、一方の大
規模集積回路のすべてのバッファ内の情報がパラレルに
読出され、この読出された情報がシリアル信号に変換さ
れて出力される。In response to an activation signal including an error detection signal, the n buffers in the two divided large-scale integrated circuits are set to shift mode, and the information of the n buffers is serially transferred to one large-scale integrated circuit. be done. After the transfer is completed, the information in all the buffers of one large-scale integrated circuit is read out in parallel, and this read information is converted into a serial signal and output.
以下、本発明の一実施例を図面に基づき説明する。第１
図はこの実施例の構成を示す回路図である。Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a circuit diagram showing the configuration of this embodiment.
この実施例は、ＬＳＩＩおよびＬＳＩ３の２つのＬＳＩ
を有する。ＬＳＩＩはｎ個のバッファ２を有し、ＬＳＩ
２はｍ個のバッファ４を有する。This example uses two LSIs, LSII and LSI3.
has. The LSII has n buffers 2, and the LSI
2 has m buffers 4.
すなわち、この実施例は、ｎ個のバッファ２を有する第
一大規模集積回路１と、ｍ個（ｍ＞ｎ）のバッファ４を
有する第二大規模集積回路３とを備え、さるに、起動信
号に応じて上記第−大規模集積回路内のｎ個のバッファ
および上記第二大規模集積回路内のｎ個のバッファをシ
フトモードに設定し、上記第一大規模集積回路内のｎ個
のバッファに格納された情報を上記第二大規模集積回路
内のｎ個のバッファに転送する転送手段であるバッファ
制御回路６と、この転送手段による転送終了後に上記第
二大規模集積回路のｍ個のバッファに格納された情報を
並列に読出し、この読出しだ並列情報を直列情報に変換
する並列直列変換手段であるパラレルシリアル変換回路
５とを備える。That is, this embodiment includes a first large-scale integrated circuit 1 having n buffers 2 and a second large-scale integrated circuit 3 having m buffers 4 (m>n). In response to the signal, the n buffers in the first large-scale integrated circuit and the n buffers in the second large-scale integrated circuit are set to shift mode, and the n buffers in the first large-scale integrated circuit are set to shift mode. a buffer control circuit 6 which is a transfer means for transferring the information stored in the buffer to the n buffers in the second large-scale integrated circuit; A parallel-to-serial conversion circuit 5 is provided as a parallel-to-serial conversion means for reading out information stored in the buffer in parallel and converting the read parallel information into serial information.
第２図はこの実施例の動作を示す説明図である。FIG. 2 is an explanatory diagram showing the operation of this embodiment.
次に、この実施例の動作を第１図および第２図に基づき
説明する。Next, the operation of this embodiment will be explained based on FIGS. 1 and 2.
エラー（ＥＲＲ）を検出して情報（ＤＡＴＡ）を取り込
むと、バッファ制御回路６が信号を出力する。ＬＳＩＩ
はバッファ制御信号４００を受は取り、バッファ２のｎ
個をシフトモードにし、また、ＬＳＩ３もバッファ４の
ｎ個をシフトモードにする。バッファ転送信号１００に
よりｎ個分の情報をシリアルにＬＳＩ３のバッファ４の
ｎ個にセレクタ２０を介して転送、する。そのときにＬ
ＳＩＩ内のバッファｎ個はセレクタ３０により元の情報
を保持する。バッファ制御回路６はｎ個分の転送が終了
すると信号を止める。すべての情報（バッファｍ個分）
をＬＳＩＢ内に格納すると、パラレルシリアル変換回路
５にバッファパラレル続出信号２００を与え、バッファ
シリアル続出信号３００に変換して出力する。When an error (ERR) is detected and information (DATA) is taken in, the buffer control circuit 6 outputs a signal. LSII
receives the buffer control signal 400 and controls the n of buffer 2.
In addition, the LSI 3 also puts n buffers 4 into shift mode. Using the buffer transfer signal 100, n pieces of information are serially transferred to n pieces of buffer 4 of the LSI 3 via the selector 20. At that time L
The n buffers in the SII retain the original information by the selector 30. The buffer control circuit 6 stops the signal when n transfers are completed. All information (m buffers)
When stored in the LSIB, the buffered parallel successive signal 200 is given to the parallel-serial conversion circuit 5, which converts it into a buffered serial successive signal 300 and outputs it.
本発明は、以上説明したように、ＬＳＩが個別にもつバ
ッファを１つのＬＳＩに格納するので、バッファの続出
回路を１つにまとめ、かつ複雑でなくハード量を少なく
し、容易に読出ずことができる効果がある。As explained above, the present invention stores the buffers that each LSI has individually in one LSI, so that the circuits for successive buffers can be combined into one, and it is not complicated, reduces the amount of hardware, and is not easily readable. It has the effect of
第１図は本発明実施例の構成を示す回路接続図。
第２図は本発明実施例の動作を示す説明図。
第３図は従来例の構成を示す回路接続図。
１．３・・・ＬＳＩ、２．４・・・バッファ、５．５′
・・・パラレルシリアル変換回路（ＰＳ変換回路）、６
・・・バッファ制御回路、７・・・バッファシリアル続
出選択回路、１０・・・オア回路、２０．３０・・・セ
レクタ、１００・・・バッファ転送信号、２００・・・
バッファパラレル読出信号、３００・・・バッファシリ
アル読出信号、４００・・・バッファ制御信号。FIG. 1 is a circuit connection diagram showing the configuration of an embodiment of the present invention. FIG. 2 is an explanatory diagram showing the operation of the embodiment of the present invention. FIG. 3 is a circuit connection diagram showing the configuration of a conventional example. 1.3...LSI, 2.4...Buffer, 5.5'
...Parallel-serial conversion circuit (PS conversion circuit), 6
... Buffer control circuit, 7... Buffer serial successive selection circuit, 10... OR circuit, 20.30... Selector, 100... Buffer transfer signal, 200...
Buffer parallel read signal, 300... Buffer serial read signal, 400... Buffer control signal.
Claims (1)
と を備えたバッファ回路において、 起動信号に応じて上記第一大規模集積回路内のｎ個のバ
ッファおよび上記第二大規模集積回路内のｎ個のバッフ
ァをシフトモードに設定し、上記第一大規模集積回路内
のｎ個のバッファに格納された情報を上記第二大規模集
積回路内のｎ個のバッファに転送する転送手段と、 この転送手段による転送終了後に上記第二大規模集積回
路のｍ個のバッファに格納された情報を並列に読出し、
この読出した並列情報を直列情報に変換する並列直列変
換手段と を備えたことを特徴とするバッファ回路。[Claims] 1. In a buffer circuit comprising a first large-scale integrated circuit having n buffers and a second large-scale integrated circuit having m buffers (m>n), the activation signal Accordingly, the n buffers in the first large-scale integrated circuit and the n buffers in the second large-scale integrated circuit are set to shift mode, and the n buffers in the first large-scale integrated circuit a transfer means for transferring the stored information to the n buffers in the second large-scale integrated circuit; and a transfer means for transferring the information stored in the m buffers in the second large-scale integrated circuit after the transfer by the transfer means is completed. read in parallel,
A buffer circuit comprising: parallel-to-serial conversion means for converting the read parallel information into serial information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27207688A JPH02118827A (en) | 1988-10-28 | 1988-10-28 | Buffer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27207688A JPH02118827A (en) | 1988-10-28 | 1988-10-28 | Buffer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02118827A true JPH02118827A (en) | 1990-05-07 |
Family
ID=17508759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27207688A Pending JPH02118827A (en) | 1988-10-28 | 1988-10-28 | Buffer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02118827A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49122940A (en) * | 1973-03-26 | 1974-11-25 | ||
| JPS61275952A (en) * | 1985-05-31 | 1986-12-06 | Fuji Electric Co Ltd | Data output circuit |
| JPS62150458A (en) * | 1985-12-24 | 1987-07-04 | Nec Corp | Microcomputer |
-
1988
- 1988-10-28 JP JP27207688A patent/JPH02118827A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49122940A (en) * | 1973-03-26 | 1974-11-25 | ||
| JPS61275952A (en) * | 1985-05-31 | 1986-12-06 | Fuji Electric Co Ltd | Data output circuit |
| JPS62150458A (en) * | 1985-12-24 | 1987-07-04 | Nec Corp | Microcomputer |
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