JPH02116170A - Solid state image sensing device - Google Patents
Solid state image sensing deviceInfo
- Publication number
- JPH02116170A JPH02116170A JP63269680A JP26968088A JPH02116170A JP H02116170 A JPH02116170 A JP H02116170A JP 63269680 A JP63269680 A JP 63269680A JP 26968088 A JP26968088 A JP 26968088A JP H02116170 A JPH02116170 A JP H02116170A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- output gate
- electrode
- diffusion layer
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title 1
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000003384 imaging method Methods 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は固体撮像装置に関し、特にCCD固体撮像装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a CCD solid-state imaging device.
従来電荷結合素子を用いた固体撮像装置は入射光量に応
じて電荷を蓄積する感光部と、この感光部に蓄積された
電荷を転送する転送レジスタと、転送されて来た電荷を
検出する電荷検出部から構成されている。この中で電荷
検出部付近の構成は、転送されて来た電荷を受ける浮遊
拡散層、この浮遊拡散層に隣接して転送レジスタ側に出
力ゲート電極、反対側にリセット電極が設けられている
。A conventional solid-state imaging device using a charge-coupled device has a photosensitive part that accumulates charge according to the amount of incident light, a transfer register that transfers the charge accumulated in this photosensitive part, and a charge detection device that detects the transferred charge. It consists of parts. The configuration near the charge detection section includes a floating diffusion layer that receives transferred charges, an output gate electrode adjacent to the floating diffusion layer on the transfer register side, and a reset electrode on the opposite side.
この固体撮像装置の電荷検出部は、第4図に示すように
転送されて来た電荷を受ける浮遊拡散層1、浮遊拡散層
1に隣接して片側に出力ゲート電極(2,3>、反対側
に転送されて来た電荷を感光部毎にリセットするリセッ
ト電極12で構成されている。そしてこの浮遊拡散層1
は寸法的には感度の点から小さくする必要がある。それ
には精度よく加工する必要があり、浮遊拡散層1の両側
の電極は通常1層目の電極で構成する形を取っている。As shown in FIG. 4, the charge detection section of this solid-state imaging device consists of a floating diffusion layer 1 that receives transferred charges, an output gate electrode (2, 3>) on one side adjacent to the floating diffusion layer 1, and an output gate electrode (2, 3> on the other side). It is composed of a reset electrode 12 that resets charges transferred to the side for each photosensitive part.Then, this floating diffusion layer 1
It is necessary to make the size small from the viewpoint of sensitivity. This requires precise processing, and the electrodes on both sides of the floating diffusion layer 1 are usually constructed from the first layer electrodes.
又出力がゲート電極に隣接する転送電極の最後の電極は
通常1層目で終わるため出力ゲート電極は2層、1層と
電極を設けこれら2つの電極(第2出力ゲート電極3と
第1出力ゲート電極2)を配線で接続し直流のバイアス
電圧印加端子15に接続している。このため拡散プロセ
スによっては出力ゲート電極の2層目の電極(第2出力
ゲート3)下の方が電位的に高くなる事がある。In addition, since the last electrode of the transfer electrode whose output is adjacent to the gate electrode usually ends in the first layer, the output gate electrode has two layers and one layer of electrodes, and these two electrodes (the second output gate electrode 3 and the first output The gate electrode 2) is connected by wiring and connected to a DC bias voltage application terminal 15. Therefore, depending on the diffusion process, the potential below the second layer of the output gate electrode (second output gate 3) may become higher.
こうなった場合には出力ゲート電極下で1層目と2層目
の電位差分の電荷が取り残される事になり転送効率が悪
くなってしまう欠点を持っている。In this case, the charge corresponding to the potential difference between the first layer and the second layer is left behind under the output gate electrode, resulting in a disadvantage that the transfer efficiency deteriorates.
本発明は拡散プロセスによって生じる恐れのある転送効
率劣化を防ぎ安定した歩留りが得られる固体撮像装置を
提供する事を目的としている。An object of the present invention is to provide a solid-state imaging device that can prevent deterioration in transfer efficiency that may occur due to the diffusion process and provide a stable yield.
本発明の固体撮像装置は、半導体基板の一主面に設けら
れた感光部から電荷を受け取って転送する転送レジスタ
と、前記転送レジスタの最終段の転送電極に隣接して順
次に配置された第2出力ゲート電極、第1出力ゲート電
極及び電荷検出用の浮遊拡散層を有する固体撮像装置に
おいて、前記第1の出力ゲート電極に前記第2出力ゲー
ト電極より高い電圧を印加する手段を備えているという
ものである。The solid-state imaging device of the present invention includes a transfer register that receives and transfers charges from a photosensitive portion provided on one main surface of a semiconductor substrate, and a transfer register that is sequentially arranged adjacent to a transfer electrode at the final stage of the transfer register. A solid-state imaging device having two output gate electrodes, a first output gate electrode, and a floating diffusion layer for charge detection, comprising means for applying a higher voltage to the first output gate electrode than to the second output gate electrode. That is what it is.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a>は本発明の一実施例を示す平面模式図、第
1図(b)は第1図(a)のA−A’線断面図である。FIG. 1(a) is a schematic plan view showing one embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line AA' in FIG. 1(a).
シリコン半導体基板に設けられた浮遊拡散層1に隣接し
て1層目多結晶シリコン膜からなる第1出力ゲート電極
2、この第1出力ゲート電極に隣接して2層目多結晶シ
リコンからなる第2出力ゲート電極3が各々独立して電
圧印加端子14゜15に接続されている。ここでの動作
は次の様になる。第2図は転送電極駆動パルス1,2の
信号波形図、第3図は電荷転送の格子を説明するための
電位分布推移図である。いまあるタイミング1、におい
て転送レジスタの最終段の転送電極4下に転送されて来
た電荷(第3図に斜線で示す〉があり、この電荷が浮遊
拡散層1に流れ込むには転送電極4(1層目の多結晶シ
リコン膜からなる)に印加される電圧が低いレベルにな
ると(タイミングt2)電位が浅くなり電荷は出力ゲー
ト電極下を通って浮遊拡散層に流入する。この時第1出
力ゲート電極2の方が第2出力ゲート電極3に比べて高
い電圧(IV程度)を印加する様にしておけば転送電極
下の電荷はすべて出力ゲート電極下を通って浮遊拡散層
に流入する事になり出力ゲート電極下での転送残りは発
生しない。A first output gate electrode 2 made of a first layer of polycrystalline silicon is adjacent to a floating diffusion layer 1 provided on a silicon semiconductor substrate, and a second output gate electrode made of a second layer of polycrystalline silicon is adjacent to this first output gate electrode. Two output gate electrodes 3 are each independently connected to voltage application terminals 14 and 15. The operation here is as follows. FIG. 2 is a signal waveform diagram of transfer electrode drive pulses 1 and 2, and FIG. 3 is a potential distribution transition diagram for explaining a charge transfer grid. At the current timing 1, there is a charge (indicated by diagonal lines in FIG. 3) transferred below the transfer electrode 4 at the final stage of the transfer register, and in order for this charge to flow into the floating diffusion layer 1, the transfer electrode 4 ( When the voltage applied to the first layer (consisting of a polycrystalline silicon film) falls to a low level (timing t2), the potential becomes shallow and charges flow into the floating diffusion layer through the output gate electrode.At this time, the first output If a higher voltage (about IV) is applied to the gate electrode 2 than to the second output gate electrode 3, all the charges under the transfer electrode will flow into the floating diffusion layer through under the output gate electrode. Therefore, no residual transfer occurs under the output gate electrode.
この様に、第2出力ゲート電極と第1出力ゲート電極が
それぞれ別の端子に接続されているので、第1出力ゲー
ト電極の方に若干高い電圧を印加することにより、確実
に電荷を浮遊拡散層に送り込むことができ、転送効率の
劣化は防止される。In this way, since the second output gate electrode and the first output gate electrode are connected to different terminals, applying a slightly higher voltage to the first output gate electrode ensures that the charge is floatingly diffused. transfer efficiency can be prevented from deteriorating.
以上説明した様に本発明は、浮遊拡散層に隣接する第1
.第2出力ゲート電極を別々の電圧印加端子に接続し、
浮遊拡散層に隣接する方(第1出力ゲート電極)に高い
電圧を印加する様にする事により、出力ゲート電極下で
の電荷転送残りによる問題はなくなり固体撮像装置の安
定した歩留りが実現できる効果がある。As explained above, the present invention provides the first structure adjacent to the floating diffusion layer.
.. connecting the second output gate electrode to separate voltage application terminals;
By applying a high voltage to the side adjacent to the floating diffusion layer (first output gate electrode), problems due to residual charge transfer under the output gate electrode are eliminated, and a stable yield of solid-state imaging devices can be achieved. There is.
第1図(a)は本発明の一実施例を示す電荷検出部近傍
の平面模式図、第1図(b)は第1図(a>のA−A’
線断面模式図、第2図は転送電極駆動パルスの信号波形
図、第3図は電荷転送の様子を説明するための電位分布
推移図、第4図は従来例を示す電荷検出部近傍の平面模
式図である。
1・・・浮遊拡散層、2・・・第1出力ゲート電極、3
・・・第2出力ゲート電極、4〜11・・・転送電極、
12・・・リセット電極、13・・・リセットドレイン
、14・・・第1出力ゲート電極電圧印加端子、15・
・・第2出力ゲート電極電圧印加端子、16・・・酸化
シリコン膜。FIG. 1(a) is a schematic plan view of the vicinity of a charge detection section showing an embodiment of the present invention, and FIG. 1(b) is a plane view taken along line AA' in FIG.
A schematic diagram of a line cross section, Fig. 2 is a signal waveform diagram of a transfer electrode drive pulse, Fig. 3 is a potential distribution transition diagram to explain the state of charge transfer, and Fig. 4 is a plane near the charge detection section showing a conventional example. It is a schematic diagram. 1... Floating diffusion layer, 2... First output gate electrode, 3
... second output gate electrode, 4 to 11 ... transfer electrode,
12... Reset electrode, 13... Reset drain, 14... First output gate electrode voltage application terminal, 15.
...Second output gate electrode voltage application terminal, 16...Silicon oxide film.
Claims (1)
取って転送する転送レジスタと、前記転送レジスタの最
終段の転送電極に隣接して順次に配置された第2出力ゲ
ート電極、第1出力ゲート電極及び電荷検出用の浮遊拡
散層を有する固体撮像装置において、前記第1の出力ゲ
ート電極に前記第2出力ゲート電極より高い電圧を印加
する手段を備えている事を特徴とする固体撮像装置。A transfer register that receives and transfers charge from a photosensitive portion provided on one principal surface of a semiconductor substrate, a second output gate electrode, and a first output, which are sequentially arranged adjacent to a final stage transfer electrode of the transfer register. A solid-state imaging device having a gate electrode and a floating diffusion layer for charge detection, characterized in that the solid-state imaging device includes means for applying a higher voltage to the first output gate electrode than to the second output gate electrode. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63269680A JPH02116170A (en) | 1988-10-25 | 1988-10-25 | Solid state image sensing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63269680A JPH02116170A (en) | 1988-10-25 | 1988-10-25 | Solid state image sensing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02116170A true JPH02116170A (en) | 1990-04-27 |
Family
ID=17475697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63269680A Pending JPH02116170A (en) | 1988-10-25 | 1988-10-25 | Solid state image sensing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02116170A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07176726A (en) * | 1993-12-21 | 1995-07-14 | Sony Corp | Charge transfer device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS634681A (en) * | 1986-06-24 | 1988-01-09 | Nec Corp | Semiconductor device |
-
1988
- 1988-10-25 JP JP63269680A patent/JPH02116170A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS634681A (en) * | 1986-06-24 | 1988-01-09 | Nec Corp | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07176726A (en) * | 1993-12-21 | 1995-07-14 | Sony Corp | Charge transfer device |
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