JPH02116157A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate keeping a high impedance state when an electric circuit is cut off by a method wherein an N-type semiconductor region in which a P-type channel FET is formed is connected to a high potential side source line through a Schottky junction. CONSTITUTION:An N-type channel MOS transistor TN which is one of FET's constituting a CMOS circuit is formed on a P-type substrate 1 and a P-type channel MOS transistor TP which is the other FET is formed on the N-type well 2. An N-type well contact 7 through which a source potential is applied to the N-type well 2 on which the transistor Tp is formed is composed of a Schottky junction instead of a conventional N<+>-type impurity-doped region. In other words, a Schottky diode DSSD is connected to a parasitic diode D2 in series and newly inserted between an electric source (VDD) line and an output terminal Q. The N-type well 2 is pulled up by a voltage lower than the source voltage VDD by the Schottky diode potential VSBD and a comtinuity potential. Even if the source voltage of the CMOS output circuit is cut off, the high impedance state of the output terminal can be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an integrated circuit device including a CMOS circuit.

[Conventional technology]

FIGS. 3(a) and 3(b) are a cross-sectional structural diagram and an equivalent circuit diagram of an output circuit portion of a semiconductor integrated circuit device including a conventional CMOS circuit, respectively. This CMOS circuit constitutes an inverter, and includes a P-type silicon substrate 1 and its N
N-channel MO9 arranged adjacent to each other on well 2)
- Transistor TN and P-channel MOS transistor Tp
It consists of a combination circuit with Here, the transistor TN
The source regions of Tp and Tp are respectively connected to the ground potential (GND) and the power supply potential (VDD), and function to invert the level of an input signal applied to the common connection terminal of the gate and output it from the common connection terminal Q of the drain.

[Problem to be solved by the invention]

However, in the conventional semiconductor integrated circuit device described above, the substrate and well are connected to the ground potential (
GND) and power supply potential (Voo) to stabilize the respective potentials, the P-type substrate contact 3
and the drain region 4 of the N-channel MOS transistor TN.
Parasitic diodes D1 and D2 are respectively formed between drain region 5 of P channel MOS transistor TP and N well contact 6 consisting of an N+ doping region. Therefore, in this state, if the power supply (VDD) line is cut off and the transistor TP becomes inoperable, and the transistor Tp is apparently lowered to the upper GND logic level, the current from other elements on the board will flow into this parasitic state. A phenomenon occurs in which current flows from the output terminal Q to the power supply (Voo) line via the current inflow path formed by the diode D2. At this time, if the inflow current value from the output terminal Q is high, it may damage the transistor TP, but on the other hand, the potential of the output terminal Q is maintained at a low potential of at most 0.6 V, which corresponds to the conduction potential of the diode. Therefore, this CMOS inverter circuit essentially outputs the "L" level regardless of the level of the input signal. Conventionally, this problem has been dealt with by the user paying close attention as a restriction on use, taking into full consideration that the above-mentioned problem may occur in the CMO3 circuit.

Generally speaking, it is preferable for the output terminals of integrated circuit devices to be in a high-dance state when the power is turned off. The study will be conducted by limiting the power supply to some integrated circuits and cutting off the power supply. At this time, it is of course most preferable that the output terminal of the integrated circuit whose power is cut off is in a high impedance state.

In view of the above circumstances, an object of the present invention is to provide CMO8 on a substrate.
An object of the present invention is to provide a semiconductor integrated circuit device in which an output terminal of an output circuit can be set to a high impedance state when the power is cut off.

[Means to solve the problem]

According to the present invention, a semiconductor integrated circuit device includes a CMO3 output circuit having a push-pull circuit configuration in which two N-channel and P-channel field effect transistors are respectively connected to power supply lines on a low potential side and a high potential side, The N-type semiconductor region forming the P-channel field effect transistor is connected to a high-potential side power supply line via a Schottky junction contact.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) and 1(b) are a cross-sectional structural diagram and an equivalent circuit diagram of a CMO3 circuit portion of a semiconductor integrated circuit device showing one embodiment of the present invention, respectively. According to this embodiment,
The case where one N-channel MOS transistor TN constituting the CMO3 circuit is formed on the substrate and the other P-channel MOS transistor TP is formed on the N well is shown using the same reference numerals as in FIG. This embodiment is fundamentally different from the conventional structure in that the N-well contact 7 which supplies the power supply potential to the N-well 2 in which the P-channel MO transistor Tp is formed is different from the conventional N"
Instead of a doped region, a Schottky junction surface is used. That is, as shown in the equivalent circuit [see FIG. 1(b)], the Schottky diode D se
A is newly inserted between the power supply (Voo) line and the output terminal Q, connected in series with the parasitic diode D2. According to this embodiment, the N-well 2 has a conventional structure with a power supply voltage (V
CMO3 is pulled up at a voltage lower than the power supply voltage VDD by the Schottky diode V580 and conduction potential (0.3 to 0.5 V). There is no effect on the normal operation of the output circuit. With this configuration, even if the power supply voltage is cut off in the CMO3 output circuit, the current path from the output terminal Q to the power supply (Voo) line will be cut off by the Schottky diode D5B0. The output terminal Q can maintain a high impedance state.

FIGS. 2(a) and 2(b) are a cross-sectional structural diagram and an equivalent circuit diagram of a CMO3 circuit portion of a semiconductor integrated circuit device showing other embodiments of the present invention, respectively. According to this embodiment, one P-channel MO3) transistor Tp constituting the CMO3 circuit is formed on the N-type semiconductor substrate 10, and the other N-channel MOS transistor TN is formed on the P well 9. is shown. In this embodiment as well, the N-type substrate 10 is pulled up via the Schottky junction N-type substrate contact 8, so the effect of ensuring the high impedance state of the output terminal Q when the power supply voltage is opened is similar to that of the previous embodiment. It can be played equally well.

〔Effect of the invention〕

As described above in detail, according to the present invention, the CMO8 output circuit having a push-pull circuit configuration in which a P-channel field effect transistor is connected to a high-potential side power supply line has a
The N-type semiconductor region that forms the channel transistor is connected to the high-potential side power supply line via a Schottky junction and pulled up, so even if the power supply line is cut off, the output terminal is maintained in a high impedance state. I can do it. Therefore, it is possible to obtain a semiconductor integrated circuit device with few restrictions on use and stable circuit operation.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a cross-sectional structural diagram and an equivalent circuit diagram of a CMO3 circuit portion of a semiconductor integrated circuit device showing one embodiment of the present invention, respectively, and FIGS. 2(a) and (b) are
3A and 3B are cross-sectional structural diagrams and equivalent circuit diagrams of a CMO3 circuit portion of a semiconductor integrated circuit device showing other embodiments of the present invention, respectively, and FIGS. 3A and 3B respectively show a conventional CMO
2 is a cross-sectional structural diagram of an output circuit portion of a semiconductor integrated circuit device including three circuits and an equivalent circuit diagram thereof. FIG. 1... P-type semiconductor substrate, 2... N well, 3...
P-type substrate contact, 3'... P-well contact 2.4... Train region of N-channel MOS transistor, 5... Drain region of P-channel MOS transistor, 7... N-well of Schottky junction・Contact, 8... N-type substrate contact of Schottky junction, 9... P well, 10... N-type semiconductor substrate, TN
...N-channel MO3) transistor, Tp...P-channel MOS transistor, D, , D2...parasitic diode, D SBD...Schottky diode, ■
...Input terminal, Q...Output terminal.

Claims (1)

[Claims] It includes a CMOS output circuit with a push-pull circuit configuration that connects two N-channel and P-channel field-effect transistors to each power supply line on the low-potential side and high-potential side, respectively, and includes an N-channel field-effect transistor forming the P-channel field-effect transistor.
1. A semiconductor integrated circuit device, wherein a type semiconductor region is connected to a high-potential side power supply line via a Schottky junction contact.