JP2001086641A - Input protecting circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase electrostatic breakdown strength, and to lower an input bias current by clamping the voltage of an input terminal approximately at a first source voltage, when a voltage which exceeds the first source voltage and is lower than a voltage which turns a first protective diode on, is applied to the input terminal. SOLUTION: If a voltage higher than a first source voltage is applied to an input terminal t2, and the MOSFET M1 of a clamping means 24a is turned on, the voltage of the input terminal t2 is clamped at the sum voltage of a threshold voltage and the source voltage Vdd of the MOSFET M1. When an abnormal voltage is applied long and its voltage value is especially large, a first protective diode D1 is turned on, a current flows from the input terminal t2 to the source voltage Vdd, the voltage of the input terminal t2 is clamped at the sum voltage of the source voltage Vdd and a forward bias voltage of the protective diode, and breakdown of elements is prevented. Consequently, a high-reliability circuit which does not malfunction easily is obtained without lowering strength against electrostatic breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is useful when applied to an input protection circuit which protects a semiconductor element constituting an input circuit from electrostatic damage, and is, for example, an operational amplifier such as an operational amplifier formed as an integrated circuit on a semiconductor chip. The present invention relates to a technique that is particularly useful for a linear circuit.

[0002]

2. Description of the Related Art As shown in FIG. 7, for example, when an abnormal voltage is inputted to an operational amplifier constituted by a CMOS circuit, an element (input MOSFET) constituting an internal circuit is formed.
Conventionally, as a technique for protecting M5, M6) from electrostatic breakdown, a configuration is known in which protection diodes D1 and D2 are respectively connected between an input terminal and a power supply voltage Vdd and between the input terminal and a ground potential GND. ing. According to such a configuration, when the input voltage Vin exceeds the power supply voltage Vdd or falls below the ground potential GND, a forward current flows through the protection diodes D1 and D2, and the voltage of the input terminal is clamped and The circuit is protected.

However, the protection diodes D1,
D2 is, for example, as shown in FIG.
Between the p-type diffusion region 85 or p-well region 83 formed thereon and the n-type diffusion region 84 formed thereon.
In the case of an n-junction, unintended parasitic transistors Q1 and Q2 are formed between the semiconductor substrate 80 to which the power supply voltage Vdd is applied and other internal circuit elements. Then, when the input voltage Vin applied to the input terminal exceeds the power supply voltage Vdd, the parasitic transistors Q1 and Q2 are turned on and a current flows through an unintended path.

For example, in FIG. 8, a protection diode D2 having an n-type diffusion region 84 provided in a p-well region 83 is connected to a substrate 80 by turning on a parasitic transistor Q2.
Current flows from the input terminal to the input terminal (in this case, there is no malfunction of the circuit because the current only flows to the power supply). In the protection diode D1 in which the substrate 80 is a cathode, the ON operation of the parasitic transistor Q1 causes another input from the input terminal to another. A current flows toward the p-well region 81 of the element or the p-type diffusion region provided on the substrate 80, which causes a malfunction of the circuit.

In an operational amplifier, if a relatively long abnormal voltage or an abnormal voltage having a greatly deviated voltage value is applied to the input terminal, the circuit may malfunction. It is a problem that the circuit malfunctions only by applying the voltage.

Therefore, in the conventional operational amplifier, in order to prevent the circuit from easily malfunctioning, the protection diode D1 on the side of the power supply voltage Vdd shown in FIG.
The input protection circuit is configured by connecting the protection diode D2 only between the input terminal and the ground potential.

[0007]

However, the protection diode D connected to the power supply voltage Vdd side as described above.
Omitting 1 caused the following two problems.
That is, the first problem is that since there is no protection diode on the side of the power supply voltage Vdd, the intensity with respect to a positive electrostatic pulse is reduced. Second, during normal operation, a leakage current flows from the input terminal to the ground via the protection diode D2, and this leakage current becomes an input bias current of the circuit, thus deteriorating the characteristics of the circuit.
In addition, since the leak current increases exponentially as the temperature increases, there is a problem that the characteristics change with temperature fluctuation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an input protection circuit capable of improving the electrostatic breakdown strength and reducing the input bias current and preventing the malfunction of the circuit, and easily providing such an input protection circuit on a semiconductor substrate. It is to provide a semiconductor integrated circuit that can be integrated.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a first protection diode connected in reverse direction between the input terminal and the first power supply voltage, and a second protection diode connected in reverse direction between the input terminal and the second power supply voltage. When a voltage applied to the diode and the input terminal exceeds a first power supply voltage and does not reach a voltage at which the first protection diode is turned on, the input terminal is connected to the first terminal.
And clamping means for clamping to a power supply voltage.

According to such means, since the protection diode is provided at both the first power supply voltage and the second power supply voltage at the input terminal, the strength against electrostatic breakdown is improved, and By canceling the leakage currents of the first and second protection diodes, the magnitude of the input bias current at the input terminal can be reduced, and can be reduced to zero theoretically. In addition, even when an abnormal voltage exceeding the power supply voltage (a voltage higher than the higher power supply voltage or a voltage lower than the lower power supply voltage) is input, the voltage exceeds the voltage at which the first protection diode is turned on. Until the first protection diode is clamped to a level at which the first protection diode does not turn on by the above-described clamp means, the bipolar parasitic between the first protection diode and the semiconductor region of the substrate or the element constituting the circuit is not turned on. Can avoid malfunction of the circuit. Further, if the input of the abnormal voltage exceeding the first power supply voltage is applied only for a relatively short period of time, only the clamp means operates and the first protection diode does not operate, so that malfunction of the circuit can be avoided. .

Specifically, when the input circuit is constituted by MOSFETs, the MOS connected to the input terminal
The gate protection of the FET can be prevented by the input protection circuit, and the malfunction of the circuit such as the operational amplifier can be prevented.

Further, the first and second protection diodes comprise a p-type or n-type well region formed in a semiconductor substrate and an n-type or p-type semiconductor region formed in the well region. Pn having the same structure is formed by a junction. With this configuration, the magnitudes of the leakage currents of the first and second protection diodes can be made substantially the same, and the input bias current can be reduced by canceling the two.

Further, the above-mentioned clamping means can be realized by MOSFETs whose gate terminal and substrate are connected to the first power supply voltage, whose source terminal is connected to the input terminal, and whose drain terminal is connected to the second power supply voltage. For example, if the substrate is an n-type substrate, it can be constituted by a p-channel MOSFET.
Can be configured.

By the way, MOSF as clamping means
In ET, a small amount of leakage current flows in the pn junction between the source region and the substrate in the reverse direction in the off state, which causes an input bias current at the input terminal. Therefore, desirably, the clamping MOSF is used.
The p-type or n-type semiconductor region forming the source region of the ET and the p-well or n-well region of the first protection diode are integrally formed as a common region. With this configuration, it is possible to eliminate the input bias current due to the leak current of the clamp unit and to more completely cancel the leak currents on the first and second protection diode sides. That is, the input bias current can be further reduced.

The input protection circuit configured as described above is particularly effective when applied to, for example, a semiconductor integrated circuit provided on one semiconductor substrate together with a linear circuit such as an operational amplifier.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS. [First Embodiment] FIG. 1 is a circuit diagram showing a first embodiment of an operational amplifier circuit and an input protection circuit suitable for applying the present invention. FIG. 2 is a cross-sectional view showing a specific structure of a protection diode constituting an input protection circuit in the operational amplifier circuit of FIG. 1, and FIG. 3 is a plan view showing an overall configuration of an operational amplifier IC incorporating the operational amplifier circuit of FIG. is there.

The operational amplifier IC1 of this embodiment is a semiconductor device in which a semiconductor chip in which two operational amplifier circuits 2 and 3 are integrated is housed in one package, as shown in FIG. This operational amplifier IC1 has a first power supply terminal t to which a first power supply voltage Vdd (for example, +5 V) is input.
8, a second power supply terminal t4 to which a second power supply voltage Vss (for example, a ground potential) is input, and two positive-phase and negative-phase input voltages Vin + and Vin- corresponding to one of the operational amplifier circuits 2. The input terminals t2 and t3 and these input voltages Vi
an output terminal t4 for outputting the output voltage Vout after the operational amplification of n + and Vin-, and the other operational amplifier circuit 3
And two input voltages Vin2 +, Vi of a positive phase and a negative phase
Input terminals t5 and t6 to which n2- is input, and an output terminal t7 to which an output voltage Vout2 after operational amplification of these input voltages Vin2 + and Vin2- are output are provided. Here, since the two operational amplifier circuits 2 and 3 have substantially the same configuration, only one operational amplifier circuit 2 will be described.

As shown in FIGS. 1 and 2, the operational amplifier circuit 2 is composed of a CMOS circuit and is formed on an n-type semiconductor substrate as a circuit capable of obtaining a high gain (for example, 90 dB) with low power consumption. The operational amplifier circuit 2 includes a differential amplifying stage 21 for amplifying a voltage by taking a difference between two input voltages Vin + and Vin−, and MOSFETs M10 and M11 connected in series between a power supply voltage Vdd and GND. To obtain further output gain and output voltage Vout
Push-pull type output stage 23 for outputting to the output terminal t1
A cascade stage 22 for generating a signal for driving the MOSFET M10 on the pull side of the output stage 23;
1, D2 and the MOSFET as the clamping means 24a
M1, an input protection circuit 24 corresponding to the input voltage Vin-, diodes D3 and D4, and a clamp means 2
5a, and the input voltage Vi
The input protection circuit 25 corresponding to n + is provided.

Further, the pull-down side MO of the output stage 23
A phase compensation circuit 23a consisting of a resistor R1 and a capacitor C1 for preventing oscillation is connected between the gate and the drain of the SFET M11. Although not shown, the operational amplifier IC1 has a differential amplifier stage 21 separately from the above circuit.
And p-channel MOSF for each constant current of the cascade stage 22
A bias circuit that supplies a predetermined bias voltage (constant voltage) Vc to the gates of the ETs M3 and M4 is provided.

The diodes D1, D2; D3, D4 constituting the input protection circuits 24, 25 are connected to input terminals t2, t
When an abnormal voltage equal to or lower than the ground potential or exceeding the power supply voltage Vdd is applied to 3, a current flows to protect the internal circuit from electrostatic damage. The protection diodes D 1 and D 3 are connected to the first power supply voltage Vdd ( 5V) and input terminals t2, t
3, the protection diodes D2 and D4 are connected to the input terminal t.
2, t3 and the second power supply voltage (ground potential) are connected in the opposite directions in normal times.

When the protection diodes D1 to D4 are formed by pn junctions as shown in FIG. 2, the forward voltage is about 0.7V. Therefore, the protection diodes D1, D
3 is an input voltage Vin input to the input terminals t2 and t3.
When − and Vin + are higher than the first power supply voltage Vdd (5 V) by the forward voltage (0.7 V), a current flows, and the protection diode D2 changes the input voltage Vin− input to the input terminals t2 and t3. A current flows when the voltage is lower than the two power supply voltages (0 V) by the forward voltage (0.7 V).

These protection diodes D1, D2 (D
2, D4) is a diode having the same structure and provided on the semiconductor substrate 40 and having a pn junction, as shown in FIG. 2. For example, a p-type well region 41a, 41b and the well regions 41a, 4
By providing n-type diffusion regions 42a and 42b in 1b,
Each is configured as a pn junction diode using the well regions 41a and 41b as anodes and the n-type diffusion regions 42a and 42b as cathodes.

According to such a diode structure, since the semiconductor substrate 40 is n-type, the well region 41 is formed.
A pnp-type parasitic bipolar transistor QX is formed between a, 41b, the semiconductor substrate 40, and the p-type diffusion layers serving as the drain and source regions of the p-channel MOSFETs M1 to M6 constituting the operational amplifier circuit 2. Therefore, the voltage of the input terminal t2 is equal to the potential of the semiconductor substrate 40 (V
If the value is higher than dd), the parasitic transistor QX is turned on, and a current may flow in various regions formed by the p-type diffusion region on the semiconductor substrate 40, and the circuit may malfunction. Note that the parasitic transistor Qy is also provided on the diode D2 side.
However, there is no problem because this parasitic transistor is local and does not cause a malfunction of the internal circuit even if a current flows. Therefore, in this embodiment, the clamping means 24
a, 25a are provided to clamp the input voltage so that the parasitic transistor QX is not turned on for a certain abnormal input voltage.

The protection diodes D1 to D4 are:
When a reverse voltage is applied, a leakage current of several pico-amps to several nano-amps flows. However, since the protection diodes having the same structure are used for both, the reverse leakage of the protection diodes on the power supply voltage Vdd side and the GND side is performed. The currents are added and cancel each other, so that the input bias current becomes zero.

FIG. 4 shows a modification of the present invention. In this modification, as shown in FIG.
Source region of ET M1 and protection diode D on Vdd side
One p-well region is formed as a common region. That is, the gate electrode and the drain region 45 of the MOSFET M1 are connected to the p-well region 4 of the first protection diode D1.
1 to form the first protection diode D1.
Is used as the source region of the MOSFET M1. Thereby, an increase in area can be suppressed.

In the embodiment shown in FIG.
a, the source region 44 and the substrate 4 are also provided in the MOSFET M1.
A leakage current occurs in the parasitic diode between 0 and this leakage current causes an input bias current at the input terminal. However, with the configuration as shown in FIG. 4, the leakage current of the clamp means is eliminated, and the protection diodes D1 and D2
The input bias current can be further reduced by canceling out the leak currents (D3 and D4). In the embodiment of FIG. 2, the shape of the protection diode D1 on the power supply voltage Vdd side and the shape of the protection diode D2 on the ground potential GND side are slightly different (for example, the n-type diffusion region 42a on the GND side is replaced with the n-type diffusion region on the power supply voltage Vdd side). Smaller than diffusion region 42b), M
It is also possible to configure such that the input bias current including the leak current between the source and the substrate of the OSFET M1 is offset.

Further, the first and second protection diodes D
A reverse current also occurs in the parasitic diode DX formed by the pn junction between the p-well region 41 of D1, D2 and the semiconductor substrate 40, but the electron concentration of the semiconductor substrate 40 is formed in the p-well region 41. Since the electron concentration is at least one order of magnitude lower than the electron concentration of the n-type diffusion region 42, the depletion layer is widened and the reverse current of the parasitic diode DX is at least one order of magnitude smaller than that of the first and second protection diodes D1 and D2 and is ignored. You can do it.

Third and fourth protection diodes D3 and D4
Corresponds to an input voltage Vin + having a phase opposite to that of the input voltage Vin−, and corresponds to the first and second protection diodes D1,
Since the configuration is the same as that of D2 and has the same operation, the description is omitted.

Next, the operation of the clamping means 24a, 25a will be described.

The clamping means 24a and 25a are connected to one of the enhancement-type p-channel MOSFETs M1 and M2.
The gate terminals and the base (well region or substrate) of the MOSFETs M1 and M2 are connected to the first power supply voltage Vdd, the source terminal is connected to the input terminal t2, and the drain terminal is connected to the ground. In these clamping means 24a, 25a, input terminals t2,
When a voltage higher than the first power supply voltage Vdd is applied to t3, the channels of the MOSFETs M1 and M2 are turned on, and the input terminals t2 and t3 are connected to the ground terminal (GND).
Apply current to Moreover, in this embodiment, the MOSFET
As for the threshold voltages of M1 and M2, since the substrate potential is not the source potential but the same potential as the gate voltage, the threshold voltage (0.7 V) of the other MOSFET M3 and the like due to the substrate effect.
The threshold voltage is lower than the threshold voltage, for example, about 0.3 V.

Thus, when a voltage 0.3 V higher than the power supply voltage Vdd is applied to the input terminals t2 and t3,
MOSFETs M1 and M2 turn on and input terminals t2 and t
3 is connected to the ground potential, and the voltage of the input terminals t2 and t3 is lower than the ground potential by the threshold voltage Vt of the MOSFETs M1 and M2.
The voltage is clamped to a voltage (Vdd + Vth) higher by h (0.3 V). But MOSFET
When the current flowing through M1 and M2 increases, the gate-source voltage Vgs gradually increases, and the input terminals t2 and t2
The clamp voltage of No. 3 also gradually increases. However, until the voltage at the input terminals t2 and t3 exceeds the forward voltage at which forward current flows through the protection diodes D1 and D3, the input voltage Vin
−, Vin + is clamped, and the parasitic transistor QX is turned on to prevent leakage current from flowing.

Next, the operation when an abnormal voltage is input to the operational amplifier circuit 2 of the above embodiment will be described in more detail.

First, the case where a voltage lower than the ground potential is applied to the negative-phase input terminal t2 will be described. When a voltage lower than the ground potential is applied to the negative-phase input terminal t2, the forward bias voltage (0.7
V), the second protection diode D2 is turned on and energized, and the voltage of the input terminal t2 is fixed at a potential (eg, -0.7 V) obtained by subtracting the forward bias voltage of the protection diode from the ground potential. , MOS constituting internal circuit
The gate is prevented from being broken by preventing a large negative voltage from being applied to the gate of the FET.

In the operation when a negative voltage is applied to this input terminal, only the current flows from the ground to the n-type diffusion region 42b of the cathode through the p-well region 41, which is the anode of the second protection diode D2. On the D1 side, the parasitic transistor QX is not turned on because the n-type diffusion region 42a is set to a negative voltage, so that no malfunction of the circuit occurs.

Next, a case where a voltage higher than the first power supply voltage is input to the negative-phase input terminal t2 will be described. When a voltage higher than the first power supply voltage is applied to the input terminal t2 and first exceeds the threshold voltage (0.3 V) of the MOSFET M1 of the clamp means 24a, the voltage of M of the clamp means 24a is reduced.
OSFET M1 is turned on. When the MOSFET M1 is turned on, the voltage of the input terminal t2 becomes
1 is clamped to a potential obtained by adding the threshold voltage (0.3 V) to the power supply voltage Vdd.

In the ON operation of the clamping means 24a,
Since only a current flows between the source and the drain of the MOSFET M1, the output waveform of the operational amplifier is saturated, but it is possible to prevent the parasitic transistor QX of the protection diode D1 from being turned on, so that the internal circuit does not malfunction.

In the case where the abnormal voltage is temporarily short or the voltage value is not so large, the clamping means 2
4a, the input terminal t2 is clamped.
The voltage input to 2 returns to the normal level and the MOSFET
M1 is turned off, and normal operation continues in the operational amplifier circuit 2.

On the other hand, when the abnormal voltage is long or the voltage value is particularly large, the amount of current flowing between the source and the drain of the MOSFET M1 of the clamping means 24a increases, and the voltage between the gate and the source of the MOSFET M1 increases. Vgs is increased. When the voltage obtained by adding the voltage Vgs to the threshold voltage (0.3 V) exceeds the forward bias voltage (0.7 V) of the first protection diode D1, the first protection diode D1 is turned on and the input terminal is turned on. A current flows from t2 to the power supply voltage Vdd, and the input terminal t2 is clamped at a potential obtained by adding the forward bias voltage (0.7 V) of the protection diode to the power supply voltage Vdd, thereby preventing the elements constituting the internal circuit from being destroyed.

When a large voltage that turns on the first protection diode D1 is input, the protection diode D1
The parasitic transistor QX constituted by the p-well region 41, the n-type substrate 40, and the p-type semiconductor region of another element is turned on, and the operational amplifier circuit 2 may malfunction. The malfunction of the operational amplifier in this case is not considered a problem. However, even if the applied voltage cannot be protected by the clamp means 24a due to the ON operation of the first protection diode D1, the input MOSFET is not used.
M5 and M6 can be protected and electrostatic breakdown can be prevented.

When a voltage lower than the ground potential or a voltage higher than the power supply voltage Vdd is applied to the positive-phase input terminal t3, the input protection circuit 25 operates in the same manner as the input protection circuit 24 of the negative-phase input terminal t2. Therefore, the description is omitted. [Second Embodiment] FIG. 5 is a circuit diagram of a second embodiment of an operational amplifier circuit suitable for applying the present invention, and FIG. 6 is a sectional view of a protection diode structure of the operational amplifier circuit of FIG. .

This embodiment is an example in which an operational amplifier circuit is provided on a p-type semiconductor substrate. Since the semiconductor substrate 40 is p-type, the substrate potential applied to this substrate is the ground potential. That is, in this embodiment, the ground potential corresponds to the first power supply voltage, and a higher power supply voltage Vdd (for example, 5 V) corresponds to the second power supply voltage. Further, the protection diodes D2 and D4 on the ground potential side are connected to the first protection diode, and the protection diodes D2 and D4 on the power supply voltage Vdd side.
1, 1 and 3 correspond to the second protection diode.

In this embodiment, the input protection circuit 2
Reference numerals 4 and 25 each include four protection diodes D1 to D4 provided corresponding to the two input terminals t2 and t3, and clamp means 24b and 25b.

The protection diode D corresponding to the input terminal t2
1, D2 is a p-type semiconductor substrate 4 as shown in FIG.
0, an n-type well region 51 is provided.
1 is provided with an n-type diffusion region 52, and the well region 51 is used as a cathode and the n-type diffusion region 52 is used as an anode. Protection diode D3 corresponding to input terminal t3
The same applies to D4.

The operations and functions of the protection diodes D1 to D4 of the input protection circuits 24 and 25 are substantially the same as those of the first embodiment except that the ground potential and the power supply voltage Vdd are symmetrical to those of the first embodiment. It is.

On the other hand, according to such a protection diode structure, since the semiconductor substrate 40 is p-type, the well region 5 is formed.
1, an n-type semiconductor region (eg, n-channel MOSFETs M1 and M7) in the semiconductor substrate 40 and the operational amplifier circuit 5.
To M11 drain region and source region).
Shaped parasitic transistor QX is formed. Then, the voltage of the input voltage becomes lower than the potential of the semiconductor substrate 40,
When the parasitic transistor QX is turned on, the semiconductor substrate 4
There is a possibility that a leak current flows to the n-type semiconductor region of the circuit constituent element on 0 and the circuit malfunctions.

In this embodiment, the n-channel M
A ramp means 24b is provided which is composed of an OSFET M1a. The gate terminal and the substrate potential of the MOSFET M1a are set to the ground potential, and the source terminal is set to the input terminal t2.
And the drain terminals are connected to the power supply voltage Vdd. Therefore, the clamping means 24b is connected to the input terminal t.
When the voltage input to the terminal 3 becomes lower than the ground potential, by connecting the power supply voltage Vdd to the input terminal t3, the voltage of the input terminal t3 is clamped almost to the ground potential, and the parasitic bipolar QX is turned on. To prevent

As described above, according to the operational amplifier IC1 of the first and second embodiments, each of the input terminals t2 and t3
And protection diodes D1 to D4 connected in the reverse direction between the power supply voltage and the first and second power supply voltages, it is possible to protect the internal circuit against application of a voltage that is too high or too low. The electrostatic breakdown strength can be improved. At the same time, since the structure of the two protection diodes is the same, the respective leakage currents can be offset from each other, whereby the magnitude of the input bias current can be reduced.

Further, for the protection diode (the first protection diode D1 in the first embodiment, the second protection diode D2 in the second embodiment) which causes the circuit to malfunction due to the operation of the parasitic transistor QX, the clamping means 24a is used. , 24b
Clamps the input voltage to prevent the malfunction of the circuit without ignoring the protection diode for a certain amount of abnormal voltage, and to protect the protection diode only for the abnormal voltage that cannot be dealt with by the clamping means 24a and 24b. Therefore, a highly reliable circuit that does not easily cause a malfunction even when the input voltage exceeds the power supply voltage without lowering the strength against electrostatic breakdown can be realized.

The MO constituting the clamping means 24a
By integrally forming the source region 44 of the SFET M1 and the p-type well region 41 of the first protection diode D1 as a common region, an increase in occupied area can be suppressed, and the source region 44 of the MOSFET M1 can be reduced. Leakage current flowing from the substrate to the substrate 40 can be eliminated, and the input bias current of the input terminal t2 can be further reduced.

Further, the structure of the protection diodes D1 to D4 and the clamp means 24a and 24b as in the embodiment is used for the protection diode and the clamp means, so that the operational amplifier circuits including the input protection circuits 24 and 25 are the same CMOS circuit. It can be formed by a process.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, as the clamping means 24a and 24b, those in which the MOSFETs M1 and M2 are connected as shown in FIGS. 1 and 5 are exemplified. However, the gate terminals of the MOSFETs M1 and M2 are not necessarily connected to the power supply voltage Vdd or the ground potential, but are arbitrarily set. May be applied to control the operating range of the clamp means. In addition, any configuration may be used as long as the input terminal voltage can be clamped by turning on in a voltage range from the time when the voltage of the input terminal exceeds the power supply voltage to the time when the protection diode turns on, such as using a bipolar transistor.

It goes without saying that there are various modifications of the circuit configuration of the operational amplifier specifically shown in the embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to an operational amplifier IC, which is the field of application, has been described. However, the present invention is not limited to this. CMOs that operate with low power, such as regulators and modulation / demodulation circuits
It can be widely used for S linear circuits.

[0057]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a high electrostatic breakdown strength can be obtained with respect to the application of an abnormal voltage in the input voltage, and a highly reliable circuit that does not easily malfunction even when the input voltage exceeds the power supply voltage is realized. There is an effect that can be.

In addition, there is an effect that the input offset current can be reduced in the operational amplifier by reducing the magnitude of the input bias current of the circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an operational amplifier and an input protection circuit suitable for applying the present invention.

FIG. 2 is a sectional view showing a protection diode structure of the input protection circuit of FIG.

FIG. 3 is a top view showing the overall configuration of an operational amplifier IC incorporating the circuit of FIG. 1;

FIG. 4 shows p of a source terminal of a MOSFET of a clamp means.
FIG. 4 is a cross-sectional view showing an example of a protection diode structure in which a semiconductor and a p-well of a first protection diode are integrally formed.

FIG. 5 is a circuit diagram showing an embodiment of an operational amplifier and an input protection circuit configured on a p-type semiconductor substrate suitable for applying the present invention.

6 is a cross-sectional view illustrating a protection diode structure of the input protection circuit of FIG.

FIG. 7 is a circuit diagram showing an example of a conventional input protection circuit.

FIG. 8 is a sectional view showing a conventional input protection circuit and a protection diode structure of an internal circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 operational amplifier IC 2, 3 operational amplifier circuit D <b> 1 to D <b> 1 first to fourth protection diodes M <b> 1, M <b> 2 MOSFET of clamp means 21 differential amplifier circuit 23 output buffer circuit 24 input protection circuit 24 a clamp means 40 semiconductor substrate 41 protection diode p Well region 42 N-type diffusion layer 44 Drain region of clamp means 45 Source region of clamp means 50 Well region of protection diode shared with drain region of clamp means t1 output terminal t2, t3 input terminal t3 input terminal t4 second power supply Terminal t8 First power supply terminal DX Parasitic diode QX Parasitic transistor Vin +, Vin− Input voltage Vout Output voltage Vdd First power supply voltage Vss Second power supply voltage

Claims (7)

[Claims] A first protection diode connected in a reverse direction between an input terminal and a first power supply voltage;
A second protection diode connected in the reverse direction between the first protection diode and the power supply voltage, and a voltage at which the voltage at the input terminal exceeds the first power supply voltage and does not reach a voltage for turning on the first protection diode. And a clamp means for clamping the input terminal to the first power supply voltage when the input terminal is turned on. 2. An input circuit comprising a MOSFET, wherein the input terminal comprises a MOSFET constituting the input circuit.
2. The input protection circuit according to claim 1, wherein the gate terminals are connected. 3. The first and second protection diodes comprise a p-type or n-type well region formed in a semiconductor substrate and an n-type or p-type semiconductor region formed in the well region. The input protection circuit according to claim 1, wherein the input protection circuit includes pn junctions having the same structure. 4. The clamp means includes a MOSFET having a gate terminal and a base connected to a first power supply voltage, a source terminal connected to the input terminal, and a drain terminal connected to a second power supply voltage. Claim 1 to claim
3. The input protection circuit according to any one of 3. 5. A MOSFET as said clamping means.
5. The p-type or n-type semiconductor region constituting the source region of claim 1 and the p-well region or n-well region of the first protection diode are integrally formed as a common region. Input protection circuit. 6. A linear circuit and the input protection circuit according to claim 1 are provided on one semiconductor substrate,
When the voltage inputted to the linear circuit becomes an abnormal voltage outside the range of the first and second power supply voltages, the linear protection circuit is protected by the input protection circuit. Semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 6, wherein said linear circuit is an operational amplifier.