JPH02114942U - - Google Patents
Info
- Publication number
- JPH02114942U JPH02114942U JP2224289U JP2224289U JPH02114942U JP H02114942 U JPH02114942 U JP H02114942U JP 2224289 U JP2224289 U JP 2224289U JP 2224289 U JP2224289 U JP 2224289U JP H02114942 U JPH02114942 U JP H02114942U
- Authority
- JP
- Japan
- Prior art keywords
- mounting board
- semiconductor chip
- ceramic film
- region
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の第１実施例の縦断面図、第２
図は本考案の第２実施例の縦断面図である。
１……実装基板、２……導体膜、３，３Ａ……
セラミツク膜、４……半導体チツプ、５……金ワ
イヤ、６……モールド材。
Fig. 1 is a vertical sectional view of the first embodiment of the present invention, and the second
The figure is a longitudinal sectional view of a second embodiment of the present invention. 1... Mounting board, 2... Conductor film, 3, 3A...
Ceramic film, 4... semiconductor chip, 5... gold wire, 6... molding material.
Claims (1)
体装置において、前記実装基板には少なくとも前
記半導体チツプを搭載する領域の表面にセラミツ
ク膜を形成したことを特徴とする半導体装置。 1. A semiconductor device in which a semiconductor chip is directly mounted on a mounting board, characterized in that a ceramic film is formed on at least a surface of a region of the mounting board where the semiconductor chip is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2224289U JPH02114942U (en) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2224289U JPH02114942U (en) | 1989-02-28 | 1989-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02114942U true JPH02114942U (en) | 1990-09-14 |
Family
ID=31240181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2224289U Pending JPH02114942U (en) | 1989-02-28 | 1989-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02114942U (en) |
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1989
- 1989-02-28 JP JP2224289U patent/JPH02114942U/ja active Pending