JPH02113670A - Run length processing circuit - Google Patents

Abstract

PURPOSE:To contrive the high speed of a processing to calculate the continuous length of the same color picture elements by converting run length data into address signals with a converting means to be hardware, and accessing a memory. CONSTITUTION:A means 11 is provided which generates the run length data to apply the continuous length from a change point to the next change point in the respective picture element data on a scanning line in the range from a minimum value to a maximum value. Run length data RL4 to RL15 outputted from the run length data generating means 11 are converted and generated to memory address signals MA1 to MA9 for a RAM10 by a converting means 12. Consequently, when the number of the picture elements included in one scanning line is >=the memory capacity of the RAM 10, since the number of the exchange of the data for the RAM10 is taken into consideration, and the continuous length is calculated, a software processing is made unnecessary. Thus, the processing to calculate the continuous length of the same color picture elements can be shortened by a time consumed for such a software processing as usual.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to image data encoding processing and run-length processing technology therefor, such as detection of continuous length from one change point to the next change point in image data on one scanning line in facsimile. It relates to techniques that are effective when applied to [Prior Art] In order to shorten data transmission time in facsimiles and the like, image data is compressed on the sending side. transmission

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows. In other words, scanning data is temporarily stored sequentially corresponding to the scanning line in a memory whose storage capacity is smaller than the number of data bits included in one scanning line, and data is stored from one change point of the stored data to the next change point. In the run non-guess processing circuit for generating the continuous length of pixel data on the scanning line, run length data is generated to give the continuous length from the change point to the next change point in the range from the minimum to the maximum. Means is provided, and run length data outputted from the generating means is converted and generated by a converting means into an address for the memory. [Operation] According to the above-mentioned means, by converting run-length data into an address signal using conversion means such as hardware and accessing the memory, it is possible to perform processing such as that required in encoding image data. This speeds up the process of calculating the continuous length of pixels of the same color. [Embodiment] FIG. 1 shows an embodiment of a run length processing circuit according to the present invention. The run length processing circuit shown in the figure is used to encode the continuous length of pixels of the same color until each pixel in a scanning line changes from white to black and from black to white using the MH encoding method, although it is not particularly limited. It is included in the LSI and is applied to detecting the continuous length from a change point to the next change point of image data on one scanning line in facsimile. In FIG. 1, reference numeral 10 denotes a RAM (Random Acoustic Memory) such as a buffer for sequentially capturing image data on one scanning line read from a sensor such as an image reading scanner. Although not particularly limited, this RAM 10 has a ×16 configuration in which data can be input/output in parallel in units of 16 bits, and is accessed by 9-pitch 1-memory address signals MA, -MA9. 1 read by the sensor not shown above
The number of pixels per scanning line is larger than the data pixels or storage capacity of the RAM. In other words, the maximum continuous length of two same-color pixels in one scanning line exceeds the number of data bits in RAM 1-0 by 5, where the number of pixels px, . . . ~Pxn included in one imaginary scanning line is especially There is no limit, but 64.
K is picked. In this case, the continuous length of pixels of the same color until the pixels change from white to black and from black to white, that is, the run length, is RL,1 to RT,5, as exemplarily shown in FIG. This run length R1, ]--RL5 is actually data indicating the number of pixels included in the range, and according to this embodiment, it is a 16-bit data that can arbitrarily represent the number of pixels in a maximum of 64 bits. It is composed of the following data. In this embodiment, the 16-bit data constituting the run length is hereinafter simply referred to as run length data RL o-RL.
Let it be s. The run length processing circuit of this embodiment processes run length data RT, , o-RL1 . The lower 4 bits RL of . ~RL, 12-bit run length data RL, 4~RL1 . The run length data generation means 11 is provided to sequentially output the run length data according to an internal control procedure. Run-length data Rr, which is output from the run-length data generating means 11. , ~RT,,, are supplied to the conversion means 12, which converts the run length data RL4 to RL13.
are converted into 9-bit memory address signals MA1 to MAg and supplied to the two-layer RAM 10. Although not particularly limited, the conversion means 1-2 converts the run-length data RT, , 4 according to the relationship between the number of bits of the memory address signals MA, to MA9 and the number of bits of the run-length data R'L4 to RL1F. ~RL,. are output as they are as memory address signals MA, ~MA, and are substantially the run length piggybacks of the upper 5 bits RL□1~RL1.
．． memory to the upper two pins; input signals MA, l,
Convert to MA9. This conversion mode, as shown in FIG.
1. For a series of 32 binary changes in
2-bit memory address signal MA8. MA9 is r
o, OJ, "]. O", ro, 1. Three changes in J are repeated in sequence. That is, 12-bit run length data RL4 to RT
The 9-bit memory address signals MA, .about.MA are cycled every 27×3 changes from the lower side of −1, s. FIG. 3 shows a detailed example of the conversion means 12 for realizing the conversion mode shown in FIG. 2. In Fig. 3, INVI to INV5 are inverters, NA
ND1 to NAND8 are Nantes Gate, EXORI, EX
OR2 is an exclusive OR gate, AND1 to AND12 are AND gates that receive inverted inputs to perform NOR logic, and O
RI to OR4 are three-man OR gates, and OR5 and OR6 are OR gates that receive inverted inputs to perform NAND logic. Memory address signal M output from the conversion means 12
16 addressed and read by A1 to MAg
Bits I ~ data D. -D 1. s is supplied to the white/black change detection circuit 13. The white/black change detection circuit 13 receives 16-bit read data D. -D□, it is determined whether there is a change from self to black or from black to white, and if there is a change, the detection signal S is asserted. If there is a further change, 4-bit run length data RL to RL indicating the position is generated. The lower 4-bit run length data RLo-RL3 outputted from the white/black change detection circuit 13 is sent to the synthesis circuit 14 together with the 12-bit run length data RL, ~RL1 outputted from the run length data generation means 11. Supplied. This synthesis circuit 3-4 generates -2 bit run length data RL4 to RL1. is shifted to the upper part by 4 bits, and the 4-bit run length data RL is placed in the lower part.
o-RL3 is inserted, and 16-bit run length data Rr. ~RL, , is synthesized. The combined 16-bit run length data RLo-RL15 is supplied to the arithmetic circuit 15. Although not particularly limited, the arithmetic circuit 15 calculates the current run length data at timings corresponding to changes in the detection signals S to asserted in response to pixel data on a scanning line being changed to white/black. RLo-RL, , is taken in and held, and the run length data RT held before that. ~RL, and from this, the continuous length of pixels of the same color until the pixel changes from white to black, or from black to white, ie, the run length RT, is calculated. The run length RL calculated by the arithmetic circuit 5 is encoded or compressed by the encoding circuit 16, although this is not particularly limited. Incidentally, internal operation control such as run-length data output control in the run-length data generation means 1 and arithmetic control in the arithmetic circuit 15 is not particularly limited, but is controlled according to a microprogram. According to the embodiment described above, the following effects can be obtained. (1) Scanning data is temporarily stored sequentially corresponding to the scanning line in RAM, i-0, which has a small storage capacity compared to the number of pixels included in one scanning line, and In the run length processing circuit that generates the continuous length from the change point to the next change point in each pixel data on the scanning line, run length data is used to give the continuous length from the minimum to the maximum change point in each pixel data on the scanning line. A means 11- for generating run length data RL4 to RL1 . is provided, and run length data RL4 to RL1 . , are converted into memory address signals MA, ~MAg for the two-layer RAM 1O by the conversion means 12. This results in
When the number of pixels included in one scanning line is greater than or equal to the storage capacity of RAM 10, there is no need for software processing to calculate the continuous length in consideration of the number of data exchanges in RAM 10, and conventional methods The process of calculating the continuous length of pixels of the same color, that is, the run length RL, can be accelerated by the time that would have been spent on software processing. (2) - From the effect described in (h), the number of program steps for calculating the run length RL is reduced, so that the overall burden on the software can be reduced. Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. For example, the calculation for calculating the run length RL based on the run length data RLo-RL, 5 output from the synthesis circuit 14 is not limited to the above embodiment, and the run length is calculated in response to the detection of the white/black change point. The output of the data generation means 11 may be switched and controlled. Also, RAM
is not limited to the ×16 bit configuration and can be changed as appropriate. For example, when a ×8 bit RAM is adopted, the run length data generation means 11 generates the run length data R.
The white/black change detection circuit can be modified to output 3-bit run length data RLo-RL2. Further, in the above embodiment, the calculated run length RI is encoded, but it can also be used as is without being compressed. In the above explanation, the invention made by the present inventor was mainly explained as being applied to an LSI for facsimile that supports 1 the MW encoding method, which is the field of application that formed the background of the invention, but the present invention is not limited thereto. It can be widely applied to various semiconductor integrated circuits for encoding processing of image data, which also support MR (Modified READ) system. The present invention can be applied to conditions where a memory whose storage capacity is smaller than the number of data bits included in at least one scanning line is accessed and image data is encoded by type, such as white/black. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. In other words, a run-length processing circuit reads a memory whose storage capacity is small compared to the number of pixels included in one scanning line and generates a continuous length from one change point to the next change point in a series of data. By providing means for generating run length data to give the continuous length in the range from the minimum to the maximum, and by adopting a configuration that converts and generates the run length data output from this generating means into a memory address, 1. When the number of pixels included on a scanning line is greater than the storage capacity of the memory, there is no need for software processing to calculate the continuous length by taking into account the number of data exchanges for the memory as in the past. This has the advantage that the process of calculating the continuous length of the same pixel, that is, the run length, can be accelerated by the time that was conventionally spent on such software processing. Furthermore, this makes it possible to reduce the overall burden on the software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a run-length processing circuit according to the present invention, FIG. 2 is an explanatory diagram showing an example of a conversion mode between run-length data and a memory address signal, and FIG. 4 is an explanatory diagram illustrating the relationship between pixel data on one scanning line and run length, and FIG. 5 is a memory address signal. FIG. 2 is a schematic explanatory diagram showing a conventional means for obtaining a run length from an image. 10...RAM, 1]-Run length data generation means, 12.Conversion means, 13.White/black change detection circuit, 1-4
... Synthesis circuit, 15... Arithmetic circuit, 16... Encoding circuit, RLo-RL s, s... Run length data, MA□ to MA9... Memory address signal, RT,
...Run length.

Claims (1)

[Claims] 1. Scanning data is temporarily stored sequentially in correspondence with the scanning line in a memory whose storage capacity is smaller than the number of data bits included in one scanning line, and the change point of the stored data In a run length processing circuit that generates a continuous length from a change point to the next change point in each pixel data on a scanning line, a run length processing circuit is used to generate a continuous length from a change point to the next change point in each pixel data on a scanning line, from the minimum to the maximum. A run-length processing circuit comprising means for generating length data, and conversion means for converting the run-length data outputted from the generation means into an address in the memory. 2. The above memory inputs and outputs 2^m bits of data in parallel, and the run length data does not include the lower m bits of the number of bits required to define the continuous length, 2. The continuous length is generated based on m-bit data indicating a changing bit position among 2^m bits of memory cell data and run-length data output from the generating means. 1. The run length processing circuit according to 1. 3. The conversion means converts a series of binary changes in the upper n bits of the run-length data into the upper i bits of the memory address.
3. The run-length processing circuit according to claim 1, wherein the run-length data is converted into a memory address so as to correspond to repeated binary changes in bits.