JPH04207470A - Image processor - Google Patents

Abstract

PURPOSE:To suppress the generation of the pseudo contours of images and to simplify constitution as well as to attain a cost reduction by binarizing each piece of the data formed by dividing image data to n pieces of image data and calculating data of 2<n> value from n pieces of the binarized image data. CONSTITUTION:An input means 101 inputs the image data to a picture element unit and a dividing means 104 divides the image data inputted by the input means 101 to n pieces (n>=2) of the image data. Binarizing means 105a to 105d binarizes respective pieces of the data divided by the dividing means 104 and a binarization computing means 106 calculates the data of 2<n> value from n pieces of the image data binarized by the binarizing means 105a to 105d. The inputted image data is divided to n pieces (n>=2) of the image data in such a manner and the respective pieces of the divided data are binarized. The data of 2<n> value are calculated from n pieces of the binarized image data. The gradation characteristic and resolution of the images improved in this way and the hardware is improved and simplified. The cost is reduced and the generation of the pseudo contours is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and for example, to an image processing device that quantizes multi-valued image data into 2n-valued data.

[Conventional technology]

Conventionally, in this type of apparatus, a halftone method, a dither method, an error diffusion method, etc. have been used as a method for displaying a grayscale image in binary terms. Recently, these binarization methods have been expanded to support three or more levels of gradation for output devices that can produce gradations of three or more levels.

[Problems to be Solved by the Invention] However, in the conventional examples described above, when quantization is performed using these methods, false contours occur in portions of the image where the gradation changes gradually. Further, there are disadvantages in that the processing becomes complicated and the hardware scale increases.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and its purpose is to provide an image processing device that suppresses the occurrence of false contours in images and can be configured with inexpensive hardware. .

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the purpose, an image processing apparatus according to the present invention includes an input means for inputting image data pixel by pixel, and an image processing apparatus for inputting image data by the input means. a dividing means that divides the data into n pieces of image data (n≧2); a binarizing means that binarizes each data divided by the dividing means;
21 from the n image data binarized by the binarization means.
The method is characterized by comprising a calculation means for calculating value data.

[Operations] According to such a configuration, the input means inputs image data pixel by pixel, and the dividing means divides the image data inputted by the input means into n pieces of image data (n≧2), and the dividing means divides the image data inputted by the input means into n pieces of image data (n≧2). The dividing means binarizes each divided data, and the calculating means calculates 2'' value data from the n image data binarized by the binarizing means.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment> FIG. 1 is a block diagram showing a first embodiment of an image processing apparatus according to the present invention. In the figure, 101 is an input sensor section, 102 is an analog/digital (A/D) converter section, 1
03 is a correction circuit, 104 is a conversion table, 105a, 1
05b, 105c.

105d represents a binarization circuit, 106 represents an arithmetic circuit, and 107 represents a printer.

Here, FIG. 5 is a diagram illustrating input/output characteristics according to the conversion table 104 of the first embodiment.

In operation, the input sensor section 101 is composed of a photoelectric conversion element such as a CCD and a driving device that scans the element, and reads and scans a document. The image data of the document read by the input sensor unit 101 is sequentially sent to the A/D converter 102. Here, the data of each pixel is 8 bits (0~255
) is quantized into digital data 5a(i,j). Next, a correction circuit 103 performs shading correction and the like to correct unevenness in sensitivity of the CCD sensor and unevenness in illumination due to the illumination light source, etc., by digital calculation processing. This corrected data is input to the conversion table 104. The conversion table 104 converts four 8-bit digital data S+(i, jl.) according to the value of 5o(i,+).

S 2fi, j), S s(i, j), S 4(i
, j) and output.

This conversion table 104 outputs values according to the table shown in FIG. The following equation (]) holds between input data and output data. That is, So(1,j)=□・S +(i, jD□・5z(i,
j1+□・5s(i,,+)”□・54(i,j)・・
・(1) The conversion table is created to maintain this relationship.

The signal S+(i.

j) + S tD, j) + S a(i, j), S
<(i, j) are binarization circuits 105a and 105b, respectively
, 105c, and 105d.

The binarization circuit 105a binarizes S+(t9.+) into 1
A bit signal Bl (1, J) is output. Similarly, the binarization circuit 105b outputs B 2 (i, j>, 105 c if Bs (x, +), 105 diiBi (i, j). Details of the binarization circuits 105a to 105d This will be discussed later.

Then, the 1-bit signal B + (i + j) + B 2 (
1, J).

B 3 (i, j) B 4 (i, j) is the arithmetic circuit 10
6 is input. The arithmetic circuit 106 stores the value of Bl (L, J) in the first lower bit, the value of B2 (1, J) in the second lower bit, the value of BS (i, j) in the third bit, and B4.
4-bit data Bo(i.

j) is output. The printer 107 is capable of expressing density in 16 gradations from 0 to 15 with one pixel, and reproduces an image on the record based on 4-bit data sent from the arithmetic circuit 106.

Figure 2 shows a binarization circuit 1 which is a representative of the binarization circuit shown in Figure 1.
05a is a block diagram showing the configuration of 05a.

Note that the binarization circuits 105b to 105d also have the same configuration as the binarization circuit 105a described below.

In Fig. 2, 201 and 202 are 2 bits that have been binarized.
Delay RAM 203 for storing value image data for one line
212 and 216 are DF/Fs (flip-flops) for delaying image data by one pixel, 213 is a CPU that performs weighting calculations on a predetermined area from binary image data around the pixel of interest, and 213a is a program that operates the CPU 213. The stored ROM 213b is a RAM used as a work area for the program in the ROM 213a, and 214 is a 2
A subtractor 215 calculates the difference between the weighted average value output from 213 and the multi-value data of the pixel of interest, and 215 compares the weighted average value output from 213 with the multi-value data of the pixel of interest.
A comparator 217 converts into values; an adder 217 adds the multivalued image data sent from the conversion table 104 and the error data output from the error ROM 218 and error memory 219;
218 is an error R that calculates error data based on the difference between the multi-value data of the pixel of interest sent from the subtracter 214 and the threshold value.
OM, 219 is an error memory that stores error data for one line.

In the above configuration, the comparator 21 outputs binarized data Bi(i,,+) based on the following equation (2).

That is, this binary data is input to the RAMs 202 and 201 for delaying each line, and the binary data B is delayed by one line by the RAM 202.

(1-11J"2) is output as binary data B + (i-2, j+2) delayed by two lines by the RAM 201.

Furthermore, DF/F2O3 is B+(i-2,j+1),
DF/F204 is B 1 (i-2j), DF/F 2
05 is B + (i-2, j-1), DF/F 20
6 is B, (i-2, j-2), DF/F 207 is B + (i-1, j"l), DF/F 208 is B
+ (i-1, j), DF/F 209 is B + (i-
1,j-1), DF/F 210 is Bl(i-1,j
-2), DF/F211 is B, (i, j-1), D
F/F 212 outputs Bl(1, J-2+.

These binary image data are manually input to the arithmetic unit 213, and a weighted average value is calculated according to the following equation (3). That is, (3) where R(x, y) is a weight mask for calculating the weighted average value m(i, l) of the binary image in the vicinity of the pixel of interest.

This average value m (i, l is output as a threshold value. Threshold value m
(i, j) and 5l(1
1j) + E (i, j) is input to a subtractor 214 and a comparator 215. The subtractor 214 calculates the difference between the two inputs, S+(i,j)+E(i,j)-m fi,j
) is calculated. Comparator 215 also has two inputs S +
(i, J) + E b, j) and m(i, jl are compared and binary data B+(i, j) is output.

Multivalued data S of the pixel of interest output from the subtracter 214
+ (i, j) + E (i, j) and threshold m (i, j
) is input to the error ROM 218. MisfiRO
M218 is E 2 (i,, +j
+1) is output. That is, E z(i, j+ll= (S + (i, j)+ E
(i, j) - m (i, j) ) / 2 (4). This Ea(i,j+ll is input to the adder 217 and also to the error memory '219. The error memory 219 stores the error for one line, and Ex(i
9j''l) is output again as E+(i+1.1).

The sum of these two errors, E (i, j+1) = E
+(i, j+l)+E z(i, j+1) is then added to the binary error S l(i, j+i) by the adder 219, and the DF/F 216 adds the added value S+(i,
j+1)+E (i, j+1) is delayed by one data clock period.

The first embodiment uses a simple and inexpensive hardware configuration to produce images with excellent gradation and resolution by using the low-cost binarization processing with gradation expressive power for each bit as described above. It is possible to obtain high-quality image output without generating false contours.

Now, in the first embodiment described above, the CPU
213. Although ROM213a and RAM213b were used,
The present invention is not limited to this, and hardware that implements the above calculation may be used.

<Second Embodiment> FIG. 3 is a block diagram showing a second embodiment of the image processing apparatus according to the present invention, and FIG. FIG. 3 is a block diagram showing the configuration of a circuit 305a. Note that the binarization circuits 305b to 305d also have the same configuration as the binarization circuit 305a.

In this embodiment, the error ROM 218 (FIG. 2) of the first embodiment is replaced with an error ROM 306 that is commonly used by the four binarization circuits 305a to 305d. Note that since the other configurations are the same, the description of the functions will be omitted. Regarding reference numbers, in FIG. 3, 301 is an input sensor section, 302 is an A/D conversion section, 303 is a correction circuit, 304 is a conversion table, 30
5a.

305b, 305c, and 305d are binarization circuits, 307 is an arithmetic circuit, and 308 is a printer. In Figure 4,
401, 402 are delay RAMs, 403 to 412, 416
is DF/F, 413 is CPU, 413a is ROM, 41
3b is a RAM, 414 is a subtracter, 415 is a comparator, 41
7 indicates an adder.

In the above configuration, the error ROM 306 redistributes the sum of errors generated in the four binarization circuits 305a to 305d to each of the 2M conversion circuits 305a to 305d at a constant ratio. In this way, it is possible to prevent the occurrence of roughness in which the ON portions of each of the binarization circuits 305a to 305d concentrate and cause interference. Of course, the same effects as in the first embodiment can be obtained.

Now, also in the second embodiment, the CPU
413. Although ROM413a and RAM413b were used,
The present invention is not limited to this; hardware that implements the above calculation may also be used.

[Effects of the Invention] As explained above, according to the present invention, an image with excellent gradation and resolution can be obtained with a simple and inexpensive hardware configuration, and a high-quality image without false contours can be obtained. I get the output.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of an image processing apparatus according to the present invention, and FIG. 2 is a binarization circuit 1 that is a representative of the binarization circuit shown in FIG.
05a, FIG. 3 is a block diagram showing a second embodiment of the image processing device according to the present invention, and FIG. 4 is a binarization circuit that is representative of the binarization circuit shown in FIG. 3. 3
FIG. 5 is a block diagram showing the configuration of 05a, and is a diagram illustrating input/output characteristics by the conversion table 104 of the first embodiment. In the figure, 101,301...input sensor section, 102.3
02... A/D conversion unit, 103, 303... Correction circuit, 104, 304... = conversion table, 105a,
105b, 105c, 105d, 305a
, 305 b , 305 c , 305 d
-・-Binarization circuit, 106.307... Arithmetic circuit, 1
07,308...Printer, 201,202,401
, 402...delay RAM, 203-212. 21
6,403~412°416...DF/F, 21
3. 413...CPU, 213 a, 4 1
3 a---ROM, 213b, 413b---R
AM, 214,414...Subtractor, 215,415...
... Comparator, 217,417 ... Adder, 218°3
06...Error ROM, 219,418...Error memory.

Claims (7)

[Claims] (1) An input means for inputting image data pixel by pixel; a dividing means for dividing the image data inputted by the input means into n pieces (n≧2) of image data; and a dividing means for dividing each data divided by the dividing means. A binarization means for binarizing, and 2^ from the n image data binarized by the binarization means.
An image processing device comprising: calculation means for calculating n-value data. (2) The dividing means divides the input image data into S_
0, and each image data after being divided into n pieces is S
2. The image processing device according to claim 1, wherein when _1, S_2, . (3) The binarization means includes a calculation unit that calculates a weighted average value of the binarized image data near the pixel of interest, and a calculation unit that converts the image data of the pixel of interest into two by using the average value obtained by the calculation unit as a threshold. A pixel of interest binarization means for converting the pixel of interest into a value, and a distribution means for distributing a density error generated when the pixel of interest is binarized by the pixel of interest binarization to image data of unbinarized pixels surrounding the pixel of interest. The image processing apparatus according to claim 1, further comprising: an image processing apparatus; (4) The image processing apparatus according to claim 1, wherein the binarization means binarizes using a dither matrix as a threshold value. (5) The image processing apparatus according to claim 1, wherein the binarization means uses an error diffusion method. (6) The calculation means is a mathematical formula, a chemical formula, a table, etc., where the n binarized image data are B_1, B_2, ..., B_n, and the calculated image data is B_0. 2. The image processing apparatus according to claim 1, wherein the following relationship holds true: ▼ (i is a natural number). (7) The calculation means calculates the calculated image data B_0.
is represented by n bits from 0 to (2^n-1), the value of the binarized image data B_i is assigned to the i-th bit (1≦i≦n) counting from the lower order. 7. The image processing apparatus according to claim 6, wherein the image data B_0 is obtained by performing the processing from n to n.