JPH11175712A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of bits of a line memory used to binarize multi-valued image data by an error diffusing method. SOLUTION: An error data offset adding circuit 8 subtracts K meeting specific conditions (i.e., -2N<-1> <=K<=2N<-1> -1, where N is the number of bits of the multi-valued image data) from error data from an interest pixel error data calculating circuit 6 and supplies the result to the line memory 9 and then the number of bits of the line memory 9 may be equal to that of interest image data. Then an error data offset adding circuit 10 adds K to the error data from the line memory 9 and then the original data, i.e., the same data with the error data from the interest pixel error data calculating circuit 6 are inputted to a peripheral pixel error data register 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and, more particularly, to pseudo halftone data obtained by A / D (analog / digital) conversion of image reading data of an image processing system such as a facsimile by an error diffusion method. The present invention relates to an image processing device that converts the image data into.

[0002]

2. Description of the Related Art In an image processing system such as a facsimile or the like, image processing is performed on halftone data obtained by A / D conversion of image read data and converted into pseudo halftone data.

As a method of converting halftone data to pseudo halftone data, an error diffusion method, a dither method, or the like is generally used, but a better image can be obtained by the error diffusion method.

In the error diffusion method, as shown in FIG. 1, a binarization error of each pixel in a window around a pixel of interest to be processed is weighted to obtain a sum, and the sum is used as the halftone data of the pixel of interest. The binarization of the target pixel is performed by comparing the addition result with the binarization slice level, and the difference between the addition result and the binarization data of the target pixel is error data of the target pixel. The pixel of interest is scanned, and the above process is repeated. In FIG. 1, * is a target pixel, and A1 to A7 are weight coefficients of pixels in a window. FIG. 2 shows an error diffusion processing circuit. In FIG. 2, reference numeral 1 denotes a peripheral pixel error data register which holds error data of a pixel in a window for calculating error data of a target pixel. 2
Is a weighting operation circuit, and the weighting coefficient A corresponding to each pixel is added to the error data ERRi of the in-window pixel already obtained by the peripheral pixel error data register 1.
Multiply i. Reference numeral 3 denotes an adder circuit, which obtains the sum Σ (ERRi × Ai) of the multiplication results of the weighting operation circuit 2.
Reference numeral 4 denotes an addition circuit, which adds the sum calculated by the addition circuit 3 and the halftone data P of the target pixel. The result, that is, the target pixel data P * to be compared with the slice level (threshold) is

[0005]

## EQU2 ## P * = P + Σ (ERRi × Ai), and this value is compared with the slice level in the magnitude comparison circuit 5. When the value is equal to or higher than the slice level, 1 is output as the binarized data of the target pixel. The error data ERR * of the target pixel in the target pixel error data calculation circuit 6 at this time is

[0006]

ERR * = P *-(2 ^N -1) N: Number of bits of halftone data When P * is smaller than the slice level, the binarized data of the target pixel output from the magnitude comparison circuit 5 is 0, and the error data ERR * of the target pixel in the target pixel error data calculation circuit 6 is ERR * = P *. As described above, the binarized data output from the magnitude comparison circuit 5 is pseudo halftone data, and the error data of the target pixel output from the target pixel error data calculation circuit 6 is the peripheral pixel error with respect to the other target pixels. The data is supplied to the peripheral pixel error data register 1 as data. However, when performing image processing such as error diffusion, there are several lines of processing windows. The data is stored in the line memory 7 (A1 to A5 in the example of FIG. 1, and A6 and A7 are directly supplied to the peripheral pixel error data register 1). Feed to 1.

At this time, if the halftone data is N bits, if the slice level is fixed at the center of the number of gradations, the error data is N bits including the sign. If it is located outside the center, the error data is (N + 1) bits including the sign. Considering the versatility of image processing, the slice level is preferably programmable. The exception is when the slice level is 2 ^{N −1} , and the error data is N bits including the sign bit. This means that if the slice level is 2 ^N-1 ,
Both the binarization error of data smaller than the slice level and the binarization error of data larger than the slice level are 2 ^{N -1.}
This is because it becomes smaller. When the slice level is other than 2 ^N-1 , the binarization error of either the data smaller than the slice level or the data larger than the slice level becomes a value of 2 ^N-1 or more, and the sign bit also becomes larger. (N + 1) bits are included.

[0008]

Therefore, a line memory for storing error data that has a bit number that is one bit more than the bit number of the halftone data is required.

In the case where such an image processing system is constituted by a one-chip IC, the area occupied by the line memory on the chip becomes considerably large. This hinders miniaturization and increases costs.

An object of the present invention is to provide an image processing apparatus which has solved the above-mentioned problems.

[0011]

In order to achieve the above object, according to the present invention, when converting multi-valued image data into binary data by an error diffusion method, error data of a pixel of interest is calculated. Binarization error calculation means, subtraction means for subtracting an offset corresponding to the slice level at the time of the binarization from the error data obtained by the binarization error calculation means, and after subtracting the offset from the subtraction means Storage means for storing the error data, and addition means for adding the offset to the error data from the storage means and supplying the error data to the binary error calculation means.

According to a second aspect of the present invention, in the first aspect, the binarized error calculating means includes a register for holding error data of a pixel in a window for calculating error data of a pixel of interest, and the register A first arithmetic circuit for weighting the error data within the window from
A first addition circuit for obtaining the sum of weighted error data in the window from the arithmetic circuit, and a summation of the weighted error data in the window from the first addition circuit and the pixel data of interest And the error data of the pixel of interest from the addition result from the second addition circuit in response to the binary data responsive to the comparison result between the addition result from the second addition circuit and the slice level. A second arithmetic circuit for performing an arithmetic operation.

Further, in the invention according to a third aspect, in the first aspect, the offset sets the slice level to 2 ^{N -1} +
When K is

[0014]

Equation 4] ^{-2 N-1 + 1 ≦ K} ≦ 2 N-1 -1 ( however, N: the number of bits of the multi-value image data K: the offset), characterized in that a.

Further, the invention of claim 4 is characterized in that, in claim 1, the storage means is a line memory having the same number of bits as the number of bits of the multi-level image data.

[0016]

FIG. 3 shows an error diffusion processing circuit according to an embodiment of the present invention. In FIG. 3, the components having the same reference numerals as those in FIG. 2 are the same as those in FIG. Reference numeral 8 denotes an error data offset adding circuit, which adds an offset described later to the error data of the target pixel from the target pixel error data calculation circuit 6 based on the slice level. The error data from the error data offset adding circuit 8 is input to the line memory 9 having the same number of bits (N) as the pixel data of interest. Reference numeral 10 denotes an error data offset adding circuit, which adds an offset described later to the error data from the line memory 9 based on the slice level and inputs it to the peripheral pixel error data register 1.

Here, the binarization error in the target pixel error data calculation circuit 6 is described in the case where the slice level is 2 ^{N -1} + K (where -2 ^N -1 +1 ≤ K ≤ 2 ^N -1 -1). Specifically, when (data ≧ slice level),

[0018]

## EQU5 ## Since 2 ^N-1 + K ≦ P * ≦ 2 ^N −1,

[0019]

( ^2N-1 + K)-( ^2N- 1) ≤P *-( ^2N
-1) ≦ (2 ^N −1) − (2 ^N −1) That is,

[0020]

-(2 ^N-1 −1−K) ≦ ERR * ≦ 0, and when (data <slice level),

[0021]

## EQU8 ## Since 0 ≦ P * <2 ^N−1 + K,

[0022]

## EQU9 ## 0 ≦ ERR * <2 ^N−1 + K. From this, when the difference K between the slice level and 2 ^{N -1} is 0, ERR * can be represented by N bits including the sign bit, so that an N-bit line memory can be used.
When K is other than 0, ERR * is (N + 1) bits including a sign bit, and a line memory of (N + 1) bits is required. Here, the slice level is 2 ^N-1 +
When K, the error data stored in the line memory is
Is subtracted and stored in the line memory,
From the formula, the data to be stored in the line memory is (data ≧ slice level),

[0023]

-(2 ^N-1 -1) ≤ERR * ≤-K ... When (data <slice level),

[0024]

-K ≦ ERR * <2 ^N−1 .

[0025]

[Equation 12] Under the condition of −2 ^N−1 + 1 ≦ K ≦ 2 ^N−1 −1, the data stored in the line memory is N
You only need a bit. K that satisfies such conditions
(That is, −2 ^N−1 + 1 ≦ K ≦ 2 ^N−1 −1) is subtracted from the error data from the target pixel error data calculation circuit 6 by the error data offset adding circuit 8 and supplied to the line memory 9. The number of bits of the line memory 9 is the same as the number of bits of the image data of interest. The error data from the line memory 9 is added to the error data in the error data offset adding circuit 10 so that the original data, that is, the same data as the error data from the target pixel error data calculation circuit 6 is stored in the peripheral pixel error data register. 1 is input. As described above, when the error data is written to the line memory 9 and when the error data is read from the line memory 9, the bit number of the line memory can be reduced only by adding a simple processing circuit (error data offset adding circuits 8 and 10). Can be reduced.

FIG. 4 is a diagram showing the features of the present invention.
The valuation error calculation circuit 11 includes a peripheral pixel error data register 1, a weighting calculation circuit 2, an addition circuit 3,
4. A target pixel error data calculation circuit 6 is included.

[0027]

As described above, according to the present invention,
The number of bits of a memory used when binarizing multi-valued image data by an error diffusion method can be reduced, and the size of an image processing circuit can be made smaller than before.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of an error diffusion window.

FIG. 2 is a block diagram of a conventional error diffusion processing circuit.

FIG. 3 is a block diagram of an error diffusion processing circuit according to the embodiment of the present invention.

FIG. 4 is a diagram showing features of the present invention.

Claims (4)

[Claims] When converting multi-valued image data into binary data by an error diffusion method, a binary error calculating means for calculating error data of a target pixel, and a binary error calculating means for obtaining the error data. Subtraction means for subtracting an offset corresponding to the slice level at the time of the binarization from the error data, storage means for storing error data after offset subtraction from the subtraction means, and error data from the storage means. An image processing apparatus comprising: an adding unit that adds the offset and supplies the result to the binarization error calculating unit. 2. The method according to claim 1, wherein the binarization error calculation means includes a register for holding error data of a pixel in a window for calculating error data of a target pixel, and an error in the window from the register. A first arithmetic circuit for weighting data, a first adder for calculating the sum of weighted error data in a window from the first arithmetic circuit, and a weight in a window from the first adder A second adding circuit for adding the sum of the obtained error data and the pixel data of interest, and a second adding circuit that responds to the binarized data in response to the comparison result between the adding result from the second adding circuit and the slice level. An image processing apparatus comprising: a second arithmetic circuit that calculates error data of a target pixel from an addition result from the second addition circuit. 3. The method according to claim 1, wherein, when the slice level is 2 ^N−1 + K, the offset is expressed as: −2 ^N−1 + 1 ≦ K ≦ 2 ^N−1 −1 (where N : The number of bits of the multi-valued image data K: the offset). 4. The image processing apparatus according to claim 1, wherein the storage unit is a line memory having the same number of bits as the number of bits of the multi-valued image data.