JPH02112279A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the utility of a gate cell to a chip by constructing a semiconductor integrated circuit with, a region where a gate cell array and a wiring channel are formed, and a region over which the gate cell is laid. CONSTITUTION:A master chip portion 11 comprises a fixed channel region 12 and a free channel region 13. On the fixed channel region 12, many gate cells 14 corresponding to a basic transistor circuit are disposed into an array. Wiring channels 15 are disposed between the gate cells. On the free channel region 13, the gate cells 14 are laid over the entire surface thereof. Such a master chip is previously manufactured in a master process. In response to a user's request, in the fixed channel region 12, longitudinal and transversal wiring layers are formed in the wiring channel 15 to interconnect the gate cells 14. Further, in the free channel region 13, wiring is freely laid on the gate cells 14 to make available the fixed channel region 12 and the free channel region 13 as a logic circuit and a memory. Hereby, the utility of the fixed and free channel regions can be raised.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit, for example, a technique that is effective when applied to a semiconductor integrated circuit having a gate cell. be.

[Prior Art] Gate array type semiconductor integrated circuits have made remarkable progress in the field of random logic in recent years. Regarding the semiconductor integrated circuits of this Goo 1~array method, for example, please refer to the ``LSI Handbook'', 1st edition, No. 20, published by Ohmsha Co., Ltd. on November 30, 1980.
It is described on pages 4 to 207.

FIG. 5 shows an example of this gate array type semiconductor integrated circuit.

In the figure, reference numeral 1 indicates a chip, and gate cells 2 corresponding to transistors, resistors, capacitors, etc. are arranged in an array (column) on this chip. Wiring channels 3 are provided between the cell rows, and the cells 2 are interconnected by two vertical and horizontal wiring layers 4 formed in the wiring channels 3. Around the internal logic section constituted by these gate cells 2 and wiring layer 4, there is an I1 as an external interface section.
A large number of 0 cells 5 are arranged, and a large number of bonding pads 6 for electrical connection with the outside are arranged further outside the cells.

Such a semiconductor integrated circuit is obtained by a manufacturing method called a master slicing method.

This master slicing method is a master process in which the gate cells 2 and wiring channel layers 3 are manufactured in advance for all types of products, and then a wiring layer 4 is formed according to the user's request to separate the gate cells 2. This method performs a slicing process to interconnect interconnections to obtain the gate array type semiconductor integrated circuit, and since the master process is shared, manufacturing can be completed in a short period of time, and the layout is simplified into a matrix. It has the advantage of being easy to automatically lay out wiring.

A so-called fixed channel type semiconductor integrated circuit in which the wiring channel 3 is fixed is particularly effective when the number of gate cells is relatively small.

In other words, when the number of gate cells is small, the width of the wiring channel 3 can be relatively small, so the usage efficiency of the gate cell 2 with respect to the chip is high, but as the number of gate cells increases, the width of the wiring channel 3 can be reduced accordingly. This is because the width of the gate cell 2 has to be made considerably large, and the usage efficiency of the gate cell 2 with respect to the chip 1 becomes low.

[Problems to be Solved by the Invention] Recently, there has been a strong demand for such gate array type semiconductor integrated circuits to be equipped with advanced functions. That is, there is a demand for memory functions such as ROM and RAM.

Conventionally, the gate cells 2 of the semiconductor integrated circuits of the array type have been used to form, for example, flip-flops and the like to have a memory function to meet the above requirements.

However, the gate array type semiconductor integrated circuit equipped with the memory described in 1 above has the following problems.

That is, in a system in which a memory is configured using flip-flops or the like, the wiring channel 3 is fixed, so the wiring length inevitably becomes long, and the characteristics of the memory cannot be fully demonstrated. This tendency becomes more pronounced as the number of gate cells increases. This is because, as the number of gate cells increases, as described above, the width of the wiring channel 3 must be increased accordingly, resulting in an increase in the length of the wiring.

Here, the Sea of Gate (Sea of Gate) is designed to solve the above problem by spreading the gate cells 2 over the entire surface of the chip 1.
Of Gate) method is known.

This sea-of-gate method eliminates the wiring channel 3, which is a feature and drawback of the semiconductor integrated circuit of the gate array method described in 1. Gate cells are spread over the entire surface, and later wiring between the gate cells 2 is freely performed to form a memory. It is also called the free channel type because it allows for free wiring. As mentioned above, in this free channel type semiconductor integrated circuit, the gate cells 2 are spread over the entire surface of the chip 1, and the wiring area is minimized in order to freely conduct wiring between the gate cells 2 using the gate cells 2''. In particular, when used as a memory, the wiring length can be shortened, which has the advantage of fully demonstrating the memory characteristics.

However, when constructing a logic circuit using this free channel type semiconductor integrated circuit, one or two stages of gate cell rows are required as an area necessary for wiring, and the usage efficiency of gate cells 2 with respect to chip 1 is significantly reduced. Therefore, it is not suitable for building logic circuits.

Note that the gate array type semiconductor integrated circuit described above has an RO
Some systems provide a dedicated memory area such as M, RAM, etc., but the dedicated memory area can only be used by that system, resulting in an inflexible design.

The present invention has been made in view of the above problems, and is a semiconductor integrated circuit that can increase the usage efficiency of gate cells with respect to chips when mounting memory and logic circuits, and can also fully demonstrate the characteristics of memory. The main purpose is to provide.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the semiconductor integrated circuit is constructed of a region where a gate cell row and a wiring channel are formed, and a region that covers the entire surface of the gate cell row.

[Function] According to the present invention, a semiconductor integrated circuit is divided into a region (fixed channel region) where a gate cell row and a wiring channel are formed;
Since it is configured with an area where gate cells are spread over the entire surface (free channel area), when logic circuits and memory are mounted together, it is possible to configure the logic circuit in the fixed channel area and the memory in the free channel area. Due to the effect of being able to do this, the above-mentioned objective of increasing the usage efficiency of both areas is achieved.

Further, if a memory is constructed in a free channel region in which gate cells are close to each other, the wiring length between the memories is shortened, thereby achieving the above-mentioned objective of fully exhibiting the characteristics of the memory.

Furthermore, the free channel area can be used as it is as a logic circuit, or as a memory, or can be further divided into logic circuits and memory. In comparison, design flexibility is increased, and design man-hours and manufacturing costs can be reduced.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the invention is shown in FIG. The outline is as follows.

In the figure, reference numeral 11 indicates a part of the master chip, and the portion 11 is composed of a fixed channel region 12 and a free channel region 13. In the fixed channel region] 2, a large number of gate cells 14 corresponding to basic transistor circuits such as MOS transistors or bipolar transistors 1 to transistors are arranged in an array, and wiring channels 15 are provided between the cell rows. It is being On the other hand, in the free channel region 13, gate cells 14 similar to those in 1- are spread over the entire surface.

Then, such a master chip 11 is manufactured in advance during the mask process, and according to the user's request, the wiring channels 15 in the fixed channel region 12 are formed, for example, in the wiring channel 15.
Two vertical and horizontal wiring layers are formed to interconnect the gate cells 14, and on the other hand, in the free channel region 13, wiring is freely performed on the gate cells 14 and interconnected, thereby connecting the fixed channel region 12 and the free channel region 12. Channel area 1
3 can be freely used as a logic circuit and/or memory.

Therefore, when installing a large amount of memory such as ROM, RAM, etc., as shown in FIG.
The whole may be configured as a logic circuit.

In addition, in the case where a relatively small amount of memory is installed, as shown in FIG. You can configure each as follows.

If no memory is installed, the free channel area 13 and the fixed channel area 12 may each be configured as a logic circuit, as shown in FIG. 4, and the entire master chip 11 may be configured as a logic circuit. .

In this way, the conductor integrated circuit can be adapted to systems with slightly different specifications without any design changes.

In addition, when configuring a semiconductor integrated circuit including a memory in "-", if the memory is formed on the free channel region side, the length of the wiring connecting the cells can be shortened.

Furthermore, in each of the above embodiments, the ratio of the free channel area 13 used as a logic circuit and/or memory to the fixed channel area 12 used as a logic circuit is as follows:
It can be changed as appropriate depending on the expected user specifications.

Incidentally, although not shown in the figure, around the region where the gate is formed, there is an I10 cell serving as an external interface section similar to that shown in FIG. A large number of bonding pads are arranged for electrical connection.

According to the semiconductor integrated circuit configured in this manner, the following effects can be obtained.

That is, according to the semiconductor integrated circuit described above, since the semiconductor integrated circuit is configured by the fixed channel region 12 and the free channel region 13, when a logic circuit and a memory are mounted together, the logic circuit is placed in the fixed channel region 12. On the other hand, the effect of configuring memories in the free channel area 13 makes it possible to increase the usage efficiency of the peripheral area.

In addition, the free channel region 1 adjacent to the gate cell 14
By configuring the memory in 3, the wiring length between the memories becomes short, so that the characteristics of the memory can be fully exhibited.

Furthermore, the free channel area 13 can be used as a logic circuit or as a memory.
Furthermore, ROM can be used by dividing it into logic circuits and memory.

Compared to the case where a dedicated memory area such as RAM is provided, design flexibility is increased, and design man-hours and manufacturing costs can be reduced.

Incidentally, when the number of gate cells in the semiconductor integrated circuit increases, the free channel type becomes more efficient in use, and the purpose of providing the fixed channel region 12 is lost.
The total number of gate cells in the above example is 1000.
It is desirable that the number is 0 or less.

In addition, as a result of the present inventors' study on the utilization efficiency of the number of gate cells, the most desirable number of gate cells is 5.
It was found that there were less than 000 pieces.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, if the free channel area 13 alone is insufficient, memory may also be configured in part of the fixed channel area 12.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, since the semiconductor integrated circuit is configured with a region where gate cell rows and wiring channels are formed (fixed channel region) and a region where gate cells are spread over the entire surface (free channel region), the logic circuit and memory can be In the case of mixed mounting, a logic circuit can be configured in a fixed channel area, while a memory can be configured in a free channel area. As a result, it becomes possible to increase the usage efficiency of the peripheral area.

Further, if the memory is configured in a free channel region where gate cells are close to each other, the wiring length between the memories can be shortened, so that the characteristics of the memory can be fully exhibited.

Furthermore, the free channel area can be used as it is as a logic circuit, used as a memory, or even divided into a logic circuit and memory, compared to the case where a dedicated area for memory such as ROM or RAM is provided. This will increase design flexibility.

[Brief explanation of drawings]

Fig. 1 is a top view of a semiconductor integrated circuit showing an embodiment of the present invention, Fig. 2 is a conceptual diagram of the free channel region of the above device configured as a memory, and Fig. 3 is a conceptual diagram of the free channel region of the above device configured as a memory. A conceptual diagram when configured with a logic circuit. FIG. 4 is a conceptual diagram of the case where the free channel region is constructed of logic circuits. FIG. 5 is a top view of a semiconductor integrated circuit showing the prior art. 12...Fixed channel region, 13...Free channel region, 14...Gate cell, 15...Wiring channel, Fig.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a region in which a large number of gate cells are formed, the region is composed of a region in which gate cell rows and wiring channels are formed, and a region in which gate cells are spread over the entire surface. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated circuit according to claim 1, wherein the area over which the gate cells are spread is used as a memory area. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the total number of gate cells is 5000 or less.