JPH02112222A - Mark for detecting position - Google Patents

Abstract

PURPOSE:To eliminate the influence of remnants caused by a loading effect of RIE and facilitate accurate alignment of a wafer by forming dummy patterns in the neighborhood of patterns for position detection. CONSTITUTION:An alignment mark is composed of alignment patterns (patterns for position detection) 11 and two dummy patterns 12 and 13. The alignment patterns 11 are formed by dividing a linear pattern with a certain interval. The dummy patterns 12 and 13 are composed of linear patterns. The dummy patterns 12 and 13 are provided on both the sides of the alignment patterns 11 and are in parallel with the patterns 11 with a certain distance from them. A wafer or a film to be patterned is subjected to reactive ion etching(RIE) with a resist pattern as a mask to form the protruding alignment mark.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a position detection mark used to detect the position of a wafer in lithography technology during the manufacturing process of semiconductor devices.

(Prior art) Regarding semiconductor device manufacturing, especially in the MO3LSI manufacturing process, by repeatedly using a processing technology that combines lithography technology and etching technology to copy a target device pattern on a resist, transistor parts, intermediate Through holes in the insulating layer, electrode wiring, etc. are formed. The precision of such processing techniques greatly influences the quality and yield of devices. Particularly, in the exposure process in lithography technology, the accuracy of alignment between patterns is important in forming patterns by overlapping a large number of masks.

Conventional alignment marks used for the above purpose are arranged and formed as shown in FIG.

That is, as shown in FIG. 4(a), a linear pattern 44 is arranged on the dicing line 43 between each chip 42 of the sea urchin I\41 as shown in FIG. 4(b). Patterns 44 of the same shape are arranged on each part of the wafer 4, and alignment is performed for each chip 42. Note that the alignment mark may be formed in a region other than the above-mentioned dicing line 43 where a pattern where no device pattern is formed is sparse.

By the way, in order to form alignment marks, a wafer or a film to be processed is etched using a resist pattern as a mask. In recent years, etching techniques for forming semiconductor devices have changed from wet etching to active ion etching (RIE). R.I.E.
On the dicing line or in sparse areas of the resist pattern, the etching rate changes due to excess or deficiency of the etching gas consumed due to changes in the etching area. ) occurs. For example, as shown in FIG. 5, when a resist pattern 53 is formed on a film to be processed 52 on a wafer 51 and the film to be processed 52 is selectively etched by RIE using this as a mask, the side surfaces of the film to be processed 52 that have been etched are etched. And a residue 54 is generated on the surface of the wafer 51.

As described above, alignment marks are formed in areas where dicing lines and device patterns are sparse, so residues are likely to be generated around these marks. If residual material is generated around the alignment mark, erroneous detection occurs during mark detection, and the position of the apparent upper mark (the apparent upper mark determined by the mark detection mechanism) is shifted both absolutely and relatively. In addition, there is not only residue but also dust around the alignment mark (4
If the dust is erroneously detected as a mark, the appearance of the mark will be shifted from the position of the mark above.

Such a shift not only causes a total loss of wafer shot (.) during wafer alignment, but also increases variations in wafer rotation, wafer run alignment, and orthogonality, leading to a decrease in alignment accuracy. In lithography in which a pattern is formed by overlapping a large number of masks, there is a problem in that the manufacturing yield decreases due to a decrease in the accuracy of mask/wafer alignment.

(Problem to be solved by the invention) As described above, in the conventional alignment method using position detection marks formed on a wafer, the marks are formed on the dicing line of the chip or in an area with a sparse pattern density. There is a risk that residue etc. may be generated due to the RIEO loading effect, which poses a problem that may lead to incorrect detection of mark positions. There was also the problem that dust and the like could be mistakenly detected as marks.

The present invention has been made in consideration of the above circumstances, and includes:
The objective is to provide a position detection mark that can eliminate the influence of residue caused by the loading effect of RIE and that can align a wafer with high precision.

[Configuration of the Invention (1st Step for Solving the Problems) The gist of the present invention is to form marks in a plurality of patterns in order to prevent the generation of residues caused by the loading effect of RIE.

That is, the present invention provides a position detection mark used for positioning a wafer when transferring a mask pattern onto the wafer, in which a position detection pattern is provided on the wafer, and a position detection mark is provided around the wafer. The idea is to provide a dummy pattern.

(Function) According to the present invention, by forming a dummy pattern around the position detection pattern, the resist pattern around the position detection pattern becomes denser than sparse. This reduces the etching area during the etching process (particularly RIE) and prevents the generation of residues due to loading effects. Therefore, erroneous detection during wafer alignment can be prevented, unnecessary shift amount, wafer low angle, wafer runout, variation in wafer orthogonality, etc. can be prevented, and highly accurate positioning can be achieved. Furthermore, by forming the position detection pattern and the dummy pattern into a plurality of parallel straight lines, the signal obtained by scanning the beam during mark detection will have a plurality of peaks.

Therefore, it is possible to distinguish between a signal due to dust or the like and a mark detection signal, thereby preventing false detection.11. It becomes possible to do so.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a plan view showing a position detection mark according to an embodiment of the present invention. The mark in this embodiment is formed from an alignment pattern (position detection pattern) 11 and two dummy patterns 12, 1.3. The alignment pattern 11 is a linear pattern separated at equal intervals, and the dummy patterns 12 and 13 are linear patterns. The dummy patterns 1213 are arranged parallel to the alignment pattern 11 at equal intervals, with the alignment pattern 11 in between. In addition, each pattern 11, 12
．． The width of 13 is, for example, 1 μm, and the pattern interval is, for example, 4 μm.

With this configuration, since the dummy patterns 12 and 13 are present on the left and right sides of the alignment pattern 11, it is possible to prevent the generation of residues due to the loading effect due to RIE. Therefore, it is possible to eliminate misidentification due to residue and perform stable and highly accurate alignment.

FIG. 2 is a diagram showing an apparatus configuration when performing alignment using the position detection pan shown in FIG. 1. mask 21
The pattern is projected and exposed onto a wafer 23 through a projection lens 22, whereby the pattern of the mask 21 is transferred to a resist or the like on the wafer 23. On the other hand, a light beam from a laser light source 24 is focused by an optical system 25 and irradiated onto a wafer 23 through a projection lens 22. The reflected light from the wafer 23 is received by a detector 26 via a lens 22 and an optical system 25.

Here, when the position of the laser beam coincides with [macro]0 by scanning a stage (not shown) on which the wafer 23 is placed, the intensity of the reflected light changes, and the output of the detector 26 changes. Then, based on the change in the detection signal, for example, the peak position of the detection signal and the stage coordinates are correlated and processed,
The coordinates of the signal peak position are detected as mark coordinates and alignment is performed.

FIG. 3 is a schematic diagram showing the principle of mark detection.

The beam 31 is scanned over the mark 10 as shown in FIG.
The reflected light becomes stronger, and the detection signal becomes as shown in FIG. 4(b). This detection signal is binarized at a predetermined threshold level to obtain three pulse signals as shown in FIG. 3(C). Then, the beam coordinates (or stage coordinates) for the central pulse of the three pulses are determined as mark coordinates.

In the conventional method, the mark position is determined from the detection signal corresponding to pattern 11, but in this embodiment, in addition to this, pattern 12.1' is detected (based on the rJ number, the signal is the original mark position; In other words, the tolerance of the interval T, , T2 between the central pulse (corresponding to the reflected signal from pattern 1) and the adjacent pulse (corresponding to the reflected signal from pattern 12.13) is determined in advance. A value is determined in advance, and when a pulse is detected, it is determined whether the pulse interval is within the allowable value.When the beam 31 crosses the mark 10, the above-mentioned intervals T, T2 are always within the allowable value. In the conventional method, if a pulse is detected due to dust or the like, it is mistakenly recognized as a mark, but it is highly unlikely that the three pulses mentioned above will be obtained at equal intervals in the field of dust.Therefore, in this embodiment, ,
By determining that a mark has been detected only when three pulses are generated at equal intervals, it is possible to eliminate misidentification of dust, etc., to ensure mark position detection, and to perform highly accurate positioning.

Thus, according to this embodiment, the alignment pattern 11
By providing dummy patterns 12 and 13 on the left and right sides, it is possible to prevent the generation of residue due to the loading effect due to RIE, and it is possible to perform stable high-viscosity alignment. Moreover, it is possible to eliminate erroneous recognition of mark detection due to dust or the like, and to perform reliable mark position detection. Therefore, if it is used for pattern transfer during semiconductor device manufacturing, it can contribute to improving device manufacturing yield.

Note that the present invention is not limited to the embodiments described above. For example, the shape of the position detection pattern may not be divided, but may be continuous in a straight line. Furthermore, using a diffraction grating as a position detection pattern,
It is also possible to detect the position by detecting the reflected or transmitted diffracted light by this grating. Further, the dummy pattern does not necessarily have to be a straight line, but may be formed around the position detection pattern. Furthermore, the number of dummy patterns, etc. can be changed as appropriate according to specifications. In addition, various modifications can be made without departing from the gist of the present invention.

1 ] [Effects of the Invention] As detailed above, according to the present invention, since the dummy pattern is provided around the position detection pattern, it is possible to eliminate the influence of residue caused by the loading effect of RIE, It becomes possible to align the wafer with high precision.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a position detection mark according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of an apparatus configuration when performing alignment using the above mark, and FIG. 3 is a plan view showing a position detection mark according to an embodiment of the present invention. Figure 4 is a schematic diagram to explain the principle of position detection, Figure 4 is a plan view showing conventional position detection marks and their placement parts, Figure 5 is a cross section to explain etching residue due to the loading effect of RIE. It is a diagram. DESCRIPTION OF SYMBOLS 10... Mark for position detection, 11... Alignment pattern (pattern for position detection), 12.13... Dummy pattern, 21... Mask, 22... Projection lens, 23... Wafer, 24... Laser light source, 25...
...Optical system, 26...Detector, 31...Laser beam.

Claims (3)

[Claims] (1) In the position detection mark used to align the wafer when transferring the mask pattern onto the wafer, the position detection mark formed on the wafer and the position detection mark formed around this pattern. A position detection mark comprising a dummy pattern. (2) Both the position detection pattern and the dummy pattern are linear patterns, and a plurality of the dummy patterns are arranged parallel to the position detection pattern with the position detection pattern in between. The position detection mark according to claim 1. (3) The position detection pattern and dummy pattern are
2. The position detection mark according to claim 1, wherein the mark is formed in a convex shape by reactive ion etching using a resist pattern as a mask.