JPH0464217A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the dispersion of pattern width by a micro-loading effect by arranging a dummy pattern around a pattern to be matched in the patterns of a semiconductor device. CONSTITUTION:Resists 4 are formed onto a polysilicon layer 3 by applying photolithography, the unnecessary sections of the polysilicon layer 3 are removed through etching under the state, and polysilicon resistors R1, R2 and dummy patterns D1, D2 are left. Even when pattern arrangement density in the peripheries of the polysilicon resistors R1, R2 is varied at that time, pattern arrangement density nearest to the resistors R1, R2 is equalized to the patterns D1, D2. Accordingly, micro-loading effects to each of the resistors R1, R2 are also made uniform, thus reducing the dispersion of resistance width between the resistors R1, R2, then improving matching between the resistors R1, R2.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a semiconductor device that prevents variations in pattern width due to microloading effects during etching and improves matching between patterns.

(b) Conventional technology Conventionally, for example, in order to form a polysilicon resistor on a silicon substrate, a polysilicon layer is deposited on the silicon substrate by low-pressure CVD.
A resist pattern is formed on this polysilicon layer by photolithography. In this state, reactive sputter etching (RYE)
The unnecessary portions are removed to form a polysilicon resistor pattern.

(c) Problems to be Solved by the Invention In the etching of the polysilicon layer described above, a phenomenon called a microloading effect occurs. When this microloading effect occurs, the pattern width becomes smaller where the pattern is dense, and conversely, where the pattern is sparse, the variation in pattern width increases, resulting in variation in resistance value.

This is because where the pattern is dense, there is less polysilicon removed by reactive species, resulting in excessive etching, whereas where the pattern is sparse, more polysilicon is removed by reactive species, resulting in insufficient etching. It is thought that it is because it becomes a gimmick.

For example, in a differential amplifier or the like, it is necessary to accurately match (match) two polysilicon resistors.

As shown in Part 3 of these two polysilicon resistors R+ and Rt, if one Rt has a dense pattern and the other R2 has a sparse pattern, the micro-loading effect will cause the width of the resistor R1 to increase. W1 becomes smaller than the expected value, and conversely, the width W2 of the resistor R2 becomes larger than the planned value, resulting in the problem that the resistance values vary and matching becomes impossible.

The present invention has been made in view of the above, and aims to provide a semiconductor device that prevents variations in pattern width due to the microloading effect and improves matching between patterns.

(d) Means and operation for solving the problems In order to solve the above problems, the semiconductor device of the present invention is obtained by forming a layer to be etched on a semiconductor substrate and patterning the layer to be etched by etching. The method is characterized in that a dummy pattern is arranged around a pattern that requires matching among the patterns.

In the semiconductor device of the present invention, by arranging the dummy patterns, pattern densities near the patterns to be matched can be made uniform.

Therefore, the microloading effect for each pattern can be made equal, and variations in pattern width can be suppressed.

(E) Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1(a) is a diagram illustrating the arrangement of polysilicon resistors in a semiconductor device according to this embodiment. R8 and R2 are polysilicon resistors that should be matched, and dummy patterns D, D,
It is. Take R1, , distance X+ between R2 and D2, X
All z's are made equal, and the value is taken as the minimum rule, that is, the minimum value of the distance between patterns allowed in design. Note that C indicates a contact hole for electrical connection to the polysilicon resistors R, , R2.

These polysilicon resistors R1, Rz and dummy pattern D
1. The formation of Dt will be explained with reference to FIG. Second
Figure (al is the insulating layer (S) of the silicon substrate (wafer) 1
A polysilicon layer 3 is formed on the iOz layer 2 by low pressure CVD. In addition, the silicon substrate l
Although other elements such as transistors are built in, they are omitted in FIG.

In FIG. 2(b), a resist 4 is placed on the polysilicon layer 3.
The state formed by applying photolithography is shown. Etching (RIE) is performed in this state to remove unnecessary portions of the polysilicon layer 3 and form polysilicon resistors R,,R.
2. Dummy patterns D1 and D2 are left [Fig. 2 (C
)reference〕. At this time, even if the pattern arrangement density around the polysilicon resistor R, , R is dense or dense, the polysilicon resistor R
, , R, are made equal in pattern arrangement density in the nearest vicinity due to the dummy patterns D7 and D2. Therefore, the microloading effects on each of the polysilicon resistors R,,R, are also equal, and the polysilicon resistors R,,R
, the variation in the resistance width W, , W, between , is reduced, and the matching between the polysilicon resistors R1 and Rz is improved.

FIG. 1(b) shows a polysilicon resistor R, according to a modified example.
It is a figure explaining arrangement of R2. In this case, guard ring-shaped dummy patterns G, , G2 are arranged around the polysilicon resistors R, , R,.

Each polysilicon resistor R,, R2 and dummy pattern G,,
The gaps yI and y2 with respect to G are set to equal values (y+ = yz) according to the minimum rule. Therefore, by making the pattern density around the polysilicon resistors R+ and Rz equal, it is possible to improve the matching between the resistors R, , R,.

(f) As described in detail, the semiconductor device of the present invention is characterized in that a dummy pattern is arranged around a pattern that requires matching. It has the advantage of suppressing width variations and improving matching between patterns.

[Brief explanation of drawings]

FIG. 1(a) is a diagram illustrating the arrangement of polysilicon resistors and dummy patterns in a semiconductor device according to an embodiment of the present invention, and FIG. 2(a), 2(b), and 2(C) are diagrams explaining the arrangement of patterns, and FIG. FIG. 2 is a diagram illustrating the arrangement of polysilicon resistors in a conventional semiconductor device.・R2: Polysilicon resistance, D, ・D2 ・G1 ・G2: Dummy pattern, 1:
Silicon substrate, 3: polysilicon layer. R1/R2: Polysilicon J19 (a) Patent applicant Agent: ROHM Co., Ltd.
Patent Attorney Shigeru Nakamura Shinyasa→+→Ko2y2 Diagram (a) Polysilicon resistance pile matrix diagram (C)

Claims (1)

[Claims] (1) In a semiconductor device in which a layer to be etched is formed on a semiconductor substrate and the layer to be etched is patterned by etching, a dummy pattern is arranged around a pattern that requires matching among the patterns. A semiconductor device characterized by: