JPH0210998A - Broad band circuit added with elastic memory function - Google Patents

Abstract

PURPOSE:To realize a high speed time division switch by latching a serial signal of an input highway by an individual clock for each highway after parallel conversion and applying serial conversion to an output with a multiplex parallel serial conversion section based on a master clock. CONSTITUTION:A serial signal of each highway is converted and outputted into k-bit parallel signal based on highway clocks #1-#k by parallel expansion sections 101-10k. The parallel output is latched simultaneously at a latch circuit 30 with a clock synchronized with the master clock from an internal control section 40. Thus, equal length and phase adjustment are applied. A conversion circuit 50 applies a latch output as the same input to apply time position conversion and outputs a serial signal by multiplex parallel/serial conversion.

Description

[Detailed Description of the Invention] [Summary] It is added to the front stage of serial-to-parallel conversion LSI, etc., which is essential for processing wideband signals in digital exchanges, and has a simple elastic memory function, reducing the Regarding wideband circuits that do not require a dedicated elastic memory LSI, a circuit with an elastic memory function is added to the front stage of the serial-to-parallel conversion LSI to reduce deterioration and eliminate the need for a dedicated LSI. The purpose is to realize a wideband circuit such as the following: a parallel expansion section that expands the input highway serial signal into parallel signals; A control unit that generates a clock, a latch circuit that simultaneously latches each parallel output of the parallel expansion unit, an internal control unit that generates a clock to be given to the latch circuit based on the master clock, and a control unit that uses the latch output as the same input and has a time position. It is configured to include a conversion circuit that performs conversion and serial expansion and outputs the result.

[Industrial Application Field] The present invention relates to a serial-to-parallel conversion LSI that is essential for processing wideband signals in digital exchanges.
The present invention relates to a wideband circuit that is added to the front stage of the above circuit, has a simple elastic memory function, reduces the need for equalization (phase adjustment), and eliminates the need for a dedicated elastic memory LSI.

[Prior Art] Recently, digital exchanges have been using wideband signals (150M
Broadband switching equipment for exchanging B/S) has become essential.

[Problem to be solved by the invention] However, using time-sharing exchange,
In order to replace highways of lb/s or more, signal propagation delays, which were not a problem with conventional narrowband (64 Kb/s system) switching equipment, cannot be ignored.

When processing wideband signals, serial-to-parallel conversion is performed by the time division switch section. FIG. 4 is a diagram showing the configuration of a conventional time division switch section.

The time division switch section is configured to handle multiple wideband signals (several hundred Mb/s
The above) are inputted and processed in the same manner, and are usually implemented in LSI. This time division switch section converts the serial signals of each input highway into parallel signals by means of a multiplex serial/parallel converter A1, as shown in FIG. 2(a). These parallel signals are sent to time division switch A2
After time position conversion is performed at , serial conversion is performed at a multiplex parallel-to-serial converter A3, and output to output highways (plurality).

Figure (b) is a diagram showing the configuration of the parallel expansion part, where the serial signal of each highway is in the pit shift register A.
l 11 , . . . , K-bit register A12s after being converted into parallel by A11K.

..., latched by A12K. This latch output is a set of:1 selector (selects and outputs one out of K inputs) A211. . . . is taken into the bit register A31 via A21K and output as a parallel signal. The relationship between the signals on the input side and the output side is shown in FIG. 4(C) (this is for K-4). Serial signals aO, al, a2, a3 of highway #a on the input side are ao, al, a2, a3 on the output side.
It is output as a3 parallel signal. highway#
b signals bO, b1. b2. The same applies to b3, and the same applies to other highway signals.

However, this switch section has a drawback in that the dispersion of the propagation delay of the highway increases because it processes distributed highways at once. In order to solve this problem, according to the prior art, a configuration as shown in FIG. 5 can be considered, but in FIG. However, this method has a problem in that as the number of highways increases, equalization and phase adjustment are performed at the stage before the time division switch section B2, and it is not practical. In addition, in the method shown in FIG. 6(b), phase adjustment between input and output is performed in the elastic memory C2 after equalization for each highway; in this method, the elastic memory LSr
There is a problem in that it is necessary to additionally add C2 before the time division switch section B2.

In view of these problems, an object of the present invention is to add a circuit having a practically sufficient elastic memory function to the front stage of the serial-to-parallel converter LSI, etc., which is essential for a time division switch configuration, and to improve the performance. The object of the present invention is to provide a wideband circuit with an elastic memory function that eliminates the need for a dedicated LSI.

Means for Solving the Problem] FIG. 1 is a diagram showing the principle configuration of the present invention. In the figure, 10
1. . . . 10 is a parallel expansion unit that expands the serial signal of the input highway into a parallel signal of 2 bits, and 20
1. . . . 20 is a control unit that is provided individually for each highway and generates a clock necessary for the parallel expansion unit based on the clock for each highway, and 30 is a control unit that generates the clock necessary for the parallel expansion unit based on the clock that is provided. A latch circuit that simultaneously latches the outputs; 40 is an internal control unit that generates a clock to be applied to the latch circuit 30 based on the master clock; 50 is a multiplex parallel-to-serial converter that uses the latch outputs as the same input and performs time position conversion; This is a conversion circuit that performs serial expansion and outputs it.

[Operation] In such a configuration, the serial signals of each highway are processed by the parallel expansion section 101. . . 10, the signals are expanded in parallel based on the clocks of each highway and output as parallel signals. The parallel outputs of each highway are simultaneously latched in the latch circuit 30 by a clock from the internal control section 40 (synchronized with the master clock). As a result, equal improvement 1 phase adjustment is performed. The conversion circuit 50 performs predetermined processing on the latch output and outputs it to the output highway.

In this way, the circuit of the present invention can easily realize a wideband switch circuit with an elastic memory function without using special circuits for processing such as equalization processing and phase adjustment as in the past. can.

[Embodiment] FIG. 2 is a configuration diagram of an embodiment of the present invention. In the figure,
Components equivalent to those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

In the parallel exhibition room, 111. . . . 11 includes a bit shift register for taking in the serial signal of the input highway and converting it into a bit parallel signal based on the clock from each control unit 20; 121. ...12
A first circuit latches the parallel output of each bit shift register based on the clock from each control section 20.
It is a register of bits.

In the latch circuit 30, 311. ... 31 is a second bit register that individually latches the parallel output of each first bit register, and simultaneously latches the parallel output of each first bit register based on the clock from the internal control unit 40. Latch.

This latch output is input to the conversion circuit 50.

The operation in such a configuration will be explained next with reference to the time chart of FIG. Here, the case of K-4 will be explained. K-bit shift register 111. ...
As shown in FIG. 3, the timing at which the data is taken into Ilk, expanded in parallel, and latched into the first bit registers 121° . . . 12k varies depending on the highway, as shown in FIG.

As shown in FIG. 3(l), the internal control unit 40 is set to generate the latch clock later than these timings and earlier than the latch of the next input signal. All the highway signals (parallel-converted signals) are latched at the same time in the second bit registers 311, . . . 31k, and their phases are matched. - Predetermined processing is performed in the conversion circuit 50 during a period until the 31k latches the next highway signal.

The same operation is repeated thereafter.

[Effects of the Invention] As explained above, according to the present invention, it is possible to reduce the deterioration of the highway signal (several hundred Mb/s or more) input to the high-speed time division switch section (conversion circuit), and to reduce the number of components. By reducing the number of input signals (a dedicated elastic memory LSI becomes unnecessary), it is possible to realize a high-speed time division switch without being aware of input signal propagation delays.

[Brief explanation of the drawing]

Figure 1 shows the basis of the present invention! ! ! 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a time chart for explaining the operation, FIG. 4 is a configuration diagram of a conventional time division switch section, and FIG. 5 is a diagram of a highway according to the prior art. FIG. 2 is a configuration diagram of a circuit for eliminating variations in transmission delay. In FIGS. 1 and 2, 101. ...10 is a parallel expansion section, 201, ...20 is a control section, 30 is a latch circuit, 40 is an internal control section, 50 is a conversion circuit, 111, ...11 is a bit shift register, 12
1, . . . 12 are first bit registers, 311
, . . . 31 is a second bit register. Patent applicant: Fujitsu Limited
Company representative Patent attorney Ijima
Fuji Jigai 1 person (b) Figure 5

Claims (1)

[Claims] A circuit having a time-division switch function for inputting and processing a plurality of broadband signals at the same time, the circuit comprising a parallel expansion section (101, . . .・・10k)
, a control unit (201,...20k) that is provided individually for each highway and generates the clock necessary for the parallel expansion section based on the clock for each highway; A latch circuit (30) that simultaneously latches each parallel output of the latch circuit (30), an internal control unit (40) that generates a clock to be given to the latch circuit 30 based on the master clock, and a latch circuit (40) that uses the latch output as the same input and performs time position conversion. A conversion circuit (5
0) A broadband circuit equipped with an elastic memory function.