JPH04372043A - Bus for information processing device - Google Patents

Abstract

PURPOSE:To optimize the maximum transfer rate while minimizing the limit by the switching time by making the phase of the output timing of an address signal and that of a data signal inverted against a synchronous clock. CONSTITUTION:In a cycle 1, a slave S0 ends the transaction while outputting the final data D03 to the final data effective signal LSTD. A master M1 starts the next transaction after receiving this, an address A1 is outputted in the inverted phase timing against the data D03 and a synchronous clock CLK. The master M1 outputs the address A1 in the middle of cycles 2 and 3 while taking the switching time to prevent the collision between the data D03 and the address A1 at 0.5 clock cycle. When the slave S1 specified by the address A1 outputs the read data, leading data D10 is outputted at a cycle 4 while taking the switching time at 0.5 clock cycle.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus used in information processing devices such as personal computers, workstations, and office computers.

0002

BACKGROUND OF THE INVENTION Conventionally, buses for information processing devices, which multiplex address signals and data signals, and which are clock synchronous, are known, for example, from I.E.
E, Standard for a Simple
32-bit backplane bus: Nubus (1
988) pages 21 to 62 (IEEE Sta.
ndard for a Simple 32
-Bit Backplane Bus: Nubu
s, ANSI/IEEE Std 1196-19
87 (1988) PP21-62) is known.

0003

[Problems to be Solved by the Invention] The above prior art is a clock synchronous bus that uses a three-state line as a signal line for multiplexing and outputting address signals and data signals, and the address signals and data signals are multiplexed and output with respect to a synchronous clock. output at the same phase timing. This has the effect of simplifying the bus interface circuit, but when the synchronous clock is high-speed, it is necessary to avoid collisions of signal outputs when switching outputs when address signals and data signals are output by different bus-connected devices. There is a problem in that the switching time requires at least one clock cycle, and the switching time limits the maximum transfer speed of the bus, making it impossible to optimize it.

[0004] In recent years, with the dramatic improvement in the performance of CPUs and the degree of integration of LSIs, there has been a strong demand for improved maximum transfer speeds for buses for information processing devices rather than simplification of interface circuits. An object of the present invention is to minimize the limitation caused by the switching time and to maximize transfer in a clock synchronous bus that multiplexes an address signal or a bus control information signal output at the same timing as the address signal and a data signal. The goal is to provide a speed-optimized bus.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a clock synchronous method in which an address signal or a bus control information signal output at the same timing as the address signal and a data signal are multiplexed. In the bus, the output timing of the address signal and the output timing of the data signal are set in opposite phases to the synchronous clock, so that the switching time between the address signal and the data signal can be made shorter than one clock cycle.

[0006]

[Operation] In the above-mentioned conventional technology, for example, when read transactions of N words are consecutive, at least one clock cycle is required to switch from data signal output to address signal output at the boundary between transactions, and the data signal is output from the address signal output during the transaction. Since switching to an output requires a switching time of at least one clock cycle, at least (N+3) clock cycles are required per transaction, including one clock cycle of address signal output and N clock cycles of data signal output. According to the present invention, for example, in a bus that uses a clock signal with a duty ratio of 1:1 as a synchronization clock, the switching time of the two types described above can be set to 0.5 clock cycles each, so that (
N+2) clock cycles, and the maximum transfer rate can be optimized. Note that the present invention can be applied regardless of the duty ratio of the synchronous clock.

[0007]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. 1 and 2 are timing charts showing examples of transaction timing specifications according to the prior art and the present invention, respectively, and FIG. 3 is a circuit configuration diagram showing an example of a bus interface circuit for a bus according to the present invention.

In FIGS. 1 and 2, CLK is a clock signal with a duty ratio of 1:1, which is a bus synchronization clock, and A/D is an address/digital signal on a three-state signal line where an address signal and a data signal are multiplexed and output. The data signal, AVLD, is an address valid signal that is output low only while the address signal is being output to the A/D, and LSTD is the A/D signal.
This is a final data valid signal that is output low only while the last data of the transaction at /D is being output.

FIG. 1 is a timing chart showing an example of transaction timing specifications according to the prior art, and shows an example in which read transactions with a number of words of 4 are consecutive. In FIG. 1, the address signal and the data signal are output at the same phase timing with respect to the synchronous clock CLK. In cycle 1, the slave S0 outputs the final data D03 to LSTD at the same time as outputting low, thereby ending the transaction. In response to this, master M1 starts the next transaction, but if address A1 is output in cycle 2, the address signal and data signal are output at the same phase timing with respect to the synchronous clock CLK. , master M1
If the output turn-on time of the slave S0 is shorter than the output turn-off time of the slave S0, it collides with the output of the data D03 by the slave S0. If the synchronous clock is high-speed, the master M
It is difficult to ensure that the output turn-on time of slave S0 is longer than the output turn-off time of slave S0, and this collision is unavoidable. For this reason, a switching time of one clock cycle is provided, and master M1 outputs address A1 in cycle 3. Next, the slave S1 specified by the address A1 outputs read data, but here as well, a switching time of one clock cycle is provided to avoid collision with the address A1, and the first data D10 is output in cycle 5. In cycle 8, the slave S1 outputs the final data D03 at the same time as it outputs low to LSTD, thereby completing the read transaction of 4 words. In this case, the transaction by master M1 is performed in seven clock cycles from cycle 2 to cycle 8, and if read transactions of N words are consecutive, the transfer rate will be (N+3) clock cycles per transaction. I understand.

FIG. 2 is a timing chart showing an example of transaction timing specifications according to the present invention, and similarly to FIG. 1, it shows an example where read transactions with a number of words of 4 are consecutive. In FIG. 2, the address signal and data signal are output at timings opposite in phase to the synchronization clock CLK. Cycle 1 as in Figure 1
The slave S0 then outputs the final data D03 to LSTD at the same time as outputting a low signal, thereby ending the transaction. In response to this, master M1 starts the next transaction, but in the case of FIG. 2, address A1 is data D.
03 and the synchronization clock CLK, master M1 sets the switching time to 0.5 clock cycle to avoid collision between data D03 and address A1, and outputs data in the middle between cycle 2 and cycle 3. Address A1 can be output. Also, address A1
Even when slave S1 specified by outputs read data, the switching time is set to 0 to avoid collision with address A1.
．． The first data D10 can be output in cycle 4, which is 5 clock cycles. In this case, master M1
The transaction from cycle 2 to cycle 7
It can be seen that the transfer speed is (N+2) clock cycles per transaction when read transactions of N words are consecutive.

Comparing FIG. 1 and FIG. 2, for example, N=4
In this case, according to the present invention, the transfer speed can be increased by about 16% compared to the conventional technology.

FIG. 3 is a circuit diagram showing an example of a bus interface circuit for a bus according to the present invention. In Figure 3,
301 is a clock input driver, 302 is an address/
303 is a three-state driver for address/data output; 304 is a logic inversion circuit; 3
05 is a data latch register, 306 is an address latch register, 307 and 308 are flip-flops,
309 is an OR circuit, and 310 is an address/data multiplexing selector. In addition, in FIG. 3, CLK is a synchronous clock signal of the bus, iCLK is a synchronous clock signal to a connected device, A/D is an address/data multiplexed signal of the bus, iADR is an input address signal to a connected device,
iDATA is the input data signal to the connected device, oAD
R is the output address signal from the connected device, oDATA
is the output data signal from the connected device, AoEN is the address output enable signal from the connected device, DoEN
is the data output enable signal from the connected device. In FIG. 3, the address and data signals are all n bits wide.

The bus interface circuit shown in FIG. 3 is located between the bus according to the present invention and the device connected to the bus, and receives the synchronous clock CLK to control the multiplexing of the address/data multiplexed signal A/D. It has the function of controlling input and output. The bus interface circuit may be included in the same LSI as the connected device, or may be a separate LSI. The operation of the bus interface circuit will be explained below.

The bus interface circuit receives a bus synchronous clock signal CLK with a clock input driver 301, outputs it again as a synchronous clock signal iCLK to a connected device, and at the same time uses it as a latch clock for each signal. The address/data multiplexed signal A/D input from the address/data input driver 302 is generated by both the normal phase clock from the clock input driver 301 and the opposite phase clock generated by the logic inversion circuit 304. Latched separately. The normal phase clock is used in the data latch register 305, and the latched A/D is sent to the connected device as an input data signal iDATA. The reverse phase clock is address latch register 3
The latched A/D used in 06 is sent to the connected device as an input address signal iADR. This separates the multiplexed address and data signals on the bus, and allows connected devices to receive latched inputs of the address and data signals on the bus.

The connected device also outputs an output address signal oADR to the bus interface circuit in order to output an address signal or a data signal or both to the bus.
, output data signal oDATA, address output enable signal AoEN, and data output enable signal DoE
Output N. In the bus interface circuit, the flip-flop 307 latches the data output enable signal DoEN with a normal-phase clock, and the flip-flop 308 latches the address output enable signal AoEN with a reverse-phase clock. The latched DoEN and AoEN are ORed by an OR circuit 309 and then used as an output enable signal of the address/data output three-state driver 303. Also, the latched DoE
N is used as a select signal for address/data multiplexing selector 310. The output address signal oADR and the output data signal oDATA are input as data signals to the address/data multiplexing selector 310, and are multiplexed by the latched DoEN so that only the data output enable is selected as the output data signal oDATA. , is used as a data signal for the address/data output three-state driver 303. As a result, the address signal and data signal to be output on the bus are multiplexed, and the output address signal oADR is output at a timing synchronized with a clock of opposite phase when the address output is enabled.
Furthermore, when the data output is enabled, the output data signal oDATA is output onto the bus at a timing synchronized with the normal phase clock.

As described above, the bus interface circuit shown in FIG.
Multiplexing control and input/output control can be performed.

FIG. 4 is a block diagram showing an example of a system configuration of an information processing device using a bus according to the present invention. In FIG. 4, 401 is a CPU with a multiprocessor configuration;
402 is a CPU that connects the CPU 401 to the system bus
A control circuit, 403 is a main memory, 404 is a main memory control circuit that connects the main memory 403 to the system bus, 405 is various input/output devices, 406 is an input/output device control circuit that connects the input/output device 405 to the system bus, 407 is a bus interface circuit shown in FIG. 3, 408 is a synchronous clock signal CLK and address/data multiplexed signal A/D of a system bus according to the present invention, and 409 is various control lines of the system bus.

CPU control circuit 402, main memory control circuit 4
04 and the input/output device control circuit 406 are examples of connected devices in the explanation of FIG. CPU control circuit 40
2. The main memory control circuit 404 and the input/output device control circuit 406 are connected to the system bus synchronous clock signal CLK by the bus interface circuit 407 with the configuration shown in FIG.
and an address/data multiplexed signal A/D;
It is also directly connected to various control lines 409 of the system bus. The system bus control lines 409 are similar to the bus control lines of the prior art. With the configuration shown in FIG. 4, the information processing device using the bus according to the present invention can:
A system configuration similar to that of an information processing device using a conventional bus can be adopted.

[0019]

According to the present invention, an address signal or a bus control information signal that is output at the same timing as the address signal and a data signal are multiplexed in a clock synchronous bus that is output at the same timing as the address signal or the address signal. When bus control information signals and data signals that are output at different timings are output by different bus-connected devices, the maximum transfer speed can be achieved by minimizing the limitations imposed by the switching time required to avoid signal output collisions when switching outputs. An optimized bus can be provided.

[Brief explanation of the drawing]

FIG. 1 is a timing chart showing an example of transaction timing specifications according to conventional technology;

FIG. 2 is a timing chart showing an example of transaction timing specifications according to the present invention;

FIG. 3 is a circuit diagram showing an example of a bus interface circuit of a bus according to the present invention;

FIG. 4 is a block diagram showing an example of a system configuration of an information processing device using a bus according to the present invention;

[Explanation of symbols]

301... Clock input driver, 302... Address/data input driver, 303... Three-state driver for address/data output, 304... Logic inversion circuit, 305... Data latch register, 306... Address latch register, 307 and 308 ...Flip-flop, 309...OR circuit, 310...Selector for address/data multiplexing.

Claims (4)

[Claims] 1. A system for multiplexing address signals and data signals, which is a clock synchronous type, characterized in that the output timing of the address signal and the output timing of the data signal are in opposite phase with respect to the synchronous clock. bus for information processing equipment. Claim 2: A method of multiplexing a bus control information signal outputted by the same bus-connected device as an address signal and a data signal, which is a clock synchronous type, and the output timing of the bus control information signal and the output timing of the data signal. A bus for an information processing device, wherein the bus has an opposite phase to the synchronization clock. 3. According to claim 1 or 2, a three-state line is used as the signal line for multiplexing and outputting the address signal or a bus control information signal output from the same bus-connected device as the address signal and the data signal. Bus for information processing equipment. 4. An information processing device comprising one or more buses according to claim 1, 2 or 3.