JPS5941593B2 - electronic musical instruments - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an electronic musical instrument that can generate multiple tones simultaneously;
In particular, the present invention relates to an electronic musical instrument in which the phases of the sounds of the same pitch are matched when a plurality of sounds of the same pitch are generated.

In this specification, "same note name" refers to the name of 12 notes within one octave (C, , C#, ......A#,
Judgments will be made only based on the relationship in B), and if the pitch name is the same even if the octave range is different, it will be considered the same pitch name.

For example, C2 note, Cs note, C4 note, etc. are the same note name (C). Furthermore, "matching the phases" or "synchronizing the phases" not only refers to the state in which the phases match each cycle, that is, the frequencies and phases match, but also refers to the state in which multiple frequency signals in an octave relationship are matched. It also includes a state in which the zero phase point of the lower frequency signal coincides with the zero phase of the other frequency signal. When multiple tones with the same note name are sounded simultaneously on a polyphonic electronic musical instrument, the phases of the generated tones are out of phase, causing the tones to cancel each other out, resulting in no sound being produced or Levels may drop significantly.

In order to prevent such a situation, it has been considered that when a plurality of tones with the same pitch name are generated, the phases of the musical tone signals are matched. However, the conventional method of matching the phases is to first set all of the sounds to zero phase when multiple sounds with the same note name are generated, and then advance the phase of each signal. It was hot. Therefore, if keys with the same note name are pressed one after the other (this is the case in most cases; keys with the same note name are rarely pressed at the same time), the point at which the later key is pressed is , the phase of the previously generated identical note name musical tone signal is once forced back to zero phase, regardless of its current phase. Therefore, at this time, the previously generated musical tone signal is slightly modulated. That is, since the phase of the musical tone being generated suddenly returns to zero phase from an intermediate phase, there is a possibility that a click sound may be generated. This invention was made in order to eliminate the above-mentioned drawbacks, and when matching the phases of musical tone signals with the same note name that are generated simultaneously, it is necessary to adjust the phase of the musical tone signal that is to be newly generated. It is designed to match the current phase of a musical tone signal having the same note name.

Therefore, the phase of a musical tone signal to be newly generated does not necessarily start from zero phase, but starts from the current phase of an already generated musical tone signal having the same note name. Further, since the phase of the musical tone signal that is already being generated is not forcibly returned to zero phase, the phase progression is not disturbed. The electronic musical instrument of the present invention includes a plurality of musical tone generation sequences, and the generation of one or more tones selected by pressing a key or the like is assigned to a separate musical tone generation sequence.

Each musical tone generation series is equipped with a frequency dividing circuit for generating a musical tone signal, and the pitch name frequency signal of the tone assigned to that series is sequentially divided by the frequency dividing circuit to generate the corresponding sound over multiple octaves. Obtain a divided signal of the same frequency. Of these frequency-divided signals, those in the required octave range are used as musical tone signals for the assigned tone. According to this invention, when a tone with the same pitch name is assigned to a plurality of musical tone generation series, the contents of the frequency dividing circuit of one series are converted into the frequency dividing circuit of the series to which the tone with the same pitch name is assigned. I am trying to match the content of More specifically, when a tone with the same note name is assigned to multiple musical tone generation sequences, the frequency dividing circuit of the newly assigned series is divided into the groups to which the note with the same note name has already been assigned. The contents of the frequency dividing circuit are preset, and the frequency dividing operation of the frequency dividing circuit of the newly assigned series (to which the newly pressed key is assigned) is started from the preset value. Since the same note frequency signal (high frequency) is applied to each frequency dividing circuit of the musical tone generation series (multiple) to which notes with the same note name are assigned, the frequency of each of these frequency dividing circuits is as follows. Once the contents are matched, these frequency dividing circuits operate in complete synchronization from then on, and their frequency division contents always match. Therefore, the phases of musical tone signals having the same note name generated from a plurality of musical tone generation sequences can be matched. According to the present invention, in the frequency dividing circuit of each musical tone generation series, the frequency division content output terminal and preset input terminal are connected to a common phase adjustment bus through respective read gates and write gates.

When presetting the frequency division contents of one frequency divider circuit to another frequency divider circuit, the frequency division contents of one frequency divider circuit are supplied to the phase matching bus through its own readout gate, and the frequency division contents of the other frequency divider circuit are The cycle circuit inputs the frequency-divided data supplied to the phase matching bus to the preset input terminal via its own write gate. Such a preset operation is performed only when a new note is assigned (a new key is pressed). That is, the write gate is opened only once when a new note is assigned to the series. The comparison circuit compares the pitch name of the sound that has already been assigned (currently being pronounced) and the pitch name of the newly assigned (newly pronounced) sound, and based on this comparison, a new The reading gate of the frequency dividing circuit in a series to which a note with the same note name as the note assigned to has already been assigned is opened in synchronization with the opening of the write gate. Therefore, the frequency division contents of the frequency divider circuit of the series that has already generated the sound with the same pitch name are supplied to the frequency divider circuit of the series that is about to be produced via the phase matching bus, and The frequency content is preset in the former frequency divider circuit. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

1. General description of general assignment operation In FIG. 1, a key coater 12 detects the on/off state of a key switch corresponding to each key arranged on a keyboard 11, and outputs a key code KC representing the pressed key.

The key code KC of each pressed key is a common key code bus 13.
The signals are multiplexed and supplied in a time-division manner. The transmission time width of the key code KC of one key given to the key code bus 13 is, for example, 48 μs. This one key code KC
The transmission time width is shown in Fig. 2a. The key code KC consists of keyboard codes K2, Kl representing the keyboard type, block codes B3, B2, Bl representing the octave range, and note codes N4, N3, N2, Nl representing the note names. Thus, each key on the keyboard 11 is identified. →Ij of the contents of the key code KC is shown in Table 1. In addition, as the key coater 12, for example,
An apparatus such as that described in the specification of No. 0-99152 (Japanese Unexamined Patent Publication No. 5223324) titled "V Key Coater" can be used. The key code KC of the pressed key is applied to the channel processor 14 via the key code bus 13.

The channel processor 14 converts the pressed keys into a specific number (
For example, the key code KC is assigned to one of the 16) sound generation channels, and the assignment operation is performed based on the key code KC given via the key code bus 13. In the channel processor 14, a sound generation assignment circuit section 15 mainly controls the above-mentioned assignment operation, and the result of assignment based on the control of this sound generation assignment circuit section 15 is stored in a key code storage circuit 16. The key code storage circuit 16 has a number of memory locations corresponding to the number of sound generation channels (for example, 16), and has a gate 1 on the input side.
Contains 6G. This storage location is constituted by a 16-stage shift register 16S, and the key code KC* of the key assigned to each channel is stored in a time-division manner. A detailed explanation of the pronunciation assignment circuit section 15 will not be given, but it may be referred to in Japanese Patent Application No. 47-125514 (Japanese Unexamined Patent Publication No. 49-84216) titled "Key Assigner" or in Japanese Patent Application No. 50-100878 (Unexamined Japanese Patent Application No. 52-1988). -245
No. 17) It can be constructed according to the allocation device as described in the specification of the invention entitled "Channel Processor." The assigned key codes KC'+' stored in the key code storage circuit 16 are sequentially read out in channel order in accordance with the main clock pulse O having a period of 1 μs.

Key code KC output from key code storage circuit 16
The channel relationship of 8 is shown in FIG. 2b. The numbers 1 to 16 shown in Figure 2b indicate the timing of the first channel to
Indicates that it is time for the 16th channel. As can be seen from FIGS. 2a and 2b, during the 48 μs in which one key code KC of a pressed key is supplied via the key code bus 13, the number of keys already assigned to each channel (1st channel to 16th channel) is Key code KC8 is repeatedly output three times. Of course, the key code KC* does not appear during the time of the channel to which no sound generation has been assigned yet, and the output of the key code storage circuit 16 at that time is all 0'.
The key code comparison circuit 17 compares the 48 μs wide key code KC of the pressed key with the key code KC8 assigned to each channel, and produces a match output EQ if the two match.

Comparison with the key code KC* of all channels is performed during the first 16 μs from the time the key code KC rises (
(first processing period). Sound generation assignment circuit section 15
If no matching output EQ is generated during this first processing period, it is determined that the key code KC of the pressed key given from the key coater 12 has not yet been assigned to any channel, and is assigned to an appropriate channel (for example, The sound associated with the key code KCVC is assigned to a channel to which no sound has been assigned yet (that is, a blank channel). The allocation process in the sound generation allocation circuit section 15 is performed during the next 16 μs after the first processing period (second processing period shown in FIG. 2b). In other words, the currently supplied key code K
When C is to be newly assigned to a certain channel, a set signal SET is outputted from the sound generation assignment circuit section 15 in synchronization with the time of the channel in the second processing period.
This set signal SET is used when making a new allocation.
That is, it is generated only once when a new key is pressed and the key is assigned to a certain channel. Set signal S
ET is added to the input gate 16G of the key code storage circuit 16, and reads the key code KC of the key code bus 13 into the shift register 16S. Therefore, the key code KC is stored in the shift register 16S in synchronization with the time of the assigned channel. When the set signal SET is not generated, the output KC8 of the shift register 16S is fed back to the shift register 16S via the gate 16G. still,
Second processing period signal H2 generated in synchronization with the second processing period
(see Figure 2c) and the signal S generated in synchronization with the last channel time (16th channel time) of the first processing period.
Various other timing signals are utilized in the channel processor 14, such as I6 (see FIG. 2d).

Furthermore, the sound generation assignment circuit section 15 controls the pressed keys to be assigned to specific channels for each key.

For example, the pedal keyboard sound is assigned to the first channel based on the pedal keyboard dedicated channel signal PX (see FIG. 2e). Further, the lower keyboard sound is assigned to any one of the second channel to the eighth channel based on the lower keyboard dedicated channel signal LK (see FIG. 2 f). The upper keyboard tones are assigned to the 10th to 16th channels based on the upper keyboard dedicated channel signal UK (see FIG. 2g). In addition, the 9th channel contains the automatic arpeggio dedicated channel signal ARP (2nd
Although automatic arpeggio sounds are exclusively assigned based on the standard (see Figure h), this point will not be particularly explained or illustrated.

Further, the sound generation assignment circuit 15 generates a key-on signal KO in synchronization with the channel time while the key assigned to each channel is being depressed.

This key-on signal KO and key code KC8 are supplied to the digital tone generator section 18. ．． General Description of Tone Generator The digital tone generator section 18 includes 16 tone generation sequences TG1 to TG16 corresponding to each channel, and a note clock generation section 19.

In the digital tone generator section 18 shown in FIG. 3, the note clock generating section 19 generates note clock signals Nc, Nc#, . ...NA:,NB
are generated in parallel. Each note clock signal N. -NB
is the note clock 4x20 and each musical tone generation series TG
1 to TGl6. Musical tone generation series TGl~TG
l6 is a frequency divider circuit FDl to FDl6 (FDl, FD3, F
D7 (only D7 is shown), selects the single tone note clock signal Nc-NB assigned to the channel from the note clock bus 20, and sends it to its own frequency dividing circuit F.
The selected note clock signal (any one of Nc-NB) is frequency-divided in D1 to FD16. Note clock signal N for each musical tone generation series TGl to TGl6
The assignment of c-NB is performed according to the key code KC8 output from the key code storage circuit 16.

Since this key code Kcl (is generated in a time-divisional manner corresponding to each channel (see Figure 2b), the key code KC8 of each channel is converted into a corresponding tone generation sequence TGl to T
Distribute to Gl6 respectively. A reference pulse SP is used for this distribution. For example, the reference pulse Sp is as shown in FIG.
This occurs at the last channel time (16th channel time) of the second processing period, as shown in FIG. Delay flip-flops DFFl to DFFl6 (DF
Pulses SPl to SPl corresponding to each channel time are sequentially delayed by
6 (see FIG. 2j) are generated sequentially. Therefore, during the next 16 μs of the second processing period (this is called the third processing period)
, pulses SP1 to SP16 are obtained by sequentially delaying the reference pulse SP corresponding to each channel time.

For example, a pulse SPl is generated by delaying the reference pulse SP by one bit time in correspondence with the first channel time in the third processing period, and is used in the tone generation sequence TGl corresponding to the first channel. The same goes for the following, and finally, a pulse SPl is obtained by delaying the reference pulse SP by 16 bit time corresponding to the 16th channel in the third processing period.
6 is generated, which is used in the tone generation series TG16 corresponding to the 16th channel. In addition, each series TGl to TG
The delay flip-flops DFF1 to DFF16 of l6 are connected in cascade in sequence and are each driven by 1 by the main clock pulse O. In addition, in FIG. 3, for convenience of explanation, the first
Only the musical tone generation series TG1 for the channel is shown in detail, the main parts of the musical tone generation series TG3 and TG7 for the third and seventh channels are illustrated, and the musical tone generation sequences TG2, TG4 to TG6, TG for the other channels are illustrated.
8 to TG16 are omitted from illustration, but each musical tone generation series TG
1 to TG16 have the same configuration.

The note codes N1 to N4 of the key code KC* supplied from the key code storage circuit 16 to the digital tone generator section 18 are sent to the decoder 21 (FIG. 1), where they are decoded for each note name and sent to the note select bus 22. Given.

In addition, the block code B1 included in the key code KC8
~B3 is applied to the decoder 23 (FIG. 1), decoded for each octave, and provided to the octave select bus 24. The note select data (decoded from the note codes N1 to N4 in the key code KC8) applied to the note select bus 22 in a time-divisional manner is sent to the note latch circuits NLl to NLl provided in each tone generation series TGl to TGl6. It is added to the data input terminal of NLl6 (only NLl, NL3, and NL7 are shown). The octave select data (decoded from the block codes B1 to B3 in the key code KC*) given to the octave select bus 24 in a time-divisional manner is for each tone generation series TGl to TGl.
Octave latch circuit 0L1 to 0 provided in 6
It is added to the data input terminal of L16 (0L2 to 0L16 are not shown). Latch circuit NLl of each series TGl to TGl6
~NLl6 and 0L1~0L16 strobe input terminals receive pulses SPl~SPl6 from delay flip-flops DFFl~DFFl6 corresponding to each series TGl~TGl6.
are added respectively.

Therefore, each note latch circuit NLl to NLl6 latches note select data representing the pitch name of the note assigned to the corresponding channel, and each octave latch circuit 0L1 to 0L16 latches the note select data representing the note name assigned to the corresponding channel. Octave select data representing the octave range is latched. In this way, the time-divided key code K
C* is each series TGl to TGl by octave and note
6 and converted to a static state (latched).

Note select circuits NS1 to NS16 (only NS1, NS3, and NS7 are shown) provided in each series TG1 to TG16, respectively, assign notes to the corresponding channels based on note select data latched in note latch circuits NL, to NL16. A note clock signal (one of Nc-NB) corresponding to the note name of the note selected is selected from the note clock bus 20.

The selected single note clock signal (one of NO-NB) is applied from the note select circuits NS1 to NS16 to the frequency divider circuits FD1 to FD16, where the frequency is divided into multiple stages. If the frequency dividing circuits FDl to FDl6 are composed of, for example, four stages of binary counters, the +, +, 10, and blue signals of the note clock signal (Nc-NB) are output from each output stage of the frequency dividing circuits FDl to FDl6. Sound source square wave signals TSl, TS2, TS3, and TS4 of different frequencies are output, respectively. These sound source square wave signals TS1 to TS4 are in an octave relationship, respectively. The sound source square wave signals TSl to TS4 output from each frequency dividing circuit FDl to FDl6 are applied to octave select circuits 0S1 to 0S16 (0S2 to 0S16 are not shown) provided in the corresponding series TGl to TGl6, respectively. .

The octave select circuits 0S1 to 0S16 use a sound source square wave signal (among TSL to TS4) corresponding to the octave range of the sound assigned to the channel based on the octave select data latched in the octave latch circuits 0L1 to 0L16. Select one). If there is one foot system of sounds to be generated in the musical sound generation series TGl to TGl6, the sound source square wave signals TSl to TS4
Only one is selected, but if there are multiple, husbands and wives are selected according to each foot system. The figure shows that, for example, the 8-foot system 81 and the 16-foot system 16'' sound source square wave signal are selected in the first channel (pedal keyboard dedicated channel). Octave select circuit 0S1 (0
The output of S2-0S16) is the switching circuit KYl (KY2-K
Yl6), and the opening/closing is controlled based on the key-on signal KO of the sound assigned to the channel.

Similarly, the key-on signal KO given in a time-division manner from the sound generation allocation circuit section 15 is handled based on each pulse SPl (SP2-SPl6) in the latch circuit KLl (KL2-KLl6) provided in each series TGl-TGl6. channel. ．． Explanation regarding phase matching (1) Detection of phase matching conditions For phase matching control according to the present invention, the channel processor 14 side includes a note matching detection circuit 25, a priority circuit 26, a new key memory 27, and a note matching circuit. A memory 28 is provided.

In this portion on the side of the channel processor 14, it is detected whether or not conditions for performing phase matching are satisfied.
The conditions are that 1) the new sound that is to be generated exists, and 2) the pitch name of the new sound is the same as the pitch name of the sound that has already been generated. It is. Then, in which tone generation series (channel) the new note is to be generated is temporarily stored in the new key on memory 27, and in which musical tone generation sequence (channel) the tone with the same note name that has already been generated is stored. ) is temporarily stored in the note matching memory 28. The note coincidence detection circuit 25 adds note codes N1 to N4 of the key codes KC of the pressed keys given from the key coater 12 via the key code bus 13 to one input, and outputs the note codes from the key code storage circuit 16 in a time-sharing manner. Of the assigned (currently sounding) key codes KC'+, note codes N1 to N4 are added to the other input.

Therefore, the note name of the note currently occurring in each channel (each series TGl to TGl6) is compared with the note name of the note pressed on the keyboard, and when the two match (when they are the same note name), a note is issued. A match signal NEQ is output.

The output NEQ of this note coincidence detection circuit 25 is applied to an AND circuit 29, and is selected and becomes valid only when the key code KC is supplied from the key coater 12.

In other words, note code N1 included in key code KC
~N4 are all added to the OR circuit 30, and this OR circuit 3
The AND circuit 29 becomes operable by the output "1" of 0.

This is because, as can be seen from Table 1 above, if key code KC exists, one of the bits of note codes N1 to N4 will always be "1". Therefore, key code KC
When the note code N1 to N4 are not present (all note codes N1 to N4 are O''), even if a match signal NEQ is generated, it is blocked by the AND circuit 29.The note match signal NEQ is , a key code KC* having the same note name as the 48 μs wide key code KC given from the key coater 12 is generated in synchronization with the assigned channel time.

Therefore, when sounds with the same pitch name are being generated in multiple channels, the note matching signal NEQ is generated at the time of the multiple channels.

The priority circuit 26 selects only the note match signal NEQ generated during one channel time. That is, according to the present invention, all the tones with the same pitch name that are already being generated are synchronized in phase, so it is only necessary to match the phase of the new tone to only one of them. The priority circuit 26 selects the note match signal NEQ that occurs first and blocks subsequent note match signals NEQ. Note match signal NEQ provided from AND circuit 29 is applied to AND circuit 31 within priority circuit 26.

The other input of the AND circuit 31 is the second processing period signal H2 (
(see FIG. 2c) is added, and the note match signal NEQ that occurs first in the second processing period is selected by the AND circuit 31. The output of the AND circuit 31 is applied to the note matching memory 28 via the OR circuit 32, and
The signal is applied to the delay flip-flop 34 via the . The memory of delay flip-flop 34 is self-maintained via AND circuit 35. Therefore, the delay flip-flop 3 starts from the next channel time when the first note match signal NEQ is read.
4 output valve is held, and this output ゛1゛ is connected to inverter 3.
6 and inverts the AND circuit 31 to disable it.

Therefore, only the note match signal NEQ that occurs first in the second processing period is selected, and subsequent note match signals NEQ are blocked by the AND circuit 31.

When the second processing period and further the third processing period elapse and the next first processing period begins, another key code KC is supplied from the key coater 12, so that the memory in the delay flip-flop 34 is no longer necessary. Therefore, the AND circuit 35 is disabled by the signal Sl6 (see FIG. 2d) generated at the final channel time of the first processing period, and the delay flip-flop 3
Release the self-hold of 4.

For example, assume that C3 and C2 notes have already been assigned to the third and fifth channels, respectively, and that a new key for C4 note is pressed and it is assigned to the seventh channel.

In this case, the contents of the key code KC* output from the key code storage circuit 16 are as shown in FIG. 2k. Second
At the 7th channel time of the processing period, the set signal SE
T is generated from the sound generation allocation circuit section 15, the key code KC of the C4 note is read into the key code storage circuit 16, and the key code KC'+' of the C4 note is generated in the seventh channel time of the third processing period. . Further, the note match signal NEQ is generated as shown in FIG.
Based on the EQ, the output of the delay flip-flop 34 occurs as shown in FIG. 2m.

Therefore, the note match signal NEQ caused by note C2 is blocked. Note match memory 28 and new key on memory 27 are shifted according to main clock pulse φ, which is a 16 stage-1 bit shift register.

Single note match signal NEQ selected by priority circuit 26
is read into the note matching memory 28, and the AND circuit 37
Self-maintained through . Therefore, note matching memory 2
From 8 onwards, the key code KC supplied from the key coater 12
A signal ``1'' is output in synchronization with a single channel time to which a note with the same pitch name is assigned. AND circuit 37
A signal obtained by inverting the second processing period signal H2 by an inverter 38 is added to the second processing period signal H2, and the priority circuit 2
When a signal is given from 6, the old storage in memory 28 is cleared. The output of this note coincidence memory 28 is used in the digital tone generator section 18 as a read command signal RO for frequency-divided data. In the case of the example shown in FIG. 2 km, the note match signal NEQ read into the note match memory 28 at the time of the third channel (the channel to which the C3 note has already been assigned) in the second processing period is 1
At the third channel time of the third processing period six bit times later, the signal is output from the memory 28 as shown in FIG. 2n.

New key on memory 27 has an OR circuit A set signal SET is stored via 39.

As mentioned above, the set signal SET is generated only once when a new tone (a new tone to be generated) is assigned to a certain channel. The output of the new key on memory 27 is temporarily self-held via the AND circuit 40,
The self-holding is canceled based on the second processing period signal H2 generated in the next second processing period. Therefore,
Immediately before a new sound is to be generated, the output of the new key on memory 27 becomes 1'' in the channel time to which that sound is assigned. It is used as the command signal WI.If the set signal SET is generated at the 7th channel time of the second processing period, as in the example shown in FIG. During the channel time, as shown in FIG. 2, the output (write command signal WI) of the new key on memory 27 becomes cracked.

Eventually, when the phase matching conditions are met, the write command signal WI
is generated (becomes "1"), and the read command signal RO is generated (becomes "1") at the time of the channel in which a note with the same pitch name as that note has already been generated.

2) Explanation of phase matching operation on tone generator side New key on memory 27 and note matching memory 2
The outputs of 8 are connected to each musical tone generation series TGl to TGl6 of the digital tone generator section 18 via lines 41 and 42.
, and pulses SP obtained by sequentially shifting the reference pulse SP
Series TG in which the write command signal WI and read command signal RO should be phase-aligned based on l to SPl6
1 to TGl6.

Each musical tone generation series TGl to TGl6 is provided with a phase matching signal memory PMl to PMl6 (only PMl, PM3, and PM6 are shown), and corresponds to its own channel among the signals given to lines 41 and 42 in a time-sharing manner. The signals are stored in their own phase matching signal memories PMl to PMl6. Pulse SPl corresponding to own channel time ~
SPl6 (and circuit group AGl~AG according to FIG. 2j)
16 (only AGl, AG3, and AG7 are shown) are made operational, and the signals on lines 41 and 42 are routed to each memory PMl~
They are distributed and stored in PM16 respectively.

Each of the AND circuit groups AGl to AG,6 includes two AND circuits, and includes phase matching signal memories PMl to PMl6.
has two 7-lip flops, lines 41 and 42
The write command signal WI or the read command signal RO given to the memory card 1 can be stored respectively. line 4
Phase matching signal memories PMl to PM that store signals of
The output of l6 becomes the write gate signal 1G, which is connected to line 4.
The outputs of the memories PMl to PMl6 storing the signals of 2 become the read gate signal 0G.

Frequency dividing circuits FDl to F for each musical tone generation series TGl to TGl6
Dl6 has a structure that can be preset, and write gates WGl to WGl6 are provided at the preset end 1, respectively.

In addition, the output terminal Q has readout gates RGl to RGl6.
(Only RGl, RG3, and RG7 are shown) are provided respectively.

Write gate WG for each musical tone generation series TGl to TGl6
1 to WGl6 (only WGl, WG3, and WG7 are shown) and read gates RG and to RGl6 are commonly connected by a phase matching bus 43 for each same weight value. For example, since the frequency dividing circuits FDl to FDl6 have four stages, the phase matching bus 43 is provided with four common lines corresponding to the four weight values of the frequency divided data. This phase matching bus 4
Frequency-divided data is transmitted and received via 3. The readout gate (R
One of Gl to Rl6) is opened, and the frequency division data TS of the frequency dividing circuit of that series (one of FDl to FDl6) is opened.
l to TS4 are read out to the phase matching bus 43.

A write gate (one of WGl to WGl6) is opened for a single musical tone generation sequence (one of TGl to TGl6) corresponding to the channel in which the write command signal WI is generated, and the tone is read out to the phase matching bus 43. The frequency division data that is
). An example will be explained in which a read command signal RO and a write command signal WI are generated as shown in FIG. 2 N and O.

First, when a pulse SP3 is generated in the musical tone generation series TG3 in synchronization with the third channel time of the third processing period, the read command signal RO supplied to the line 42 at the third channel time is transmitted via the AND circuit group AG3. and stored in the phase matching signal memory PM3.

Therefore, the phase matching memory P of this musical tone generation series TG3
The read gate signal 0G output from M3 becomes 31''.

When the read gate signal 0G becomes 11'', the read gate RG3 of the series TG3 is opened, and the frequency divisions TS1 to TS4 of the frequency dividing circuit FD3 are transferred to the phase matching bus 43.
supplied to

At this time, other series TGl, TG2, TG4 to TGl6
Since the read command signal RO is not distributed to these series of phase matching memories PMl, PM2, PM4 to
The outputs 0G of PMl6 are all ``0'', and the readout gates RGl, RG2, RG4 to RG, , 6 are closed. Therefore, only the frequency-divided data of the single frequency divider circuit FD3 is sent to the phase adjustment bus 43. On the other hand, when the pulse SP7 is generated in the tone generation sequence TG7 in the seventh channel time of the third processing period, the write command signal WI (second
(see FIG. 0) is stored in the phase matching signal memory PM7 via the AND circuit group AG7.

Therefore, the phase matching memory PM of this musical tone generation series TG7
The write gate signal G capi 1' output from the frequency dividing circuit FD7 becomes open, and the write gate WG7 of the frequency dividing circuit FD7 is opened.

At this time, since the write command signal WI is not distributed to the other series TG1 to TG5 and TG8 to TG16, the write gates WG1 to WG6 and WG8 to WG16 are closed. Therefore, the output terminal Q of the frequency dividing circuit FD3 of the tone generation series TG3 and the tone generation series TG are connected via the read gate RG3, the phase matching bus 43, and the write gate WG7.
The preset input terminal 1 of the frequency divider circuit FD7 of 7 is connected,
Frequency division circuit FD3Q frequency division data is preset in frequency division circuit FD7.

Musical sound generation series TG3 corresponds to the third channel,
A musical tone of C3 tone is already being generated. Also, musical sound generation series T
G7 corresponds to the seventh channel, from which the newly assigned C4 tone will be generated. Therefore, the content of the frequency divider circuit FD7 of the series TG7 which should generate a new sound is the same as that of the frequency divider circuit FD7 of the series TG3 which is already generating a sound with the same note name.
Matches the contents of 3. Then, the frequency dividing circuit FD7 starts frequency dividing operation from the preset value. Since notes with the same note name are assigned to both series TG3 and TG7, the note select circuits NS3 and NS7 output exactly the same note clock signal N. is supplied to both frequency divider circuits FD3 and FD7.

Therefore, while sound is being generated, the frequency division contents TS1 to TS4 of both frequency dividing circuits FD3 and FD7 are reliably matched. Therefore, the phases of sounds C3 and C4 generated from both series TG3 and TG7 are synchronized. In the example of FIG. 2k, C2 tone is being generated in the fifth channel (musical tone generation series TG5), but
The phases of the three tones C2, C3, and C4 are synchronized because the same phase matching as described above has already been completed between the C2 tone and the C2 tone. still,
Phase matching signal memory PMl for each series TGl to TGl6
The memory of ~PMl6 is designed to be reset by the reference pulse SP (see FIG. 2, 1).

Therefore, the transmission/reception (presetting) of frequency division data via the phase matching bus 43 is only performed temporarily at the beginning of a new sound. In the above embodiment, the pulses SP1 to SP16 are sequentially generated in the third processing period, and during this period, the distribution and phase of the key code KC'+' (note select data, octave select data) for each tone generation series TG1 to TG16 is determined. Frequency-divided data is sent and received via the matching bus 43.

However, since the first processing period and the second processing period can also be used in the digital tone generator section 18, the note select bus 22, octave select bus 24, and phase matching bus 43 are all made common, and note select data and octave select It is also possible to transmit the data and the frequency-divided data for phase adjustment in a time-division manner. Further, in the above embodiment, the phase matching bus 4
3, lines corresponding to the number of stages (number of frequency division data) of each frequency dividing circuit FDl to FDl6 (four lines in Fig. 3) were used, but only one line was used as a phase matching bus. Good too.

For example, in a channel in which frequency-divided data is read out to a phase matching bus, each frequency-divided data is converted into parallel one-page columns and transmitted to one line (phase matching bus) in a time-sharing manner.
In the channel in which this frequency division data is written (preset), the serial frequency division data given from a phase matching bus consisting of one line may be converted from serial to parallel, and then preset to the frequency division circuit. In addition, in the above embodiment, the content of the frequency dividing circuit of a series to which a note with the same pitch name has already been assigned is preset for the frequency dividing circuit of the newly assigned series, and When starting the frequency dividing operation of the frequency dividing circuit of the series (to which the pressed key is assigned) from its preset value, the above-mentioned preset operation is performed immediately when a new note is assigned.

However, the present invention is not limited to this, and the system waits until the contents of the frequency divider circuits of the series to which sounds of the same note name that are already being produced are all "0", and when they become all "0", the new assignments are made. The contents of the frequency divider circuits of the selected series may be preset (in short, cleared or reset) to all "O" values, and the frequency division operation may be started from that value (0).
In this case, instead of using the preset method via the phase matching bus, the moment when the contents of the frequency divider circuits of the series to which the notes of the same note name that are already being produced become all 10'' is detected. Based on this detection, the frequency divider circuit of the newly assigned series is cleared (or reset).
You may also do so. As explained above, according to the present invention, when multiple tones with the same note name are generated, the phases of these musical tone signals can be matched, and moreover, the phases of the tones that have already been generated can be left unchanged and the phases of the tones can be adjusted later. Since the phase of the generated sound is matched to the phase of the already generated sound with the same pitch name, the phase can be matched very naturally without disturbing the sound being generated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the electronic musical instrument according to the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a detailed diagram of the digital tone generator section of FIG. 1. In the block diagram showing an example, only the tone generation sequence TG1 corresponding to the first channel is shown in detail, and the other sequences TG2 to TG16 are shown with some or all of them omitted. 14... Channel processor, 18...
...Digital tone generator section, 25...
Note match detection circuit, 26...Priority circuit, 27
...New Key on Memory, 28...
Note matching memory, TGl to TGl6...musical tone generation series, FDl to FDl6...frequency dividing circuit, P
Ml to PMl6... Phase matching signal memory, R
Gl~RGl6... Read gate, WGl~
WGl6...Write gate.

Claims (1)

[Claims] 1. A musical tone generating device that can separately allocate a plurality of musical tone signals to a specific number of musical tone generation sequences and generate these musical tone signals simultaneously, and in which the phase of a newly generated musical tone signal is determined by the phase of the already generated musical tone signal. In an electronic musical instrument equipped with a musical tone generator configured to generate each musical tone signal in accordance with the phase of the musical tone signal, the musical tone generator divides the pitch name frequency signal of the tone assigned to itself to generate an octave relationship. a plurality of musical tone generation sequences, each having a frequency division circuit that obtains a plurality of frequency-divided signals, and a newly assigned musical tone generation sequence when a note with the same note name is assigned to a plurality of said musical tone generation sequences. Preset the contents of the frequency divider circuit of the musical tone generation series to which the same note name has already been assigned to the frequency divider circuit, and start the frequency division operation in the frequency divider circuit of the newly assigned musical tone generation series from the preset value. An electronic musical instrument comprising phase synchronization means.