JPH02108338U - - Google Patents

Info

Publication number
JPH02108338U
JPH02108338U JP1989016584U JP1658489U JPH02108338U JP H02108338 U JPH02108338 U JP H02108338U JP 1989016584 U JP1989016584 U JP 1989016584U JP 1658489 U JP1658489 U JP 1658489U JP H02108338 U JPH02108338 U JP H02108338U
Authority
JP
Japan
Prior art keywords
chip component
wiring pattern
wiring board
substrate
information card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989016584U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989016584U priority Critical patent/JPH02108338U/ja
Publication of JPH02108338U publication Critical patent/JPH02108338U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Credit Cards Or The Like (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP1989016584U 1989-02-15 1989-02-15 Pending JPH02108338U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989016584U JPH02108338U (enExample) 1989-02-15 1989-02-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989016584U JPH02108338U (enExample) 1989-02-15 1989-02-15

Publications (1)

Publication Number Publication Date
JPH02108338U true JPH02108338U (enExample) 1990-08-29

Family

ID=31229647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989016584U Pending JPH02108338U (enExample) 1989-02-15 1989-02-15

Country Status (1)

Country Link
JP (1) JPH02108338U (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022529522A (ja) * 2019-04-22 2022-06-22 エイヴェリー デニソン リテール インフォメーション サービシズ リミテッド ライアビリティ カンパニー Ｒｆｉｄ装置用自己接着性ストラップ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022529522A (ja) * 2019-04-22 2022-06-22 エイヴェリー デニソン リテール インフォメーション サービシズ リミテッド ライアビリティ カンパニー Ｒｆｉｄ装置用自己接着性ストラップ

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