JPH0210830A - Etching method - Google Patents

Abstract

PURPOSE:To form a fine trench by controlling the ratio of depth to the diameter of the opening of a mask shaped onto a silicon semiconductor layer, depositing a reaction product generated at the time of etching only at the central section of a silicon semiconductor exposed surface in the opening section and conducting anisotropic etching. CONSTITUTION:Masks 2a, 2b, 2c, 2d (thermal oxide film masks) in film thickness of 0.5mum, 0.7mum, 1.0mum and 2.0mum are formed respectively onto silicon substrates shaping silicon semiconductor layers 1 in an opening diameter l=1.0mum, and the etching of the peripheral sections of mask opening sections 3 is advanced with the increase of the ratios of depth W to the mask opening sections (l), aspect ratios, through etching by using the mixed gas (Cl2+N2) of chlorine and nitrogen. SixNy as a reaction product 6 in the etching gas system is deposited in thin thickness in the periphery of the opening section and in thick thickness in the vicinity of a center in the phenomenon. Accordingly, the etching only of the peripheral region of the opening region in which the reaction product 6 is hardly deposited progresses, and a fine trench 5 through peripheral etching is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a process for etching a silicon semiconductor, and a method for etching a silicon semiconductor. The present invention particularly relates to an etching method in which a mask is formed on a silicon semiconductor layer and the silicon semiconductor is etched using the mask.
This can be used in the field of manufacturing semiconductor devices.

[Summary of the invention]

The present invention forms a mask on a silicon semiconductor layer, and when etching the silicon semiconductor layer using the mask, controls the ratio of the depth to the opening diameter of the mask to remove reaction products generated during etching from the opening. By depositing only in the center of the silicon semiconductor exposed surface in the area and anisotropically etching the silicon semiconductor layer near the opening, the silicon semiconductor layer is subject to limitations on miniaturization determined by the resolution associated with the use of a lithography process. This makes it possible to form fine grooves and the like by etching.

[Conventional technology]

Many techniques are known in which a mask is formed on a silicon semiconductor layer and the silicon semiconductor is etched using the mask. For example, a so-called trench isolation technique is known in which deep trenches are formed in single-crystal silicon or the like and applied to device isolation. It can be said that such trench isolation technology has become an indispensable technology as semiconductor devices become smaller.

In the above-mentioned trench isolation technology, a common conventional method is to form isolation grooves in a silicon substrate by a lithography process and then a reactive ion etching method.

[Problem that the invention seeks to solve]

However, when a groove is formed using a lithography process according to the conventional technique described above, the isolation width determined by the groove width is inevitably determined by the resolution of the lithography. For this reason, in order to form finer isolation regions, as will be required in future ULSI manufacturing processes, for example, if miniaturization is limited by the resolution of the lithography process, further finer isolation regions will be required. It is inconvenient for us to be unable to meet the demands of the government.

Due to the above-mentioned circumstances, there is a strong need for a process that can form fine isolation grooves that are not controlled by lithography resolution. It is also desired that the process be capable of forming fine grooves in a self-aligned manner (that is, in a self-aligned manner).

A typical technique that has been proposed under such circumstances is the peripheral etching method. However, the conventional peripheral etching method has the problem that the process is complicated, such as the need to deposit metal silicide for a mask, and a simpler method is required.・Refer to 28th Symposium on Integrated Circuit Technology J (1984), pp. 42-47, "Ultra-fine groove formation and device isolation technology by peripheral etching method").

The present invention was made in view of the above-mentioned problems, and it is possible to form fine grooves on a silicon semiconductor, and in this case, the fine grooves can be formed without being limited by the resolution of the lithography process. The purpose of this invention is to provide an etching method that can achieve this.

[Means and effects for solving the problem] In order to solve the above-mentioned conventional problems, the etching method of the present invention controls the ratio of the depth to the opening diameter of the mask formed on the silicon semiconductor layer, and performs etching. A method is adopted in which reaction products generated during etching are deposited only at the center of the silicon semiconductor exposed surface in the opening, and the silicon semiconductor layer near the periphery of the opening is anisotropically etched.

The configuration of the present invention will be schematically explained with reference to FIG. 1 as follows.

That is, as illustrated in the diagram (d) in FIG. 1, the etching method of the present invention is based on the etching method of the present invention, in which the depth W of the mask 2d formed on the silicon semiconductor layer 1 is determined based on the opening diameter l of the opening 3. By controlling the ratio to obtain the desired optimal final shape, the reaction products generated during etching are deposited only in the center of the exposed surface of the silicon semiconductor 1, as indicated by reference numeral 4 in the figure.
The silicon semiconductor layer in the vicinity of the opening 3 is etched to obtain a groove shape shown by reference numeral 5.

The present invention has been made based on the findings of the present inventor, which will be explained below.

That is, the present inventor has shown (a), respectively, in FIG.
As shown in (b), (c), and (d), film thicknesses of 0.5μ and 0.5μ, respectively, are formed on the silicon substrate forming the silicon semiconductor layer 1.
Masks 2a of 7μ, 160μ, and 2.0μ.

2b, 2c, and 2d (here, specifically, thermal oxide film masks) are formed with an opening diameter of #=1.0μ, and the diagram is clear, so
The depth of the mask and the scale of the aperture diameter are different from the actual one), and the etching conditions are set as appropriate.Here, a mixed gas of chlorine and nitrogen (C1t+Nz) is used as the etching gas, and the pressure is IQmT.

Etching was performed under conditions of Vcb=-200 volts. As a result, different etching shapes were obtained for each mask thickness, as shown in FIGS. 1(a) to 1(d).

As can be understood from the comparisons in (a) to (d) of FIG. 1, as the ratio of the depth W to the mask opening β, the so-called aspect ratio, increases, the etching around the mask opening 3 increases. It can be seen that so-called peripheral etching is occurring.

This phenomenon occurs because Sr x Ny, which is a reaction product 6 in this etching gas system, is deposited at the bottom of the opening 3 in a shape with a thick bulge in the center, as schematically shown in FIG. 2, and this serves as a mask. This is thought to have occurred due to the progress of etching.

That is, in this case, as the aspect ratio of the opening 3 increases, the reaction product 6 becomes thinner around the opening and thicker near the center due to the difference in the angle of view seen from the bottom of the opening, as shown in FIG. accumulate. Therefore, etching progresses only in the region around the opening where less reaction product 6 is deposited, and fine grooves are formed by peripheral etching (in FIG. 2, 2 is a mask).

As explained above, the present invention performs peripheral etching by utilizing the competitive reaction between deposition of products by etching gas and etching. That is, unlike conventional peripheral etching, the present invention uses a material that becomes an etching mask. By using the deposition of reaction products during etching as a mask for peripheral etching, there is no need for a process of coating the silicon substrate on the silicon substrate.
This makes it possible to form grooves in a silicon substrate that are finer than the resolution of lithography.

Furthermore, according to the present invention, as explained with reference to FIG. 1, by controlling the opening diameter l and depth W of the mask opening, it is possible to form a groove with a self-aligned line.

In the present invention, the narrower the opening diameter, the larger the aspect ratio of the mask, and the difference in the angle of view of the deposit (reaction product 6) seen from the bottom. It can be said that it is particularly effective when For example, high-speed E
The present invention can be effectively applied to devices such as bipolar devices such as CL, in which the emitter width is narrowed to increase the speed of the device.

〔Example〕

Next, as an example of the present invention, an application example in which the present invention is applied to the formation of a bipolar device will be described.

However, it goes without saying that the present invention is not limited to the illustrated embodiments.

Shown in cross-section in FIG. 3 is a bipolar device, such as a high-speed ECL. In FIG. 3, reference numeral 71 is a collector electrode, 72 is an emitter electrode, and 73 is a base electrode. 74
is the n'' region of the emitter region. 75 is the n'' region 4
There is a region p that approaches . 81 and 82 are polysilicon layers.

83 and 84 are insulators.

In bipolar devices such as high-speed ECLs, the emitter width is narrowed to increase the speed of the device.
At this time, as shown in FIG. 3, in order to increase the degree of integration, the base region is contacted with polysilicon 81, and the diffusion layer in this portion has a considerably high concentration. For this reason, carrier injection from the emitter to the base, which has not been observed in the past, occurs in the lateral direction, resulting in so-called side injection, which slows down the speed of the device.
(ection) effect comes out. That is, as schematically shown in FIG. 4(a), carriers are injected from the n+ region 74 of the emitter region toward the base as indicated by arrow I. To prevent this, an insulator region 9 as shown in FIG.
All you have to do is make it happen in that direction. In the example of FIG. 3, as shown in the figure, such an insulator region 9 has a width of 0.
．． The etching method of the present invention is applied to the formation of the insulator region 9, which is formed by providing an isolation region of about 1 μm.

If an attempt was made to form such an insulator region 9 with a width of about 0.1 μm using a conventional process, as shown in FIG. 2” photoresist mask between
Of course, this poses the problem of an additional process, but it was basically impossible to form such a mask due to lithography alignment and resolution. . On the other hand, if the present invention is used, the sixth
As shown in the figure, it is possible to form a shallow groove for forming an insulation region with self-line at the end of the emitter region (n'' region 74) of about 0.5 to 0.6 μm. The insulator region 9 can be formed, and therefore, it is possible to form an element having the insulator region 9 as shown in FIG. It can contribute to improving your time.

Fine grooves can be formed in a silicon substrate without the need for a lithography process. For example, by selectively processing only the target fine opening and its periphery, for example, fine grooves for isolation can be formed. This shows that it is possible to create.

[Brief explanation of the drawing]

FIG. 1 is a detailed explanatory diagram of the present invention, and FIG. 2 is an explanatory diagram of its operation. FIG. Figures (a) and (b) are diagrams for explaining the operation of this embodiment, and Figures 5 and 6 are diagrams for explaining the comparison between the conventional process and the process of the present invention. 1... Silicon semiconductor layer, 2 , 2a to 2d...mask, 3... opening, 4... central part of semiconductor layer exposed surface (
Deposition part), 5... Groove. l...Mask opening diameter, W...Mask opening depth. [Effects of the Invention] As described above, according to the etching method of the present invention, Fig. 2' PR7 and 7 Mikage (Tame J Matashina Go) Fig. 5 nrcSB moon map (Original 68)' Figure 6

Claims (1)

[Claims] 1. In an etching method in which a mask is formed on a silicon semiconductor layer and the silicon semiconductor layer is etched using the mask, the ratio of the depth to the opening diameter of the mask formed on the silicon semiconductor layer. is controlled so that reaction products generated during etching are deposited only at the center of the exposed surface of the silicon semiconductor layer in the opening, and the silicon semiconductor layer near the periphery of the opening is anisotropically etched. Etching method.