JPH02107095U - - Google Patents
Info
- Publication number
- JPH02107095U JPH02107095U JP1499889U JP1499889U JPH02107095U JP H02107095 U JPH02107095 U JP H02107095U JP 1499889 U JP1499889 U JP 1499889U JP 1499889 U JP1499889 U JP 1499889U JP H02107095 U JPH02107095 U JP H02107095U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- sleep
- sound
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006870 function Effects 0.000 claims description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 230000004622 sleep time Effects 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims 2
- 230000004044 response Effects 0.000 claims 1
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
Description
図面は本考案の一実施例に係るスリープ機能付
時計の回路構成を示す図である。
２……時計回路、１６……目安スイツチ、１８
……アラームセツトスイツチ、２０……スリープ
カウンタ、２６……音記憶回路、２８……ゲート
回路、３６……音量調整回路、３８……発音回路
、４０……睡眠時間カウンタ、４８……トリガ信
号発生回路、６０……切換信号発生回路、６６…
…切換ゲート回路。
The drawing is a diagram showing a circuit configuration of a watch with a sleep function according to an embodiment of the present invention. 2... Clock circuit, 16... Reference switch, 18
... Alarm set switch, 20 ... Sleep counter, 26 ... Sound memory circuit, 28 ... Gate circuit, 36 ... Volume adjustment circuit, 38 ... Sound generation circuit, 40 ... Sleep time counter, 48 ... Trigger signal Generation circuit, 60...Switching signal generation circuit, 66...
...Switching gate circuit.
Claims (1)
刻になつたことを検知してオンする目安スイツチ
と、 外部操作によりオンオフ制御され、オン操作さ
れているときにのみ前記目安スイツチのオン信号
を有効とするアラームセツトスイツチと、 前記アラームセツトスイツチがオン状態の時に
のみ前記時計回路からの一定周期信号をカウント
して一定時間後に出力信号を発生するスリープカ
ウンタと、 アラーム用とスリープ用の音をそれぞれ記憶し
前記目安スイツチがオンされている時にはアラー
ム用の音を選択する音記憶回路と、 前記アラームセツトスイツチと目安スイツチが
共にオンの時あるいは前記アラームセツトスイツ
チがオンでかつ前記スリープカウンタがカウント
中のときにのみ前記音記憶回路を動作可能とする
ゲート回路と、 この音記憶回路からの音信号に基づいて発音す
る発音回路と、 からなるスリープ機能付時計において、 前記アラームセツトスイツチのオン状態のとき
にのみ前記時計回路からの一定周期信号のカウン
トを行い、そのカウント値が一定値以上になつた
時に出力信号を発生する睡眠時間カウンタと、 前記目安スイツチのオン信号に基づいてトリガ
信号を出力するトリガ信号発生回路と、 前記睡眠時間カウンタからの出力信号発生時に
このトリガ信号の発生に応答して切換信号を発生
するとともにスリープ機能の動作終了時にこの切
換信号の発生を停止する切換信号発生回路と、 前記スリープカウンタの最終段出力と途中段出
力とを入力し、前記切換信号発生回路からの切換
信号入力時には途中段出力を、切換信号非入力時
には最終段出力を前記ゲート回路に供給して前記
音記憶回路の動作を停止させる切換ゲート回路と
、 を設けたスリープ機能付時計。[Scope of claim for utility model registration] A clock circuit that displays the time, a reference switch that turns on when it detects that the time displayed by the clock circuit has reached a preset time, and a switch that is turned on and off by external operation, an alarm set switch that makes the ON signal of the reference switch valid only when it is turned on; and an alarm set switch that counts a constant periodic signal from the clock circuit and outputs a signal after a certain period of time only when the alarm set switch is in the ON state. a sleep counter that generates a sleep counter; a sound memory circuit that stores sounds for alarm and sleep respectively and selects a sound for the alarm when the indicator switch is on; a gate circuit that enables the sound memory circuit to operate only when the alarm set switch is on or when the sleep counter is counting; and a sound generation circuit that produces sound based on the sound signal from the sound memory circuit; A clock with a sleep function, which counts constant periodic signals from the clock circuit only when the alarm set switch is on, and generates an output signal when the count value exceeds a certain value. a counter; a trigger signal generation circuit that outputs a trigger signal based on the ON signal of the reference switch; and a sleep function that generates a switching signal in response to the trigger signal when an output signal from the sleep time counter is generated; a switching signal generation circuit that stops generating the switching signal when the operation of the sleep counter is completed; a final stage output and an intermediate stage output of the sleep counter; A timepiece with a sleep function, comprising: a switching gate circuit that supplies a final stage output to the gate circuit to stop the operation of the sound storage circuit when a switching signal is not input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1499889U JPH0527033Y2 (en) | 1989-02-10 | 1989-02-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1499889U JPH0527033Y2 (en) | 1989-02-10 | 1989-02-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02107095U true JPH02107095U (en) | 1990-08-24 |
| JPH0527033Y2 JPH0527033Y2 (en) | 1993-07-08 |
Family
ID=31226669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1499889U Expired - Lifetime JPH0527033Y2 (en) | 1989-02-10 | 1989-02-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0527033Y2 (en) |
-
1989
- 1989-02-10 JP JP1499889U patent/JPH0527033Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0527033Y2 (en) | 1993-07-08 |
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