JPH02105228A - Microprocessor operation confirming system - Google Patents

Abstract

PURPOSE:To surely detect the operation abnormality of a microprocessor by outputting a signal representing abnormality when the microprocessor makes access to a program ROM area and also, outputs the readout signal of a RAM. CONSTITUTION:A program area detection circuit 13 judges whether an address outputted from the microprocessor 1 makes access to, for example, the area of a program ROM 11 or the area other than that. In such a case, since access only to the area of the ROM 11 is performed when the processor 1 performs an ordinary operation, and also, a control signal is a program data readout signal PSN, a case where the control signal is the readout signal RD of RAM data is detected as the operation abnormality of the processor 1. In other words, the circuit 13 outputs 0 when the access to the area of the ROM 11 is performed, and the output of a NOR gate 14 goes to a level 1 when the signal RD is set at a level 0, then, the abnormality of the processor 1 is outputted. In such a manner, it is possible to surely detect the operation abnormality of the processor 1.

Description

[Detailed Description of the Invention] [Summary] Regarding a microprocessor operation confirmation method related to microprocessor operation confirmation, the microprocessor reads program data from a program ROM, with the aim of reliably detecting abnormalities in the microprocessor operation. Sometimes, a program area detection circuit is provided that receives an address output from a microprocessor and detects that an area other than the program has been accessed, and the output of the program area detection circuit and the microprocessor read data from the RAM. The NOR output with the read signal is configured to be used as an abnormality notification signal for the microprocessor.

[Industrial Field of Application] The present invention relates to a microprocessor operation check method for checking the operation of a microprocessor, and more particularly to checking the operation of a microprocessor when reading a program from a ROM in which the operation program is stored.

[Prior Art] Conventionally, abnormal operation of a microprocessor is detected by using a configuration in which a program periodically sends pulses to a pulse monitoring circuit of external hardware, and when pulses no longer come to the external pulse monitoring circuit, an abnormality is detected. The company determined that this was the case, and adopted a method of notifying the company of the problem.

FIG. 4 is a diagram showing an example of a conventional circuit. In the figure, a microprocessor 1 sends a predetermined address to an address selection circuit 2, and the address selection circuit 2 sets its output to "0" if the address is in a predetermined area.

FIG. 5 is a diagram showing the allocation of address space used in the microprocessor 1. A is a ROM area, B is a RAM area, and C is a register allocation area used here. That is, when the microprocessor 1 is operating normally, the address periodically sent for testing outputs an address corresponding to area C in the figure.

The address selection circuit 2 outputs "0°" only when an address within the area C arrives. A NOR between the address selection circuit 2 and the write signal (write signal) WR is taken at the subsequent gate 3, and the register The NOR gate 3 outputs a signal that becomes "1" only when both inputs are "0".On the other hand, data is also output from the microprocessor 1 to the register 4, and the register 4 outputs a signal that becomes "1" only when both inputs are "0". The "1" level of data is latched by the output of the NOR gate 3 and "1" data is output. When the pulse monitoring circuit 5 receives this "1" level signal, it determines that the operation of the microprocessor 1 is normal. Abnormality In this case, the determination can be made based on the fact that the 1° level signal does not come from the register 4.

[Problem to be solved by the invention] In the conventional system as described above, the microprocessor 1
There is a problem in that if the abnormality is due to runaway, it is difficult to determine whether it is normal or abnormal. In other words, the microprocessor 1 goes out of control and happens to be in the area C in Figure 5.
If the address and data corresponding to , are output, the circuit of FIG. 4 is judged to be apparently normal. In other words, as a result of a "1" level signal being input to the pulse monitoring circuit 5, the pulse monitoring circuit 5 is determined to be normal.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a microprocessor operation confirmation method that can reliably detect malfunctions in the microprocessor.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals. In the figure, 11
1 is a program ROM in which a program for operating the microprocessor 1 is stored; 12 is a RAM in which data can be written and read; 14 is a RAM data read signal (read signal) RD output from the program area detection circuit 13 and the microprocessor 1;
It is the Noah Gate that receives this.

Here, it is assumed that the RD multiplied signal is at the "0" level as shown in the figure. In the figure, PSN is the program RO
This is a read signal for reading program data from the MII.

[Effect]

The program area detection circuit 13 determines whether the address output from the microprocessor 1 is for accessing ROMII, such as area A in FIG. 5, or for accessing another area. . When microprocessor 1 is operating normally, area A
(See FIG. 5), and the control signal is supposed to be the PSN signal. In other words, the program ROMI
For I, only program data can be read. In view of the above points, the present invention detects the case where the microprocessor 1 is accessing the area A and the control signal is the RAM data read signal (read signal) RD as an abnormal operation of the microprocessor 1. It is.

When accessing area A, the program area detection circuit 13 outputs "0". On the other hand, when the RAM data read signal RD of the microprocessor 1 is at the .theta. level, the output of the NOR gate 14 is at the "1" level. Therefore, in this case, the NOR gate 14 outputs a "1" level signal (microprocessor abnormality) as shown in the figure.

Furthermore, when the microprocessor 1 is accessing areas other than area A, the output of the program area detection circuit 13 is at the "1" level, so the output of the NOAGET 14 is always "1" level.
0" and is not considered abnormal. If the microprocessor 1 stops operating, the output of the NOR gate 14 remains fixed at the "1" level or "0 level", so an abnormality in the microprocessor 1 is detected. You can also.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 2 shows the program area detection circuit 13 (see Figure 1).
FIG. 2 is a diagram illustrating a specific configuration example. The embodiment shown in the figure shows a case where the address bus is 8 bits. In this case, the ROM access area is #0 as shown in FIG.
Assuming that it is 0 to #IF (# indicates hexadecimal),
Addresses above 420 are not for the ROM area. Therefore, as shown in the figure, ORing the three bits following the MSB will serve the purpose.

For example, when accessing the ROM area, the upper 3 bits are all “0°, so the OR gate 20
The output of becomes "0". On the other hand, when an area other than the ROM area is being accessed, at least one of the upper three bits becomes "1#", so the output of the OR gate 20 is "1".
It becomes °.

In the above explanation, the microprocessor changed the read signals PSN and RD when reading data from the ROM and from the RAM, respectively, but the 1-bit read/write signal (R
/W) It can also be shared as a signal. In other words, R
When the /W signal is at 1" level, it is used as a read signal, and when it is at "0" level, it is used as a write signal.

FIG. 3 is a block diagram showing another embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals.

In the embodiment shown in the figure, the R/W signal of the microprocessor 1 and the NOR output of the program area detection circuit 13 are used as abnormality notification signals.

In this example, when the microprocessor 1 is accessing the ROM area and there is a write signal, the output of the NOR gate 14 becomes "1" level, which can notify that the microprocessor is abnormal.

[Effects of the Invention] As described in detail above, according to the present invention, when the microprocessor accesses the program ROM area and outputs a RAM read signal, the microprocessor It is possible to provide a microprocessor operation confirmation method that can reliably detect malfunctions in the microprocessor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing a specific configuration example of a program area detection circuit. FIG. 3 is a configuration block diagram showing another embodiment of the present invention. FIG. 4 is a conventional block diagram. FIG. 5 is a diagram showing an example of a circuit, and FIG. 5 is a diagram showing address space allocation. In FIG. 1, 1 is a microprocessor, and 11 is a program ROM. 12 is RAM. 13 is a program area detection circuit, and 14 is a NOR gate.

Claims (1)

[Claims] The microprocessor (1) is a program ROM (11).
A program area detection circuit (13) is provided which receives an address output from the microprocessor (1) and detects access to an area other than the program when reading program data from the program area detection circuit (13). 13) and a read signal for microprocessor (1) to read data from RAM (12).
1. A method for checking the operation of a microprocessor, characterized in that it is configured to be used as an abnormality notification signal.