JPH0210452A - Temporary storage circuit with faulty cell switching function - Google Patents

Abstract

PURPOSE:To present a temporary storage circuit with faulty cell switching function by providing a pattern generating circuit, a first space switch which inserts a pattern to an arbitrary data path, a second space switch for reverse conversion, a pattern collating circuit, and a circuit which controls them. CONSTITUTION:n-number of data inputs and (n+1)-number of data inputs of a pattern generating circuit 101 are inputted to a space switch 102, and the output of the pattern generating circuit 101 is connected to arbitrary one of (n+1)-number of outputs. Data is written in and read from a temporary storage circuit 103 as (n+1)-number of bits, and time slots are transposed. This output is inputted to a space switch 104 and is reverse converted to n-number of data and one pattern. This pattern is inputted to a pattern collating circuit 105 and is successively transferred to data inputs 1-(n) to perform pattern collation. This operation is controlled by a control circuit 106. If error occurs in pattern collation, pattern insertion is fixed to the data path where error occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a time slot 1 replacement device that performs time slot replacement in the order of time slots I:l+T, and more particularly, to a time slot 1 replacement device that performs time slot replacement in the order of time slots I:l+T. Regarding detection and switching.

2. Description of the Related Art Conventionally, a parity check method has been widely used as a means of monitoring temporary memory circuits, in which a 1-bit parity bit is added in addition to the valid information, and the write side checks whether the total number of marks is an odd number or an even number. Monitoring is performed by setting rules to ensure that the number of marks on the reading side is as specified, and in the event of an error, a backup temporary memory circuit prepared in advance is used. I took a method of switching to .

Problems to be Solved by the Invention However, with the conventional dual temporary storage circuit, it is not possible to identify a faulty cell in the temporary storage circuit.

Another disadvantage is that if even one cell fails, the failed temporary storage circuit becomes unusable.

The present invention has been made in view of the conventional two-tiered actual situation, and therefore, the object of the present invention is to provide a novel temporary temporary cell switching function that makes it possible to overcome the disadvantages inherent in the conventional technology. The purpose is to provide a memory circuit.

Means for Solving the Problems In order to achieve the above object, a temporary storage circuit with a faulty cell switching function according to the present invention includes a pattern generation circuit.

a first spatial switch that inserts the pattern into an arbitrary data bus; and a second spatial switch that performs inverse transformation of the first spatial switch.
, a pattern matching circuit, a control circuit for controlling the pattern generation circuit, the first and second spatial switch circuits, and the pattern matching circuit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the operation of the time slot switching device.

As shown in Figure 2, Di-
Write the data of DI4. Then, when reading, the read address is 13.10.3, 1.5...I'
When changed to llT, DI3.010. D3. D
Data is read out in the order of I, D5, . . . As a result, (DI, D2, D3, D4, D5...
・) → (DI3, Dlo, D3. DI, D5...
・) The time slots are replaced in time.

Referring to FIG. 1, in the present invention, there are 0 data inputs and (n + 1) of the pattern generation circuit (PTN GEN) 101.
．． ) book data is input to the (n+1) x (n+1) space switch (SSlil) 102, and (n+1
) Connect the output of the pattern generation circuit 101 to any one of the outputs of the book. Since there are n data inputs, there is no effect on the data. After this, the temporary memory circuit (RAM)
At 103, writing and reading are performed as n,+1 bits, and time slots are exchanged. This output is (
n+1)X (n+1) space switch (ssv) to
It is input to i and converted into n data and one pattern>ip. The data is output as is, and one pattern is input to the pattern matching circuit (PTN CIIK) +05, where it is compared with the inserted pattern. The patterns are verified by sequentially transferring these patterns to the data inputs 1 to n. The control circuit (CONT) 106 controls this.
It is. If an error occurs during pattern matching, the control circuit 106 fixes pattern insertion to the data bus where the error occurred.

As described in detail, according to the present invention, by sequentially changing the generated pattern from 1 to (n+1) of the data inputs, the generated pattern can be stored in the temporary storage circuit without affecting the data time slot switching operation. It is possible to test the previous cell, and by changing the pattern written to the same cell, it is possible to monitor for failures where the output of the temporary memory circuit is fixed. By making the data bus unusable even if a failure occurs, it is possible to temporally replace n time slots of valid data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. lot,, pattern generation circuit (PTN GEN), 1
．． 02.104. ,. (n + 1) X (n + 1) space switch (ss
v), 103. ,,temporary memory circuit (RAM), 105.
,,Pattern matching circuit (PTN CIIK),106,,
, control circuit ('C0NT) FIG. 2 is a time chart showing the operation of the time slot 1 switching device. FIG. 3 is a block diagram of the prior art.

Claims (1)

[Claims] A time slot switching device that switches time slots of the data by sequentially writing data into a temporary storage circuit and reading it out randomly, or by writing data at random and reading it sequentially, includes a pattern generation circuit and an output of the pattern generation circuit A first spatial switch to be inserted into data, a second spatial switch that performs inverse transformation of the first spatial switch, a pattern matching circuit, the pattern generation circuit, first and second spatial switches, and a pattern matching circuit. A temporary memory circuit with a faulty cell switching function, characterized by comprising a control circuit for controlling the circuit.