JPH02104091A - Color signal processor - Google Patents

Abstract

PURPOSE:To obtain a color signal processing unit not causing a low frequency noise or a flicker by holding a signal of a prescribed portion of a chrominance carrier signal inputted synchronously with the start of the unit, using the holding signal and correcting a DC offset of a demodulated color difference signal. CONSTITUTION:Data to correct a DC offset of a demodulated color difference signal is extracted synchronously with the start of the unit and used. The data is not fluctuated between lines and between fields and then no low frequency noise nor flicker takes place. Moreover, the data for DC offset correction of a color difference signal is fetched from a prescribed portion of the chrominance carrier signal of the input. Thus, the occurrence of modulation distortion caused due to the dispersion in the analog circuit element constant or power voltage fluctuation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color signal processing device that once converts a carrier color signal into a color difference signal, performs various color signal processing, and then modulates the carrier color signal again into a carrier color signal. .

[Conventional technology]

When performing digital processing such as noise reduction on a composite video signal using, for example, a field memory, it is convenient to perform demodulation into baseband signals such as a luminance signal and a color difference signal. In this case, the demodulation of the composite video signal consists of: ■ Luminance signal (hereinafter referred to as Y signal) and carrier color signal (
(hereinafter referred to as a C signal); and (1) demodulating the C signal into a color difference signal. Among these processes, process (2) converts the baseband color difference signal component in the form of a digital signal by directly A/D converting the carrier color signal using two types of sampling clocks locked to the color burst signal of the carrier color signal. I am getting .

To explain in more detail using an NTSC color television signal as an example, after separating the NTSC composite video signal from Y/C, the C signal is A/D converted using a sampling clock with a frequency four times that of the color burst signal. , the sampling clock is 06.9 of the color burst phase.
If the phase synchronization is accurate to 0'', 180@ or 270 degrees, the sample data at 180' will be transferred to the B-Y signal, 2
The sample data at 70° can be considered as the RY signal. By distributing these sample data using a subcarrier frequency (fsc) clock, the carrier color signal can be demodulated into two color difference signals.

In addition, in order to modulate the color difference signal component into a C signal, 00 data is changed from 180° phase data to 27° by polarity inversion.
Generate 90″ data from 06 phase data, and generate 180″ data.
°, 270", 0", 90" phase order, sequentially D
/A Convert.

For example, 180' phase data obtained by A/D converting a C signal is I)+a. Then, the generated 00 phase data D0 is given by Do = (Dlso Dc,). Here, D. is the DC offset value of the C signal.

If the value of D cm does not exactly match the A/D conversion data at the center of the C signal, phase distortion will occur in the resulting C signal. Therefore, there is a method in which a sample value of a part of the C signal without a carrier wave, that is, a vertical synchronization period or a horizontal synchronization period, is used as a center value to avoid being affected by the Uc offset fluctuation of the C signal.

[Problem to be solved by the invention]

However, in the conventional example, the DC offset value of the C signal is
If it is at the dark value level of D conversion, the value of D cm is no longer constant, and the phase distortion begins to change line by line or field by field. As a result, there is a drawback that, for example, when the Dea acquisition period is a horizontal synchronization period, low-frequency noise occurs, and when it is a vertical synchronization period, flicker occurs.

Therefore, it is an object of the present invention to provide a color signal processing device that does not cause such low frequency noise or flicker.

[Means to solve the problem]

A color signal processing device according to the present invention is a device that demodulates a carrier color signal into a color difference signal using a clock that is phase-synchronized with its reference phase, performs predetermined processing, and then modulates the carrier color signal again into a carrier color signal. The apparatus is characterized by comprising a correction means for correcting the reliability of a predetermined portion of the inputted carrier color signal in synchronization with the startup of the apparatus.

[Effect]

The data for correcting the DC offset of the demodulated color difference signal is extracted and used in synchronization with the device startup by the above-mentioned holding means, so this data does not vary between lines or fields, and therefore the low frequency No noise or flicker occurs. Furthermore, since data for DC offset correction of the color difference signal is taken in from a predetermined portion of the input carrier color signal, it is possible to prevent modulation distortion caused by individual deviations of analog circuit element constants, power supply voltage fluctuations, etc.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG.
3 and 3 show their timing charts.

In Fig. 1, 10 is an A/D converter, 12°14.1
6 is a latch circuit, 17 is an AND gate, 1B, 19.
20.21, 22, 23.24 are full adders, 26, 27
．． 28 is an inverter, 30゜32.34.36 is a border circuit (Q) with output control (output/high impedance switching)
C latch circuit), 38 is a D/A converter, 40 is a PLL circuit, and 42 is a timing controller. In addition, latch circuits 12 to 16, 30 to 36 and inverter 26°2
7.28 are provided in parallel for the number of output bits of the A/D converter 10. 50 is an input terminal for a C signal obtained by separating Y/C from a composite video signal; 51A is an input terminal for a clock generated during the horizontal or vertical synchronization period; 51B is an input terminal for a flag signal indicating system activation; An input terminal for a timing signal representing the section of the color burst signal,
53 is a C(i(7) output terminal), and 54, 56.58 are constant values.

1' (hexadecimal) input terminal.

The output 42A of the timing controller 42 is an A/D conversion clock, the outputs 42B and 42C are C signal demodulation clocks, and the outputs 42D, 42E, 42, F, 42G,
42H is a timing signal for data transfer, 42J is D/A
These are conversion clocks, which are synchronized by the PLL circuit 40 with the timing signal (and therefore the color burst signal) at the input terminal 52. 70.72 is a data bus for demodulated color difference signals, and 74.76 is a data bus for carrying opposite polarity data generated by modulation processing.

The PLL circuit 40 extracts a color burst signal from the C signal at the input terminal 50 in accordance with the timing signal at the input terminal 52, and outputs clocks 40A, 40B of frequencies 4fs, c (fsc is the color subcarrier frequency) phase-synchronized with this signal. . Accordingly, the timing controller 42
A D conversion clock 56A (frequency 4fsc) is applied to the A/D converter 10. As a result, the C signal at the input terminal 60 is converted to digital data, and the latch circuit 12.
14.16 applied. timing controller 4
2 also has clocks (frequency fsc) 42B with a constant phase difference and a 90" phase difference with respect to the color burst signal.
, 42C and applied to the control input of the latch circuit 12.14. As a result, the output data of the A/D converter 10 is separated and demodulated into color difference components, and each data bus 7
It is sent out above 0.72.

The color difference signal components, including DC offset, are transferred via data buses 70 and 72 to a digital signal processing circuit (DSP) 10.
0, and is subjected to predetermined digital signal processing using field memory, such as image enlargement, composition, and noise reduction processing. Digital signal processing circuit 10
Since the signal processing itself in 0 is well known, its explanation will be omitted. The digital signal processing circuit 100 is
Two types of color difference signals processed as described above are output.

Next, a process of modulating the digital color difference signal output by the digital signal processing circuit 100 into a carrier color signal will be described. The AND gate 17 follows the flag signal of the input terminal 51B and allows the timing signal of the input terminal 51A to pass only when the system is started. In response, the launch circuit 16 latches the output of the A/D converter 10. That is,
The latch circuit 16 latches the output of the A/D converter 10 during the horizontal synchronization period immediately after system startup. The data output from the A/D converter 10 includes a DC offset, with the color signal component being 08 and the DC offset component being D.
co, the obtained data C9X is CDX = Cx + D ca . If the opposite polarity data to be created is CPX, then CPX=CX+DCll=(Cox Dca)+Dca. Therefore, if this operation is configured with a full adder and an inverter, CPX=DCII+COX+DC11+ 1 +
It becomes 1.

In the illustrated embodiment, the output of the latch circuit 16 corresponds to the DC offset D ca in the above formula, which is inverted by the inverter 26 and added by 1 by the full adder 18 . Since CDX is obtained from the digital signal processing circuit 100, it is taken in by full adders 19 and 20. Thereafter, the above calculation is completed by full adders 21 to 24 and inverters 27 and 28.

Through these processes, desired inverted polarity data is obtained from full adders 23, 24 and sent onto inverted polarity data buses 74, 76, respectively.

The color difference components output from the digital signal processing circuit 100, together with the data on the inverted polarity data buses 74 and 76,
Latch circuits 30.32, 34.3 by clock 42D
6, output control signals 42E, 42F, 42G
, 42H, the output order is controlled by the D/A converter 38.
is applied to

The D/A converter 38 converts the input digital signal into an analog signal and outputs the analog signal according to the clock 42J. The output of the D/A converter 38 corresponds to a carrier color signal that has undergone predetermined signal processing.

In the above configuration, if the extracted DC offset value D cm does not match the A/D conversion data of the DC offset of the C signal, the modulation waveform will be distorted. In this embodiment, when the system is started, A/D conversion data of a horizontal synchronization period in which no carrier color signal exists is extracted and used as the DC offset value D cm.

Therefore, the extracted DC offset is extremely accurate, which prevents the occurrence of modulation distortion caused by individual deviations of analog circuit element constants, power supply voltage fluctuations, etc.
It is possible to prevent low-frequency noise and flicker caused by fluctuations in the cm value.

In the above configuration, the DC offset of the color difference signal input to the latch circuits 30 and 32 and the DC offset Dc0 output from the launch circuit 16 are determined by the digital signal processing circuit 10.
0, the processing time timing is shifted, but the period required for the fluctuation of the DC offset is the same as that of the digital signal processing circuit 100.
Since the processing time is sufficiently longer than the processing time in , this is not a problem.

A value obtained by sampling a plurality of DC offset values in one horizontal opening period or vertical synchronization period and averaging them may be used as Dco in the above calculation process.

In this way, even more accurate cm can be obtained.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, the DC offset data necessary for modulating a color difference signal into a carrier color signal is taken in at the time of system startup.
Low-frequency noise and flicker caused by fluctuations in offset data can be prevented. Also, since the DC offset data is imported from the part where there is no color signal component,
It is possible to prevent modulation distortion caused by individual deviations of analog circuit element constants, power supply voltage fluctuations, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are timing charts thereof. 12.14, 16.30~36-latch circuit 17-・
-AND gate 18-24-Full adder 26.27
．． 28...-Inverter 40-...PLL circuit 42-
Timing controller t o - Digital signal processing circuit (2 t52 (3) 542A (4) 1/10 (5) 2B (6) Diagonal 42C (7) Bus 7° (8) No. Sufu 2 (9) Pass 74 (10) Nogusufu 6 (11 boiling 542D (12) Peeling 42E (13 return 842F (14) 1842G (15) Fee 42H (16), 438 hearts (17) Li 42'' 3rd figure

Claims (1)

[Claims] A device that demodulates a carrier color signal into a color difference signal using a clock that is phase-synchronized with its reference phase, performs predetermined processing, and then modulates it again into a carrier color signal. A holding means for holding a signal of a predetermined portion of a carrier color signal held by the holding means, and a correction means for correcting a DC offset of a demodulated color difference signal using the signal held by the holding means. Color signal processing device.