JPH02104094A - Color signal processor - Google Patents

Abstract

PURPOSE:To obtain a color signal output with a constant hue at all times by retarding a color difference signal in the PAL system and adding a retarded delay signal to the color difference signal. CONSTITUTION:A pseudo color difference component differs from each line if the demodulation axis is not coincident with the axis of B-Y and R-Y components. Then each pseudo orthogonal color difference component is added between lines by using a delay circuit 47 and full adders 45, 46. That is, each color component is subjected to inter-line addition. That is, a signal of a line A and its succeeding line B is added between lines. Then each color component takes a form of multiplying a prescribed scalar quantity multiplied respectively with the B-Y signal and the R-Y signal and the hue is made constant. Thus, the color difference signal is the complete B-Y signal and R-Y signal including the DC offset.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a color signal processing device that demodulates a carrier color signal compliant with the PAL system, and more specifically to a color signal processing device suitable for digital signal processing. Regarding.

[Conventional technology]

When performing digital processing such as noise reduction on a composite video signal using, for example, a field memory, it is convenient to perform demodulation into baseband signals such as a luminance signal and a color difference signal. In this case, the demodulation of the composite video signal consists of: ■ Luminance signal (hereinafter referred to as Y signal) and carrier color signal (
(hereinafter referred to as a C signal); and (1) demodulating the C signal into a color difference signal. Among these processes, in process (2), the carrier color signal is directly A/D converted using two types of sampling clocks that are phase-synchronized with the color burst signal of the carrier color signal, thereby converting the carrier color signal into a baseband color difference signal in the form of a digital signal. I'm getting the ingredients.

To explain in more detail using an NTSC color television signal as an example, when an NTSC composite video signal is Y/C separated and the C signal is A/D converted using a sampling clock with a frequency four times that of the color burst signal, The relevant sampling clock is color 1 - burst phase 0''
, 90°, 180'' or 2700, sample data at 180'' can be regarded as a BY signal, and sample data at 270° can be regarded as an RY signal. The carrier color signal can be demodulated into two color difference signals by distributing these sample data using a clock at the subcarrier frequency (rsc).

In addition, in order to modulate the color difference signal component into a C signal, polarity inversion is used to convert 0'' data from 180° phase data to 27
Generate 90° data from 0° phase data and sequentially D
/A Convert.

For example, if the 180° phase data obtained by A/D converting the C signal is Dllo, the generated 00 phase data D0 is given by Do''' (D+io DC-).

Here, DC is the DC offset value of the C signal.

The above conventional example is for the NTSC system, and in the case of the PAL system, the carrier wave of the R-Y signal is inverted for each scanning line, so the burst phase of the scanning line is monitored and the data to be distributed is divided line by line. It is necessary to switch to . P.A.
In the L method, the B-Y signal carrier is fixed at 90", and the R-Y signal carrier is fixed at 90".
The signal components are θ° (color burst phase at this time is 315') or 180'' (color burst phase at this time is 225°), and these are distributed and demodulated.

In addition, in the NTSC system, in processes that do not directly deal with hue, such as noise reduction, the demodulation axis is not absolutely fixed as described above (but if the orthogonal relationship can be preserved, demodulation processing, signal processing, modulation processing A series of processes can be performed without any problems. Therefore, the A/D clock only needs to be synchronized at a frequency four times that of the carrier wave, and the phase relationship can be ignored.

[Problem to be solved by the invention]

On the other hand, the following problem occurs in the PAL system.

Figure 4 is a vector representation of the state of orthogonal demodulation when the demodulation axis is not phase-synchronized with the B-Y axis and the R-Y axis. Then it becomes vector OB.

This carrier color signal is A/D converted and demodulated using a sampling clock shifted by a phase φ from the BY axis and the RY axis. The color components at this time are as follows.

Line A CXA= r cos (θ-φ) CyA= r sin (θ-φ) Line B CXB= r cos (θ+φ) Cys= r sin (θ+φ) However, r is the absolute value of vector OA and the same OB, That is, it is the amplitude of the carrier color signal component.

As described above, since the color signal components obtained for each line are not the same, a problem arises in that the hue cannot be preserved when inter-field processing is performed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a color signal processing device that can always obtain a color signal output of a constant hue.

[Means to solve the problem]

A color signal processing device according to the present invention includes a demodulating means for demodulating a first color difference signal and a second color difference signal using a clock whose phase is synchronized with a reference phase of a carrier color signal conforming to the PAL system; a first delay means for delaying the first time;
a first addition means for adding a first delayed signal delayed by the first delay means to the first color difference signal; and a first addition means for adding the first delayed signal delayed by the first delay means to the first color difference signal;
The present invention is characterized in that it is provided with a second delay means for delaying the second color difference signal, and a second addition means for adding the second delay signal delayed by the second delay means to the second color difference signal.

[Effect]

The first delay means and the first addition means can always keep the hue of the first color difference signal constant between fields, and the second delay means and second addition means can keep the hue of the second color difference signal constant between fields. can be kept constant at all times. Therefore, color signal processing between fields becomes extremely easy.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration block diagram of an embodiment in which the present invention is applied to a modulation/demodulation device that demodulates a carrier chrominance signal, performs various digital processing, and modulates the carrier chrominance signal again.
FIGS. 2B and 3 show waveform diagrams for explaining the operation.

In Figure 1, 10 is an A/D converter, 12.14.16
are latch circuits, 18, 19. 20, 21° 22. 23.
24 is a full adder, 26, 27.28 is an inverter, 30
, 32.34.36 is a latch circuit (QC latch circuit) with output control (output/high impedance switching), 38 is D
/A converter, 40 is a PLL circuit, 42 is a timing controller, 43 is an LH line memory that provides a delay amount equivalent to 284 sample times, 44 is an IHH line memory that provides a delay amount that is equivalent to 283 sample times, 45°46 is a full adder, 47 is a delay circuit corresponding to one sample time (specifically, a D-type flip-flop), and 48 is a memory 4.
This is a selection circuit that selects one of the outputs of the delay circuit 47 and the output of the delay circuit 47. In addition, latch circuits 12 to 16, 30 to 36
, inverters 26, 27, 28, line memory 43.
44, the delay circuit 47 and the selection circuit 48 are provided in parallel for the number of output bits of the A/D converter 10.

50 is an input terminal for a C signal obtained by Y/C separation of a composite video signal; 51 is an input terminal for a clock generated during a horizontal or vertical synchronization period; 52 is an input terminal for a timing signal representing a section of a color burst signal; 53 is an output terminal for the C signal, and 54, 56.58 are input terminals for a constant value "01" (hexadecimal).

The output 40A of the PLL circuit 40 is the color signal of the carrier color signal.
The output 40B is a quadruple frequency clock that is phase synchronized with the burst signal, and the output 40B is a clock with a carrier wave period that is in a constant phase relationship with the color burst signal of the carrier color signal, which is obtained by dividing the output 40A by four. timing controller 4
2 output 42A is the A/D conversion clock, output 42B,
42C is a C signal demodulation clock, and outputs 42D and 42E.

42F, 42G, 42H are data transfer timing signals, 42J is a D/A conversion clock, and these are PL
It is phase-locked to the output 40B of the L circuit 40 (and thus the color burst signal).

70.72 is a demodulated color difference signal data bus, 74
．． 76 is a data bus carrying data of opposite polarity generated by the modulation process.

The PLL circuit 40 extracts a color burst signal from the C signal at the input terminal 50 according to the timing signal at the input terminal 52, and calculates the average of this burst signal (B-Yvi transmission by 90%).
Clock 40B with carrier wave period synchronized with 180'' phase) and its quadruple frequency liquid (4f3 rsc
(color subcarrier frequency) outputs a clock 40A. In accordance with this, the timing controller 42 applies an A/D conversion clock 56A (frequency 4 f sc) to the A/D converter 10.

As a result, the C signal at the input terminal 50 is converted into digital data and applied to the latch circuits 12, 14, and 16. The timing controller 42 also provides a clock (frequency fsc
) 42B and 42C, respectively, and the latch circuits 12.
14 control inputs. Thereby, the output data of the A/D converter 10 is separated and demodulated into color difference components and becomes a pseudo color difference signal.

At this time, the timing controller 42 detects the phase of the color burst signal of the carrier color signal at the input terminal 50 and switches the polarity of the clock 42C.

Pseudo color difference components obtained in this way (latch circuit 12
．． As described above, the output of 14) will differ from line to line unless the demodulation axis (phase of A/D sample) coincides with the axes of the BY component and the RY component. Therefore, the line memories 43 and 44, the delay circuit 47, the selection circuit 48, and the full adders 45 and 46 perform line-to-line addition of each pseudo color difference component. In other words, when the signals of line A and the following line B are added between lines, the sum is CX
=C×^+CXB =r(cos(θ-φ) +cos(θ+φ)]=2
r cosφ' cos θ cy = CVA+ CVM = r(sin(θ-φ) +5in(θ+φ)]=2r
cosφ6sin θ, and each color component is obtained by multiplying the B-Y signal and the R-Y signal by a constant scalar amount 2 cosφ, respectively,
Hue remains constant. As a result, the color difference signal becomes a complete -Y signal and a -Y signal, although it includes a DC offset.

In the embodiment shown in FIG. 1, the RY signal is switched between 283 sample delay and 284 sample delay for the following reasons. That is, in color difference signals based on the PAL system, the phase of the B-Y signal differs by 90 degrees between lines, and the phase of the G-Y signal differs from +90' to +90' with respect to the B-Y signal, alternating line by line. In this embodiment, each color difference signal that only differs in polarity within the same carrier wave period is dealt with by thinning processing. The relationship between the sample points and the lines is as shown in FIG.

That is, for the B-Y signal, the pixel value delayed by 284 samples becomes the signal with the same phase at the closest position on the screen, and for the R-Y signal, the signal with the same phase at the closest position becomes the signal with the same phase at the closest position on the screen.
The data delayed by 83 samples and the data delayed by 284 samples alternate for each line. Therefore, the RY signal is configured to alternately switch between 283 sample delay and 284 sample delay for each line.

The outputs of the full adders 45 and 46 are sent to the digital signal processing circuit (
The signal is supplied to the DSP (DSP) 100, where it undergoes predetermined digital signal processing using field memory, such as image enlargement, composition, and noise reduction processing. Note that since the signal processing itself in the digital signal processing circuit 100 is well known, a description thereof will be omitted in this specification. The digital signal processing circuit 100 outputs two types of color difference signals that have been processed as described above.

Next, a process of modulating the digital color difference signal output from the digital signal processing circuit 100 into a carrier color signal will be described.

The launch circuit 16 controls the A/D converter 1 during the horizontal 3tII period according to the timing signal of the input terminal 51.
Latch the output of 0. The data output from the A/D converter IO includes a DC offset, and when the color signal component is CX and the DC offset component is DCQ, the obtained data COX is Cox = Cx + Dca. If the opposite polarity data to be created is CPX, then C,, =-CX+De.

= (CD1F DCII) +Dca.

Therefore, if this operation is constructed using a full adder and an inverter, CPX=Dee'' Cnx+Dca+1 +L.

In the illustrated embodiment, the latch circuit 16 is activated by the timing signal at the input terminal 51 to control the A/
D conversion data is held, and this held value is the DC offset l-D of the above formula. corresponds to Inverter 2
6, and a full adder 18 adds 1. CDX
is obtained from the digital signal processing circuit 100, so it is taken in by the full adders 19 and 20. Thereafter, the above calculation is completed by full adders 21 to 24 and inverters 27 and 28.

As a result of these processes, desired inverted polarity data is obtained from the full adders 23, 24, and these are sent onto the inverted polarity data buses 74, 76, respectively.

The color difference components output from the digital signal processing circuit 100, together with the data on the inverted polarity data buses 74 and 76,
Latch circuits 30, 32, 34.3 by clock 42D
6, output control signals 42E, 42F, 42G
.

42I (with the output order being controlled by the D/A converter 38
is applied to The D/A converter 38 converts the input digital signal into an analog signal and outputs the analog signal according to the clock 42J. The output of the D/A converter 38 corresponds to a carrier color signal that has undergone predetermined signal processing.

In the above configuration, if the extracted DC offset value D cs does not match the A/D conversion data of the DC offset of the C signal, the modulation waveform will be distorted. In this embodiment, the horizontal open signal without a carrier color signal is used. iI! Since Tomo's A/D conversion data is used as the DC offset value Dcn to be added, the extracted DC offset is extremely accurate. It is possible to prevent the occurrence of modulation distortion caused by such factors.

Note that in the above configuration, the processing time timing of the DC offset of the color difference signal input to the latch circuits 30 and 32 and the DC offset De output from the latch circuit 16 is different in the digital signal processing circuit 100. , the period required for the DC offset fluctuation is the digital signal processing circuit 1.
This is sufficiently longer than the processing time in 00, so there is no problem.

A value obtained by sampling a plurality of DC offset values during one horizontal opening period and averaging them may be used as Dcll in the above calculation process. This will give you a more accurate co.

In the above embodiment, line memories 43 and 44 perform line-to-line addition within the same field, but of course,
Addition may be performed between frames.

〔Effect of the invention〕

As can be easily understood from the above description, according to the present invention, a color difference signal of a constant hue can be obtained by adding demodulated pseudo color difference signal components between lines. Moreover, the demodulated color difference signal component is exactly 84' signal, l?
-Y signal, color signal processing becomes possible without having to precisely match the phase of the A/D conversion clock to the carrier color signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention; FIGS. 2A, 2B, and 3 are waveform diagrams thereof; FIG. Figure 5 is PA
FIG. 3 is a diagram showing the relationship between sample points and lines of color difference signals in the L method. 12.14, 16.30-36-...Latch circuit 18
~24,45.46-Full adder 43-284 sample line memory 44-283 sample line memory 47-・1 sample delay circuit 48-Selection circuit
100-Digital signal processing circuit

Claims (1)

[Claims] demodulation means for demodulating the first and second color difference signals using a clock whose phase is synchronized with the reference phase of a carrier color signal conforming to the PAL system; and a first delay means for delaying the first color difference signal by a first time. and a first addition means for adding the first delayed signal delayed by the first delay means to the first color difference signal;
A second delay means for delaying a third time different from the time of , and a second addition means for adding a second delay signal delayed by the second delay means to the second color difference signal. color signal processing device.