JPH01177793A - Chrominance signal processor - Google Patents

Abstract

PURPOSE:To prevent the modulation distortion of a signal caused by the solid-state deviation of analog circuit element constant and power source voltage variation by using A/D-converted data during a horizontal synchronizing period in which no carrier chrominance signal is present as a DC offset value to be added. CONSTITUTION:In case of modulating an orthogonal color difference signal into a carrier chrominance signal, a latch circuit 16 latches an output from an A/D converter 10 during a horizontal synchronizing period in accordance with a timing signal from an input terminal 51. This output from the converter 10 is constituted of a chrominance signal component added with a DC offset component, hence data of opposite magnetic polarity to be generated goes to a DC offset component from which the chrominance signal component is subtracted. An output from the circuit 16 is inverted by an inverter 26, goes through a full adder 18, etc., and inputted to full adders 19, 20, so that desired data of inverted polarity can be obtained from full adders 23, 24. This means that, by using A/D-converted data during a horizontal synchronizing period in which a carrier chrominance signal does not exist as a DC offset value to be added, the modulation distortion of data caused by the solid-state deviation of analog circuit element constant and power source voltage variation can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus that once converts a carrier color signal into an orthogonal color difference signal and performs various color signal processing.

[Conventional technology]

When performing digital processing such as noise reduction on a composite video signal using, for example, a field memory, it is convenient to perform demodulation into baseband signals such as a luminance signal and a color difference signal. In this case, the demodulation of the composite video signal consists of: ■ Luminance signal (hereinafter referred to as Y signal) and carrier color signal (
(hereinafter referred to as a C signal); and (1) demodulating the C signal into a color difference signal. Among these processes, in process (2), the carrier color signal is directly A/D converted using two types of sampling clocks locked to the color burst signal of the carrier color signal, thereby converting the base of the quadrature phase of the digital signal format. Band color difference signal components are obtained.

To explain in more detail, the NTSC composite video signal is
After separation, when the C signal is A/D converted using a sampling clock with a frequency four times that of the color burst signal, the sampling clock is 06 times the color burst phase.
．． 90°, 180° or 270°.

If the phase is accurately locked to , sample data at 180° can be regarded as the BY signal, and sample data at 270° can be regarded as the RY signal. By distributing these sample data using a subcarrier frequency (rsc) clock, the carrier color signal can be demodulated into two color difference signals.

In addition, in order to modulate the color difference signal component into a C signal, polarity inversion converts 06 data from 180" phase data to 2
906 data are generated from the 70° phase data and sequentially D/A converted.

For example, 180@phase data obtained by A/D converting a C signal is Dll. Then, the generated 06 phase data D is given by Do = -(DIS@Dc-). Here, D cm is the DC offset value of the C signal.

[Problem to be solved by the invention]

The conventional example described above has a problem in that the modulated C signal has phase distortion unless the value of D cm exactly matches the center value of the C signal.

Therefore, an object of the present invention is to provide a color signal processing device that does not cause such phase distortion.

[Means to solve the problem]

A color signal processing device according to the present invention demodulates a carrier color signal into an orthogonal color difference signal using a clock phase-locked to its reference phase, performs predetermined processing, and then modulates the carrier color signal again into a carrier color signal, the device comprising: The present invention is characterized in that the DC offset correction of the orthogonal color difference signal is performed using a signal indicating the level of the input carrier color signal during the horizontal retrace period.

[Effect]

Since the signal indicating the level of the horizontal retrace period extracted from the input carrier color signal is used as the DC offset, the influence of DC offset fluctuations on the input carrier color signal can be removed, and the output carrier color signal will not be adversely affected. It will fall short.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of the present invention, and FIGS. 2 and 3 show waveform diagrams for explaining its operation.

In Fig. 1, 10 is an A/D converter, 12°14.1
6 is a latch circuit, 18, 19.20, 21.22.23
．． 24 is a full adder, 26.21°28 is an inverter, 3
Is 0.32.34.36 the output side? A border circuit (QC latch circuit) with I (output/old-2 switching), 38 a D/A converter, 40 a PLL circuit, and 42 a timing controller. Note that the latch circuits 12 to 16, 30 to 36, full adders 18 to 24, and inverters 26, 27, and 28 are
The same number of output bits of the /D converter 10 are provided in parallel. 50 is C obtained by separating the composite video signal from Y/C.
A signal input terminal; 51 is a clock input terminal obtained from a synchronization separation circuit (not shown) to indicate a horizontal synchronization period during a horizontal retrace period; 52 is a timing signal input terminal representing a color burst signal section; 53 is a timing signal input terminal; C signal output terminal, 5
4.56°58 is an input terminal for a constant value "01° (octal).

The output 42A of the timing controller 42 is a clock for A/D conversion, the outputs 42B and 42C are clocks for C signal demodulation, the outputs 42D, 42E, 42F, 42G, and 420 are timing signals for data transfer, and 42J is a D/A clock. These are conversion clocks, which are synchronized with the timing signal (and therefore the color burst signal) at the input terminal 52.

70.72 is a demodulated color difference signal data bus, 74
．． 76 is a data bus carrying data of opposite polarity generated by the modulation process.

The PLL circuit 40 extracts a color burst signal from the C signal at the input terminal 50 in accordance with the timing signal at the input terminal 52, and outputs clocks 40A and 40B having a frequency (4 fsC) four times the color subcarrier frequency rsc locked to this signal. . Accordingly, the timing controller 42
A/D conversion clock 56A (frequency 4fsc)
applied to the converter 10. As a result, the C of the input terminal 60
The signal is converted to digital data, and the latch circuit 12
゜14.16. The timing controller 42 also generates clocks (frequency fsc) 42 that have a constant phase difference and a phase difference of 90 degrees with respect to the color burst signal.
B, 42C are generated and applied to the control input of latch circuit 12.14. As a result, the output data of the A/D converter 10 is separated and demodulated into orthogonal color difference components, and the data and
It is sent out on bus 70.72.

The orthogonal color difference signal components including the DC offset via the data bus 0872 are processed by the digital signal processing circuit (DSP).
100, and the circuit performs predetermined digital signal processing using field memory, such as image enlargement, composition, and noise reduction processing. Since this signal processing itself is well known, its explanation will be omitted in this specification. The digital signal processing circuit 100 outputs two types of orthogonal color difference signals that have been processed as described above. The process of modulating this processed orthogonal digital color difference signal into a carrier color signal will be described below.

The latch circuit 16 latches the output of the A/D converter 10 during the horizontal synchronization period according to the timing signal of the input terminal 51. The data output from the A/D converter 10 includes a DC offset, and if the color signal component is CM and the DC offset component is Dca, the obtained data C0
is 0 which is C□xCx +Dc*.If the opposite polarity data to be created is CFX, then cpx''-CM+DC@=(CIIX-Dca)''Dcm. Therefore, this operation can be performed using a full adder and an invert CF! −
DC11+ Cox+ Dca+ 1 + 1.

In the illustrated embodiment, the output of the launch circuit 16 corresponds to the DC offset D cm in the above formula, which is inverted by the inverter 26 and added by 1 by the full adder 18. Since C□ is obtained from the signal processing circuit 100, the full adder 19.20
I'm incorporating this.

After that, full adder, devices 21 to 24 and inverter 27°28
This completes the above calculation.

As a result of these processes, desired inverted polarity data is obtained from the full adders 23 and 24, and these are output from the digital signal processing circuit 100, which sends them onto the inverted polarity data buses 74 and 76, respectively. The orthogonal chrominance components, along with the data on the inverted polarity data bus 74.76,
Latch circuits 30.32, 34.3 by clock 42D
6 and output control signals 42'E, 42F, 42
G.

The output order is controlled by 42H and applied to the D/A converter 38. The D/A converter 38 converts the input digital signal into an analog signal and outputs the analog signal according to the clock 42J. The output of the D/A converter 38 corresponds to a carrier color signal that has undergone predetermined signal processing.

In the above configuration, the extracted DC offset value. does not match the A/D conversion data of the DC offset of the C signal, the modulation waveform will be distorted. is used as the DC offset value D cm to be added, so the extracted DC offset is extremely accurate, and this makes it possible to prevent the occurrence of modulation distortion caused by individual deviations of analog circuit element constants, power supply voltage fluctuations, etc. It can be prevented.

In addition, in the above-described configuration, the DC offset of the orthogonal color difference signals input to the latch circuits 30 and 32 and the latch circuit 16
What is the DC offset D cm output by signal processing circuit 1?
00, the processing time timing is off, but the period required for DC offset fluctuation is the signal processing circuit! This is sufficiently longer than the processing time in OO, so it is not a problem.

FIG. 4 shows a block diagram of another embodiment of the present invention,
In the figure, the same numbers are given to the same components as in FIG. 1, and the explanation is omitted. When modulating the input carrier color signal into a carrier color signal, it is not necessary to remove the negative influence of the DC offset of the input carrier color signal (this is to remove the DC offset of the orthogonal color difference signal supplied to the signal processing circuit 100 in advance). .

DC offset component D c extracted by latch circuit 16
m is inverted by an inverter 26, subjected to complement processing by a full adder 18, and then applied to full adders 19 and 20. The demodulated color difference signal components output from the latch circuits 12 and 14 are also applied to the full adders 19 and 20. Therefore, the full adders 19 and 20 convert the DC offset components from the color difference signal components including the DC offset component. Processing equivalent to subtracting the offset component D cm is performed. In other words, the outputs of the full adders 19 and 20 are color difference signal components that do not include DC offset.

The color difference signal components not including the DC offset obtained by the full adders 24 and 26 are sent to the digital signal processing circuit (DSP) 1.
00, and the circuit 100 outputs two types of orthogonal color difference signals processed as described above. Signal processing circuit 1
The color difference signal data from 00 is sent to inverter 140.142.
Full adder 132 . '134 supplied.

A/D converter 10 and D/D converter 10 are connected to input terminals 165 and 166.
Data of 1/2 of the full scale (that is, the maximum value of digital processing) of the A converter 38 is inputted. Furthermore, a value obtained by adding 01'' (octal) to the input of the input terminals 165 and 166 is applied to the input terminals 167 and 168. For example, if the output of the A/D converter 10 is 6 bits, '20 for input terminals 165 and 166
"(octal) is applied, and input terminals 167 and 168 have ""
2 do (octal) is applied.

Therefore, the full adders 132 and 134 perform complement correction and addition to provide a predetermined amount of DC offset to obtain polarity-inverted data. Full adder 12
In 8.130, only the addition of the DC offset is performed on data whose polarity has not been inverted. Each of the above terminals 165
, 166.167.168 are set to the above values for effective use of the dynamic range.

In this way, orthogonal color difference signal data with polarity inversion is obtained from the full adders 132 and 134, and orthogonal color difference signal data without polarity inversion is obtained from the full adders 128 and 134. These are connected to latch circuits 30, 32, 34 . by clock 42D.
36, output control signals 42E, 42F, 42
The output order is controlled by G and 42H, and the D/A converter 3
8. The D/A converter 38 uses a clock 42J
Converts the input digital signal to an analog signal and outputs it.

It goes without saying that this embodiment also provides the same effects as the embodiment shown in FIG. 1.

Note that a plurality of DC offset values are sampled during the horizontal synchronization period, and the averaged value is used as the DCl value in the above calculation process.
You can also use it closed, this way it will be more accurate.ca
is obtained.

〔Effect of the invention〕

As can be easily understood from the above description, according to the present invention, analog circuit element constants are It is possible to prevent the occurrence of modulation distortion caused by individual deviations, power supply voltage fluctuations, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of one embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams thereof, and FIG. 4 is a block diagram of the configuration of another embodiment of the present invention.

Claims (1)

[Claims] A device that demodulates a carrier color signal into an orthogonal color difference signal using a clock phase-locked to its reference phase, performs predetermined processing, and then modulates it again into a carrier color signal, the horizontal retrace period of the input carrier color signal 1. A color signal processing device that performs DC offset correction of the orthogonal color difference signal using a signal indicating the level of the color difference signal.