JPH02102546A - Manufacture of gaas semiconductor device - Google Patents
Manufacture of gaas semiconductor deviceInfo
- Publication number
- JPH02102546A JPH02102546A JP63257772A JP25777288A JPH02102546A JP H02102546 A JPH02102546 A JP H02102546A JP 63257772 A JP63257772 A JP 63257772A JP 25777288 A JP25777288 A JP 25777288A JP H02102546 A JPH02102546 A JP H02102546A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- parts
- drain
- electrodes
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 238000007747 plating Methods 0.000 abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に関し、特にＧａＡｓ
Ｆｌｌｉ：Ｔ （Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａ
ｎｓｉｓｔｏｎ 、電界効果トランジスタ）素子におけ
る電極形状の改良に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
Flli:T (Field Effect Tra
This invention relates to improvements in the shape of electrodes in field effect transistor (NSISTON, field effect transistor) devices.
第３図（ａｌ 、 （ｂｌは従来のＧａＡ ｓ半導体装
置の主要製造段階における断面図である。FIG. 3 (al, (bl) are cross-sectional views of a conventional GaAs semiconductor device at the main manufacturing stages.
第３図ｆ＆）において、ＧａＡｓ半導体基板（１）上の
活性層（２）の上にソース電極（８）、ドレイン電極（
４）をリフトオフ法を用いて形成する。次に、リセスを
エツチングにて形成した後にリフトオフ法にてゲート電
極（６）を形成し、その後、各電極保護の誘電体パッシ
ベーション膜、例えば５ｉｓＮａ 、８１ＯＮ等の膜（
６）を形成する。次に第３図（ｂｌに示すように、めっ
き形成のためパッシベーション膜（６）の所定位置をバ
ッファドフッ酸、ＲＩＥ等でエラチングラ行った後、金
めつき（γ）を形成する。その後、０ａＡｓ半絶縁性基
板（１）の裏面を研摩エツチングを行い所定の厚さにし
、その裏面電極（８）を蒸着、又はＶｉａ Ｈｏ１ｅ工
程後裏面金めつきを形成する。In Fig. 3 f &), a source electrode (8) and a drain electrode (
4) is formed using a lift-off method. Next, after forming a recess by etching, a gate electrode (6) is formed by a lift-off method, and then a dielectric passivation film for protecting each electrode, such as a film of 5isNa, 81ON, etc.
6) Form. Next, as shown in FIG. 3 (bl), for plating formation, predetermined positions of the passivation film (6) are etched using buffered hydrofluoric acid, RIE, etc., and then gold plating (γ) is formed. The back surface of the insulating substrate (1) is polished and etched to a predetermined thickness, and an electrode (8) on the back surface is vapor-deposited, or gold plating is formed on the back surface after the Via Hole process.
第４図は上記製造工程で造られた半導体装置の平面図で
ある。FIG. 4 is a plan view of a semiconductor device manufactured by the above manufacturing process.
このように構成されたＧａＡｓＦＥＴを動作させると、
ドレイン電極（４）からソース電極チャネル部（３ａ）
に電流が流れ、ソース電極バット部（３ｂ）からワイヤ
で外部に電流が供給される。素子に電流が流れると発熱
するが、この場合、ソース電極、ドレイン電極のチャネ
ル部（３ａ） 、 Ｃ３ｂ）はボンディングバット部（
３ｂ） 、 （４ｂ）に比べ電極の断面積が小さくなシ
、電流密度が高くなりチャネル部分の温度が最も高くな
る。When the GaAsFET configured in this way is operated,
From drain electrode (4) to source electrode channel part (3a)
A current flows through the source electrode butt portion (3b) and the current is supplied to the outside through a wire. When current flows through the device, it generates heat; in this case, the channel portions (3a), C3b) of the source and drain electrodes are connected to the bonding butt portions (
3b) Compared to (4b), the cross-sectional area of the electrode is smaller, the current density is higher, and the temperature in the channel portion is the highest.
また、このよりなＧａＡｓＦＥＴを高出力化するために
はゲート幅を長くしドレイン電流を増加させる必要があ
る。Furthermore, in order to increase the output power of this stiff GaAsFET, it is necessary to increase the gate width and increase the drain current.
従来のＧａＡｓ半導体装置の製造方法は以上のように構
成されていたので、ＧａＡｓＦＥＴの大出力化のためド
レイン電流を増加させるとソース電極。Conventional methods for manufacturing GaAs semiconductor devices have been configured as described above, so if the drain current is increased to increase the output of the GaAs FET, the source electrode.
ドレイン電極の電流密度が増加し素子の温度が上昇する
という問題があり、また電流密度を下げるには各電極の
断面積を大きくすることが必要であるがめっきの厚みは
レジスト厚及び、パターン精度等の制約がありあまシ厚
くできないため、ソース電極長、ドレイン電極長を広く
する必要がある。There is a problem that the current density of the drain electrode increases and the temperature of the element rises.Also, to lower the current density, it is necessary to increase the cross-sectional area of each electrode, but the plating thickness depends on the resist thickness and pattern accuracy. Due to such restrictions, it is not possible to increase the thickness, so it is necessary to increase the length of the source electrode and the drain electrode.
したがって各電極長を広げることによりチップサイズが
大きくなるという問題点があった。Therefore, there was a problem in that increasing the length of each electrode increased the chip size.
この発明は上記のような問題点を解消するためになされ
たもので、ＧａＡｓＦＥＴの素子のチップサイズを大き
くすることなく、ドレイン電流を増加できる半導体装置
の製造方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the drain current without increasing the chip size of a GaAsFET element.
この発明の半導体装置の製造方法はソース、ドレインの
各電極の形成において、マスクパターンを変えることに
よシ、各電極の形状を各チャネル部先端の幅を狭く、給
電側で幅広く形成するようにしたものである。The semiconductor device manufacturing method of the present invention changes the mask pattern in forming each source and drain electrode, so that the shape of each electrode is formed so that the width at the tip of each channel part is narrow and the width is wide at the power supply side. This is what I did.
この発明によるＧａＡｓ半導体装置のソース、ドレイン
各電極はチャネル部での電流値が小さい先端部は電極を
狭く、またチャネル部で最も電流値の大きい給電側の電
極を広くすることにより、ソース、ドレイン各電極のチ
ャネル部の電流密度を均一にする。In the source and drain electrodes of the GaAs semiconductor device according to the present invention, the electrodes are narrow at the tips where the current value in the channel part is small, and the electrodes on the power supply side where the current value is the largest in the channel part are widened. Make the current density uniform in the channel part of each electrode.
以下、この発明に係るＧａＡ Ｓ半導体装置の製造方法
の一実施例を図について説明する。An embodiment of the method for manufacturing a GaAs semiconductor device according to the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例であるＧａＡｓ Ｆ Ｅ
Ｔ素子に適用した場合の半導体装置の平面図、第２図（
ａｌ ｔ （ｂｌは第１図のＧａＡｓＦＥＴ素子−のＡ
−Ａ、Ｂ−Ｂ線における部分断面図である。FIG. 1 shows a GaAs F E which is an embodiment of the present invention.
A plan view of a semiconductor device when applied to a T element, FIG.
al t (bl is A of the GaAsFET element in Fig. 1)
-A, is a partial sectional view taken along line BB.
すなわち、この実施例においても、ＧａＡｓＦＥＴ素子
は前記従来のものと同様に半絶縁性基板（１）の活性層
（２）上の所定の位置にソース電極（８）、ドレイン電
極（４）をリフトオフ法にて形成する。この場合ソース
電極（８）、ドレイン電極（４）の各チャネル部（３１
） 、 （４ａ）の形状を先端部を狭く、給電側を広く
するためには各電極の形状に合わせて、写真製版用フォ
トマスクを変えるだけでよく、他の形成方法は、従来の
ものと全く同じである。次にリセスエッチングを行った
後、ゲート電極（５）をリフトオフ法で所定の位置に形
成する。この際、ソース電極（８）、ドレイン電極（４
）の形状は従来と異るが、各電極チャネル間は常に平行
であるので、フォトマスクを変えるだけで従来と同一方
法にて形成できる。次に、各電極保護の誘電体パッシベ
ーション膜（例えば、Ｓｉ ３ Ｎ４ 、８１ＯＮ膜等
）（６）を形成した後、パッシベーションＭ（６）の所
定の位置をバックアトフッ酸、ＲＩＥ等でエツチングを
行い、その後に金めつきを形成する。次に、ＧＬＡＳ半
絶縁性基板（１）の裏面を研摩エツチングを行い、所定
の厚さにし、その面に裏面電極（８）を蒸着、又はＶｉ
ａＨｏｌｅ工程後金めつきを形成する。That is, in this embodiment as well, the GaAsFET element is manufactured by lifting off the source electrode (8) and drain electrode (4) at predetermined positions on the active layer (2) of the semi-insulating substrate (1), as in the conventional device. Formed by law. In this case, each channel part (31) of the source electrode (8) and drain electrode (4)
), In order to make the shape of (4a) narrower at the tip and wider at the power supply side, it is only necessary to change the photolithography photomask according to the shape of each electrode, and the other forming methods are the same as the conventional one. It's exactly the same. Next, after recess etching is performed, a gate electrode (5) is formed at a predetermined position by a lift-off method. At this time, source electrode (8), drain electrode (4)
) is different from the conventional one, but since each electrode channel is always parallel, it can be formed by the same method as the conventional one by simply changing the photomask. Next, after forming a dielectric passivation film (for example, Si 3 N 4 , 81ON film, etc.) (6) to protect each electrode, predetermined positions of the passivation M (6) are etched using back-at-hydrofluoric acid, RIE, etc. After that, gold plating is formed. Next, the back surface of the GLAS semi-insulating substrate (1) is polished and etched to a predetermined thickness, and a back electrode (8) is deposited on that surface or Vi
After the aHole process, gold plating is formed.
第２図（ａ１部分ではソース電極（８）の給電側、ドレ
イン電極（４）の先端部であり、ソース電極チャネル部
（３ａ）は広く、ドレイン電極チャネル部（４ａ）は狭
くなる。第２図（ｂ１部分では第２図（ａｌとは反対に
なり、ソース電極チャネル部（３ａ）が狭く、ドレイン
電極チャネル部（４ａ）が広くなる。FIG. 2 (portion a1 is the power supply side of the source electrode (8) and the tip of the drain electrode (4), where the source electrode channel portion (3a) is wide and the drain electrode channel portion (4a) is narrow. In the figure (b1 part), it is opposite to the figure 2 (al), and the source electrode channel part (3a) is narrow and the drain electrode channel part (4a) is wide.
従来ものと同様に素子を動作させ素子にドレイン電流が
流れるが、各電極チャネルの先端部は電流値が小さく電
極が狭く、また給電部側では電流値が大きく電極が広い
ので、チャネル内の電流密度は等しくなる。As with conventional devices, the device operates and drain current flows through the device, but at the tip of each electrode channel the current value is small and the electrode is narrow, and on the power feeding side the current value is large and the electrode is wide, so the current inside the channel is The densities will be equal.
したがって、従来ものに比べ大きい電流が流せるため、
高出力の素子をチップサイズを小さく作成できる。Therefore, a larger current can flow than conventional ones,
High-output devices can be created with a small chip size.
なお、上記実施例ではゲート電極（６）が６本の場合に
ついて説明したが、ソース、ドレインゲートの数は各１
つ以上複数個でもよく、−また、ソースドレイン電極の
形状はチャネルの先端部が給電側に比べ狭ければよく、
比率、及び形状は変えても上記実施例と同様の効果を奏
する。In the above embodiment, the case where there are six gate electrodes (6) was explained, but the number of source and drain gates is one each.
-Also, the shape of the source-drain electrode may be such that the tip of the channel is narrower than the power supply side.
Even if the ratio and shape are changed, the same effects as in the above embodiment can be obtained.
以上のようＫこの発明によれば、写真製版のマスクハタ
ーンの変更だけでソース電極、ドレイン電極のチャネル
部の形状を先端部を狭く、給電側を広くするようにした
ので、チャネル内の電流密度が小さく、かつ均一にでき
るためチップサイズを大きくすることなしに、しかも従
来と同様のプロセスでドレイン電流を大きくできるため
、容易に高出力ＧａＡｓＦＥＴ半導体装置が得られる効
果がある。As described above, according to the present invention, the shapes of the channel portions of the source and drain electrodes are made narrower at the tips and wider at the power supply side by simply changing the photolithography mask pattern, so that the current density within the channel is reduced. Since it can be made small and uniform, the drain current can be increased without increasing the chip size and in the same process as in the past, which has the effect of easily obtaining a high-output GaAsFET semiconductor device.
第１図はこの発明の一実施例によるＧａＡｓ半導体半導
体手直図、第２図ｔａ）は第１図のＡ−Ａ線における部
分断面図、第２図（１）ｌは第１図Ｂ−Ｂ線における部
分断面図、第３図（ａｌ（ｂｌは従来のＧａＡｓ牛導体
装置の主要製造段階における断面図、第４図は従来のＧ
ａＡｓＦＥＴの平面図である。
図において、（１）は半絶縁性ＧａＡｓ基板、（２）は
活性層、（３ａ） 、 （３ｂ）はソース電極チャネル
部及びバット部、（４ａ） 、 Ｃ４ｂ）はドレイン電
極チャネル部及びバット部、（５ａ） 、 （５ｂ）は
ゲート電極チャネル部及ヒバット部、（６）はパッシベ
ーション保護１１、ｆｆ）は金めつき、（８）は裏面電
極を示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a schematic diagram of a GaAs semiconductor according to an embodiment of the present invention, FIG. 2 (ta) is a partial sectional view taken along line A-A in FIG. 1, and FIG. Partial cross-sectional view taken along line B, FIG.
FIG. 2 is a plan view of aAsFET. In the figure, (1) is a semi-insulating GaAs substrate, (2) is an active layer, (3a) and (3b) are a source electrode channel part and a butt part, and (4a) and C4b) are a drain electrode channel part and a butt part. , (5a) and (5b) are the gate electrode channel part and Hibat part, (6) is the passivation protection 11, ff) is gold plating, and (8) is the back electrode. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
法にて形成するＧａＡｓＦＥＴのソース、ドレイン電極
において、各電極チャネル部の先端の電極を幅広く、給
電部の電極の幅を狭くしたことを特徴とするＧａＡｓ半
導体装置の製造方法。In the source and drain electrodes of a GaAsFET formed by a lift-off method on an active layer formed on a GaAs semiconductor substrate, the electrode at the tip of each electrode channel part is made wider, and the width of the electrode in the power supply part is made narrower. A method for manufacturing a GaAs semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63257772A JPH02102546A (en) | 1988-10-12 | 1988-10-12 | Manufacture of gaas semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63257772A JPH02102546A (en) | 1988-10-12 | 1988-10-12 | Manufacture of gaas semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102546A true JPH02102546A (en) | 1990-04-16 |
Family
ID=17310888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63257772A Pending JPH02102546A (en) | 1988-10-12 | 1988-10-12 | Manufacture of gaas semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102546A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313083A (en) * | 1988-12-16 | 1994-05-17 | Raytheon Company | R.F. switching circuits |
| US6297787B1 (en) | 1996-01-11 | 2001-10-02 | Fourie, Inc. | Display device |
| JP2008205451A (en) * | 2007-01-25 | 2008-09-04 | Toppan Printing Co Ltd | Thin-film transistor array and method of manufacturing the same |
| JP2012023212A (en) * | 2010-07-14 | 2012-02-02 | Sumitomo Electric Ind Ltd | Semiconductor device |
| EP2629332A3 (en) * | 2012-02-17 | 2014-07-30 | International Rectifier Corporation | Transistor having increased breakdown voltage |
| US9070755B2 (en) | 2012-02-17 | 2015-06-30 | International Rectifier Corporation | Transistor having elevated drain finger termination |
| DE102014113467A1 (en) * | 2014-09-18 | 2016-03-24 | Infineon Technologies Austria Ag | Metallization of a field effect power transistor |
-
1988
- 1988-10-12 JP JP63257772A patent/JPH02102546A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313083A (en) * | 1988-12-16 | 1994-05-17 | Raytheon Company | R.F. switching circuits |
| US6297787B1 (en) | 1996-01-11 | 2001-10-02 | Fourie, Inc. | Display device |
| JP2008205451A (en) * | 2007-01-25 | 2008-09-04 | Toppan Printing Co Ltd | Thin-film transistor array and method of manufacturing the same |
| JP2012023212A (en) * | 2010-07-14 | 2012-02-02 | Sumitomo Electric Ind Ltd | Semiconductor device |
| US9379231B2 (en) | 2012-02-17 | 2016-06-28 | Infineon Technologies Americas Corp. | Transistor having increased breakdown voltage |
| US9070755B2 (en) | 2012-02-17 | 2015-06-30 | International Rectifier Corporation | Transistor having elevated drain finger termination |
| EP2629332A3 (en) * | 2012-02-17 | 2014-07-30 | International Rectifier Corporation | Transistor having increased breakdown voltage |
| DE102014113467A1 (en) * | 2014-09-18 | 2016-03-24 | Infineon Technologies Austria Ag | Metallization of a field effect power transistor |
| CN105448966A (en) * | 2014-09-18 | 2016-03-30 | 英飞凌科技奥地利有限公司 | Metalization structure of field effect power transistor |
| US9356118B2 (en) | 2014-09-18 | 2016-05-31 | Infineon Technologies Austria Ag | Metalization of a field effect power transistor |
| US9570565B2 (en) | 2014-09-18 | 2017-02-14 | Infineon Technologies Austria Ag | Field effect power transistor metalization having a comb structure with contact fingers |
| CN105448966B (en) * | 2014-09-18 | 2019-09-13 | 英飞凌科技奥地利有限公司 | The metallization structure of fet power transistor |
| DE102014113467B4 (en) | 2014-09-18 | 2022-12-15 | Infineon Technologies Austria Ag | Metallization of a field effect power transistor |
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