JPH02101545A - Coverage test device - Google Patents

Abstract

PURPOSE:To facilitate discrimination by comparing storage information of an execution address in a tested device with the instruction of a source program and map information and deciding whether the instruction of the source program has been executed or not in a coverage-side CPU. CONSTITUTION:CPU 2 in the tested device sequentially reads and executes the programs of machine words in a memory 3. In a coverage test device 4A, an address read part 7 detects the addresses which CPU 2 executes and an address write part 6 writes that the addresses have been executed into the address storage part 7 corresponding to the addresses. In the device 4A, the source programs of the programs of the machine words which previously exist in the memory 3 of the device 1 are stored in the storage part 21, and map information are stored in a storage part 22. Coverage-side CPU 8 fetches an instruction sentence from the storage part 21, the address of the instruction sentence is read from the storage part 22, and whether the instruction sentence has been executed or not is displayed in a display part 10 with information of the storage part 7. The rate of all the executed instruction sentences and the instruction sentences which have not been executed is displayed 10.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a coverage test device that performs a coverage test of software of a device under test.

[Conventional technology]

FIG. 3 is a block connection diagram showing a conventional coverage test device.
is a memory, 4 is a coverage test device, 5 is an address read section of the coverage test device 4, 6 is an address write section, 7 is an address storage section, 8 is a coverage side microprocessor (hereinafter referred to as CPU), 9 is for display ink face,
1° is the display section. Next, the operation will be explained. In this conventional example, a coverage test is performed while a program under test is executed in real time. First, the CPU 2 in the device under test 1 uses the memory 3
Read and execute the machine language program written in . On the other hand, the coverage test device 4 uses the address reading section 5 to read the address being executed by the CPU 2, and the address writing section 6 reads the address being executed by the address writing section 6.
The address is written into the address storage section 7 corresponding to the address. The coverage-side CPU 8 in the coverage test device 4 displays executed addresses, non-executed addresses, and their respective ratios on a display unit through an ink face 9 for all addresses allocated to the memory 3 in the device under test 1. 10. Moreover, FIG. 4 is a block connection diagram showing another coverage test device using a conventional large-scale computer, and in the figure,
11 is a large computer, 12 is a simulation program storage section provided in the large computer 11, 13 is a human storage section,
14 is a CPU, 15 is a source program storage unit,
Other blocks that are the same as those shown in Figure 2 include:
The same reference numerals are given. The CPU 14 of this large-sized computer executes the following operations according to the procedure of the flowchart shown in FIG. 5 by the simulation program stored in the simulation program storage section 12. First, the instruction statement of the program under test stored in the source program storage unit 15 is retrieved (step 5T).
II). Step 5T12)
, the number of the instruction statement is stored in the hit storage unit 13 (step 5T13). After that, the instruction statement is simulated (Step 5T14), and then it is determined whether the instruction statement is the end or not (Step 5T15). If it is determined that it is not the end, the next instruction statement is extracted and the above operations are performed. repeat. On the other hand, when the command statement is the end, the CPU 14 displays the result of whether the command statement has been executed or not and the respective ratios on the display unit 10 through the display interface 9.

[Problem to be solved by the invention]

Conventional coverage test equipment is configured as described above, so from a hardware perspective, it is easy to see which addresses are executed and which are not executed for all addresses in memory, and the proportions of these. However, there were problems such as it was unclear which statement was executed in the source program. In addition, in the conventional coverage test device using the large computer 11, in order to perform simulation on the program,
In addition to not being able to perform tests while running the program under test in real time, there were other problems such as not being able to simulate all programs. This invention was made to solve the above-mentioned problems, and aims to provide a coverage test device that can perform a coverage test for each instruction statement of a source program while executing the program under test in real time. purpose.

[Means to solve the problem]

The coverage test device according to the present invention provides C
The address reading section detects the address being executed by the PU, and the address writing section writes the fact that the detected address has been executed into the address storage section corresponding to the address, while writing the source program of the device under test. is stored in the source program storage unit, and the instruction sentences constituting the source program are stored in the map storage unit as map information corresponding to the addresses, and the map information corresponding to the instruction sentences extracted from the source program and the address are stored in the map storage unit. By comparing the storage information of the execution address of the storage unit,
It is arranged to determine whether the coverage side CPU has executed the above statement.

[For use]

The coverage side CPU in this invention compares the storage information of the execution address stored in the address storage section with the source program and map information obtained from the source program storage section and the map storage section, and determines the instruction statement of the source program. It is determined by software whether or not the execution has been executed, and the result is displayed on a display unit or the like.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a device under test, 2 is a microprocessor (hereinafter referred to as CPU), 3 is a memory, 4A is a coverage test device, 5 is an address reading section, 6 is an address writing section, 7 is an address storage section, 8 9 is a coverage side CPU, 9 is a display interface, and 10 is a display unit, which are the same as those shown in the conventional device shown in FIG. Further, 2 is a source program storage unit, and 22 is a map storage unit, which are connected to the CPU on the coverage side. Next, the operation will be explained. CPU in the device under test 1
2 sequentially reads out the machine language program written in the memory 3. In the coverage test device 4A,
An address reading unit 5 detects the address being executed by the CPU 2, and an address writing unit 6 writes information that the address has been executed into an address storage unit 7 corresponding to the address. The above operation is the same as that of the conventional coverage test device 4. In this invention, following the above operation, the operation according to the flowchart shown in FIG. 2 is executed. Here, in the coverage test device 4A of the present invention, the source program that is the basis of the machine language program stored in the memory 3 of the device under test l is stored in advance in the source program storage unit 21, and the Map information indicating which address the command statement corresponds to is stored in the map storage unit 2.
It is stored in 2. Therefore, the coverage side CPtJ8 extracts one instruction statement from the source program storage section 21 according to a control program (not shown) in step 5.
TI), the address at which the instruction statement is stored is read from the information in the map storage section 22 (step 5T2). Further, in step 5, it is read together with the information in the address storage section 7 whether or not the read address has been executed.
T3), the result of whether or not the statement has been executed is displayed on the display unit 10 through the display interface 9 (Step 5T4). Subsequently, the command sentences are sequentially retrieved and the above operations are repeated (step 5T5), and finally the ratio of all executed command sentences to unexecuted command sentences is displayed on the display section 10 (step 5T6).

【Effect of the invention】

As described above, according to the present invention, the storage information of the execution address of the device under test written in the address storage section is compared with the source program instructions and map information obtained from the source program storage section and the map storage section. Since the CPU on the coverage side is configured to determine whether or not the statement of the source program has been executed, even though the program under test is being executed in real time, each statement is not executed. This has the effect of making it possible to easily determine whether or not all commands have been executed.

[Brief Description of the Drawings] Fig. 1 is a block connection diagram showing a coverage test device according to an embodiment of the present invention, Fig. 2 is an information processing flow chart showing the operation of the coverage test device of Fig. 1, and Fig. 3 4 is a block connection diagram showing a conventional coverage test device, and FIG. 5 is an information processing flowchart showing the operation of the coverage test device shown in FIG. 1 is the device under test, 2 is the microprocessor (CPU),
4A is a coverage test device, 5 is an address reading section, 6 is an address writing section, 7 is an address storage section, 8 is a coverage side microprocessor (coverage side CPU), 21 is a source program storage section, and 22 is a map storage section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation Figure 2

Claims (1)

[Claims] an address reading unit that reads an address being executed by a microprocessor of the device under test; an address writing unit that writes information that the read address has been executed to an address storage unit corresponding to the address; and the device under test. a source program storage section that stores a source program; a map storage section that stores instruction statements constituting the source program as address-corresponding map information; and a map storage section that stores the instruction statements corresponding to the addresses extracted from the source program and the map information corresponding to the instruction statements and the addresses. A coverage test device comprising: a coverage side microprocessor that determines whether or not the instruction statement has been executed by comparing the execution address with storage information of a storage unit.