JPH06208480A - System program simulation system - Google Patents

Abstract

PURPOSE:To reduce cost for the development and maintenance of a system program. CONSTITUTION:A false main storage 4 is provided with the same system program as that of a main storage area in a target system. A processor simulator 1 simulates the operation of a system program in the target system which includes also interruption processing to be executed at the time of receiving an I/O request and interruption information by executing the system program stored in the false main storage area 4. A false peripheral device 3 simulates the peripheral device operation of the target system within a previously determined range. A control device simulator 2 converts an I/O request outputted from the simulator 1 into an I/O instruction to be outputted to the device 3, outputs the converted instruction and outputs the completion information of I/O operation of the device 3 and attention information from the device 3 as an interruption to the simulator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation system, and more particularly to a system program simulation system in a large-scale computer system.

[0002]

2. Description of the Related Art Conventionally, the operation verification of a large-scale system program such as an operating system has generally been carried out on a computer system (target computer) on which the program is mounted. However, this method
In the case of a system program such as a large-scale computer, an expensive computer system must be occupied for inspection for a long period of time, resulting in enormous cost for development and maintenance, and a system program for a completely new computer system. In this case, there is a drawback that a time lag from completion of hardware to completion of a system program occurs because the inspection can be performed only after completion of the hardware.

Therefore, as a method developed to solve these problems, as described in detail in the specification of JP-A-62-14240, a target computer system (abbreviated as target system)) There is a method of simulating the operation of the processor of the target system at the machine instruction level on another computer system (abbreviated as simulator). In this method, the registers in the processor of the target system allocate a part of the main memory of the simulator, and the register access of the target system is replaced with the access to the main memory of the simulator. Similarly, the main memory of the target system is replaced with an access to the main memory inside the simulator. The simulator reads the machine instruction from the area corresponding to the main memory of the target system, interprets it as the instruction of the target system, and repeats the operation corresponding to this. Further, details of extensions of this method to enable simulation of a multiprocessor system are described in JP-A-63-226740 and JP-A-3-150641.

If the above system is used, it is possible to verify the operation of the system program for the target system on a system which is totally different from the target system. However, in this method, only the simulation of the processor and the main memory system can be performed, and the trial execution of the program using the peripheral device is impossible. Therefore, it is not possible to verify a program such as a virtual memory system in which a command of the main memory is once written to the secondary memory which is a kind of peripheral device, or the contents of the secondary memory are read into the main memory and executed. . In addition, it is impossible to verify a system program that accepts a command input from a terminal as represented by a TSS system. That is, with this method, it is impossible to verify a large-scale system program such as an operating system in which the control of peripheral devices has the most important function.

On the other hand, simulation methods for peripheral devices are disclosed in Japanese Patent Laid-Open Nos. 63-3348 and 1-159743.
It is described in detail in JP-A-3-67340. However, all of these methods specialize in the simulation of peripheral devices and assume that the functions of the computer such as the processor and main memory use a system equivalent to the target system. In many cases, the prices are about the same, and we cannot expect much reduction in development and maintenance costs. Furthermore, the above-described method of simulating only peripheral devices is suitable for verifying the operation of system programs for shortening the development period when adding new peripheral devices to an existing computer system, but it is not necessary This means that it cannot be used at all when the memory system or the interface between these computer main units and peripheral devices becomes new.

Next, the input / output method of the current computer system will be briefly described. The current computer system is shown in Fig. 7.
The one having a structure as shown in is general. When the processor P accesses the peripheral device D, it is executed by issuing an input / output command to the control device C.
There are various types of control devices, from a simple one such as a DMA controller to an input / output dedicated processor used in a general-purpose computer. In either case, the processor is designed to perform other processing while the controller is performing I / O to improve overall system throughput. Generally, there are two types of functions of the control device, one is to execute the input / output requested by the processor,
Notifying the processor of its completion. The other is to notify the processor of an event that has occurred in the peripheral device. Examples of this event include information input from the outside world such as an operator pressing a key, and changes in the state of peripheral devices. In any operation, the notification from the peripheral device to the processor is realized as a so-called interrupt, and the input / output data is passed through the main memory M accessible from both the processor and the control device. When the input / output command also becomes long, it is passed from the processor to the control unit via this main memory.

There are various peripheral devices handled by the control device, such as those used as storage devices such as magnetic disk devices and magnetic tape devices, and those used for exchanging information with operators such as consoles and terminals. Each of the peripheral devices operates within the two basic operation ranges of the control device, and the difference between the peripheral devices is that the type of input / output command and the meaning and amount of information to be exchanged are different.

[0008]

In the above-mentioned conventional simulation methods, only a part of the system program can be simulated, and trial execution of software that uses the entire system such as an operating system is not possible. There was a flaw.

It is an object of the present invention to provide a simulation method capable of economically executing a trial execution of software that uses the entire system such as an operating system in a short period of time.

[0010]

According to a first aspect of the present invention, in a system program simulation method in a computer system in which a processor and a peripheral control device for controlling a peripheral device operate in parallel, a system program operation in a target system to be simulated. Is provided on the computer different from the target system.

A second aspect of the present invention is a pseudo main storage unit having a system program identical to the system program in the main storage area of the target system, and the operation of the system program of the target system in the pseudo main storage. Processor simulator for simulating the interrupt processing when an input / output request and an interrupt notification are received by executing the system program in the area, and a pseudo peripheral for simulating the peripheral device operation of the target system within a predetermined range The device and the input / output request from the processor simulator are converted into an input / output instruction to the pseudo peripheral device and output to output the completion notification of the input / output operation of the pseudo peripheral device and the attention information from the pseudo peripheral device. As an interrupt to the processor simulator, the interrupt Characterized by comprising the simulation means comprising a control device simulator for performing.

[0012]

1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, 1 is a processor simulator, 2 is a control device simulator, 3 is a pseudo peripheral device, and 4 is a pseudo main memory. Although all of the numbers 1 to 3 are singular in this figure, they may have a plurality of configurations.

Next, the operation of each component will be described. The processor simulator simulates the operation of the processor of the target system at the hardware instruction level. The pseudo main memory uses a part of the main memory of the simulator that has the same function as the main memory of the target system, and the programs and data are placed in the pseudo main memory as if they were placed in the main memory in the target system. To be done. Normal instructions and address conversion processing that can be executed only by registers and main memory are possible if this processor simulator and pseudo main memory are provided.

However, the parallel execution of the processing by the processor and the input / output operation cannot be simulated only by the processor simulator and the pseudo main memory described above. Therefore, a control device simulator as shown in FIG. 1 is provided separately from the processor simulator.

The controller simulator simulates the operation of the input / output controller of the target system at the level of the input / output command from the processor. That is,
The control device simulator decodes the input / output command passed from the processor simulator and converts it into an input / output command to the corresponding pseudo peripheral device. This allows the input / output operation of the target system to be simulated.

The notification from the processor to the control device in the target system can be realized as a notification from the processor simulator to the control device simulator by using interprocess communication or the like. Notification in the opposite direction is realized in the same way. For the interrupt operation to the processor accompanying the I / O completion notification in the target system, the processor simulator periodically checks the I / O completion notification from the control unit simulator, and if there is a notification, simulates the interrupt processing. Simulation becomes possible. Also,
By using the pseudo main memory as a shared memory between the processor simulator and the control device simulator, it is possible to perform a simulation of data and input / output command passing between the processor and the control device of the target system via the main memory.

The pseudo peripheral device is a substitute for a peripheral device having the same function as that of the peripheral device of the target system. The pseudo peripheral device and the peripheral device of the target system must have essentially the same function, and the difference in access procedure is absorbed by the controller simulator. For example, when it is desired to simulate the disk device of the target system, a random access device having a storage device may be used as the pseudo peripheral device. If the disk capacity of the target system and the disk capacity of the simulator are different, the problem can be solved by allocating a plurality of disk devices of the simulator to one disk device of the target system and dispatching the area by the device simulator. Further, if it is desired to simulate the console of the target system, the peripheral device having the function of communicating with the operator may be used as the pseudo peripheral device. For example, a simulator terminal or Xwin
dow and the like satisfy this condition. If the control procedure of the console of the target system and the terminal of the simulator are different, it can be solved by converting the control procedure by the control device simulator.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

As shown in FIG. 1, the system program simulation method of the present invention is a processor simulator 1 for simulating the operation of a processor of a target system.
And a pseudo peripheral device 3 for simulating the peripheral device operation of the target system, and an input / output request from the processor simulator 1 is converted into an input / output instruction to the pseudo peripheral device 3 to notify the completion of the input / output operation and the pseudo peripheral device 3 The controller simulator 2 for notifying the processor shifter 1 of the attention from the processor as an interrupt, and the pseudo main memory 4 simulating the main memory operation of the target system accessible from the processor simulator 1 and the controller simulator 2. . Although only one processor simulator, control device simulator, and pseudo peripheral device are described in this figure for simplification, a plurality of processor simulators, control device simulators, and pseudo peripheral devices may be described.

FIG. 2 is a flow chart showing the operation of the processor simulator 1. First, in the initialization step 11, various registers that the processor simulator 1 has are initialized as in the case where the processor of the target system is started, and the boot loader is set to the pseudo main memory 4.
To load. Then, in the instruction fetch step 12,
The instruction word is fetched from the pseudo main memory area 4, and in the instruction discrimination step 13, the instruction word fetched in the instruction fetch step 12 is discriminated. If the result of determination is a normal instruction that can be executed only with registers and main memory, then normal instruction execution step 1
In step 4, the instruction execution of the processor of the target system is simulated, and the program counter increment step 17
Then, the program counter is incremented by 1, and the notification check step 1
At 8, it is determined whether or not the input / output completion notification or attention notification from the control device simulator 2 has been received.
If no notification is detected as a result of the judgment,
Return to instruction fetter step 12. If any of the notifications is detected as a result of the determination, the interrupt processing means 19 is called, and after the interrupt processing is completed, the instruction fetch step 12
Return to.

When an input / output instruction is detected in the instruction determining step 13, control is passed to the input / output instruction executing means 15,
When it returns, it proceeds to the program counter 17. When the interrupt return instruction is detected in the instruction determination step 13, the control is passed to the interrupt return instruction executing means 16, and when returning, the process proceeds to the notification inspection step 18.

FIG. 3 is a flow chart showing the processing of the input / output instruction executing means 15. In the peripheral device determination step 151, the corresponding control device simulator 2 and pseudo peripheral device 3 are determined from the specified peripheral device information, and in the input / output request notification step 152, to the control device simulator 2 determined in the peripheral device determination step 151. Notify I / O requests.

FIG. 4 is a flow chart showing the processing of the interrupt processing means 19. In the context saving step 191,
Register information of the target system processor held in the processor simulator 1 at that time,
It is saved in the save area on the pseudo main memory 4 according to the specifications of the processor of the target system, and in the interrupt vector loading step 192, the first context at the time of the interrupt occurrence is loaded into the register according to the specifications of the target system.

FIG. 5 is a flow chart showing the processing of the interrupt return instruction executing means 16. Context restoration step 161
Then, the information is restored from the save area on the pseudo main memory 4 to the register area inside the processor simulator 1.

FIG. 6 is a flow chart showing the processing of the controller simulator 2. In the event inspection step 21, the control device simulator 2 waits for an input / output request from the processor simulator 1 or an attention from the pseudo peripheral device 3. When the input / output request from the processor simulator 1 is detected, in the input / output processing step 22,
Input / output to / from the pseudo peripheral device 3 corresponding to the designated peripheral device is performed, and in the input / output completion notification step 23, an input / output completion notification is sent to the processor simulator 1 that issued the request, and the process returns to the event inspection step 21 again. . When the attention from the pseudo peripheral device 3 is detected in the event inspection step 21, the notification destination determining step 24 determines the notification destination processor according to the procedure in the target system, and the attention notification step 25 determines the notification destination determining step 24. An attention notification is sent to the processor simulator 1 that simulates the determined processor, and the process returns to the event inspection step 21 again.

According to the present invention, if a workstation or the like having high performance for the price is used as a simulator, trial execution of a system program for an expensive computer system such as a large-scale computer can be carried out by an inexpensive system. , It is possible to reduce the cost of system program development and maintenance. The trial execution by this simulation has a problem that the timing is different from that of an actual system, and it is difficult to trial execute the control function related to time or the control function of the peripheral device in which delicate timing is a problem. However, in an ordinary system program, only a half or less of these simulations are difficult to test-execute, and the fact that a majority of the parts can be trial-executed by an inexpensive system has a great effect.

Furthermore, in actual computer system development, it generally takes time to determine the specifications, and the simulator of the present invention, which is mainly software, easily changes the specifications of the computer system. There is also an effect that can be dealt with.

[0029]

As described above, according to the system program simulation method of the present invention, each function of a system program such as an operating system of a target machine can be simulated by software on another computer. This has the effect of reducing the cost of program development and maintenance. Furthermore, the system program can be trial-executed by the simulator before the hardware of the new target system is completed, which has the effect of shortening the total development period from the completion of the hardware to the completion of the system program.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the processor simulator 1 of FIG.

FIG. 3 is a flow chart showing a process of an input / output instruction executing means 15 of FIG.

FIG. 4 is a flowchart showing the processing of the interrupt processing means 19 of FIG.

5 is a flowchart showing the processing of the interrupt return instruction execution means 16 of FIG.

FIG. 6 is a flowchart showing the processing of the control device simulator 2 of FIG.

FIG. 7 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 1 Processor Simulator 2 Controller Simulator 3 Pseudo Peripheral Device 4 Pseudo Main Memory P Processor C Control Device D Peripheral Device M Main Memory

Claims (2)

[Claims] 1. In a system program simulation method in a computer system in which a processor and a peripheral controller for controlling a peripheral device operate in parallel, a system program operation in a target system to be simulated is performed on a computer different from that of the target system. A system program simulation method characterized by comprising a simulation means for simulating with. 2. A pseudo main memory unit having the same system program as the system program on the main memory area of the target system, and an operation of the system program of the target system, the system program of the pseudo main memory area A processor simulator that simulates the interrupt processing when an input / output request and an interrupt notification are received by executing, a pseudo peripheral device that simulates the peripheral device operation of the target system within a predetermined range, and the processor simulator The input / output request from the pseudo peripheral device is converted into an input / output instruction to the pseudo peripheral device and output, and the completion notification of the input / output operation of the pseudo peripheral device and the attention information from the pseudo peripheral device are used as an interrupt to the processor simulator. A control device stain that performs the interrupt notification 2. The system program simulation method according to claim 1, further comprising the simulation means including a simulator.