JP2011123676A - Information processing apparatus and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus that prevents a simulation speed from being reduced while holding a flexibility of specifications of external interfaces of the respective simulators, when performing simulation by making a plurality of simulators cooperate with one another. <P>SOLUTION: The information processing apparatus includes a simulator connection which, when performing the simulation by making the plurality of simulators cooperate with one another, performs signal transmission processing between the simulators. The simulator connection stores corresponding information of signal identification information inherently allocated to each simulator and the simulator connection respectively and information about a transmission target simulator having each signal as an input signal in each signal to be used in each simulator. The simulator connection specifies the transmission target simulator of a signal output from any one simulator on the basis of these pieces of information and notifies the signal in timing corresponding to the transmission target simulator. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a control method thereof.

  In order to verify the operation of control software incorporated in an image forming apparatus or the like before actually incorporating it into an actual machine, it is necessary to execute a simulation using an information processing apparatus such as a computer. In order to realize such a simulation, one simulator may be constructed by combining a plurality of simulators each simulating different functions and operating them in cooperation.

  In order to execute simulations by operating different simulators in cooperation in this way, it is necessary to link changes in signals handled in each simulator with each other. For example, when a simulator that simulates the operation of a CPU in a certain machine and a mechanical simulator that simulates a unit to be controlled by the CPU are combined, a control signal transmitted between the simulators is an example. . Specifically, when the control signal in the CPU simulator changes to a signal value instructing driving of the main motor, it is necessary to change the signal value of the control signal in the mechanical simulator to a value indicating driving of the main motor. Thereby, the mechanical simulator executes a simulation for changing the driving state of the motor in accordance with the change in the signal value of the control signal.

  As a technique for exchanging signals between a plurality of simulators in a simulation system that combines a plurality of different simulators and operates them in cooperation with each other, for example, techniques disclosed in Patent Documents 1 and 2 have been proposed. In Patent Document 1, a common data area that can be accessed by a plurality of simulators is provided in the integrated simulation system, and signals are exchanged between the plurality of simulators via the common data area, and the simulation times of the simulators are synchronized. A method has been proposed.

  Patent Document 2 proposes a method in which a relation between an event and an action is defined in advance, and a simulator connecting unit that connects a plurality of simulators instructs each simulator based on the definition. In response to the event notification, the simulator connection unit instructs the simulator defined in the definition information to execute an action defined in relation to the event notification. For example, by defining an event as a change in signal value in one simulator and an action as a change in signal value in another simulator, the change in signal value can be linked between different simulators. It can be operated.

JP 2006-350549 A Japanese Patent Laid-Open No. 11-327956

  However, the above-described conventional technology has the following problems. For example, in both methods of Patent Documents 1 and 2, in order to connect and link a plurality of simulators, it is necessary to match the specifications of the external interface for connection with other simulators in each simulator. For this reason, when the specifications of the external interface in each simulator are different, it is difficult to connect and link a plurality of simulators.

  Furthermore, in the method of Patent Document 2, each time the simulator connection unit receives information indicating a change in signal from any of the simulators, the simulator connection unit Irrespectively, the received information is transmitted. In this case, if information is transmitted even when the receiving side simulator does not refer to the signal, the load on the receiving side simulator may increase and the simulation speed may decrease.

  The present invention has been made in view of the above-described problems, and prevents a decrease in simulation speed while maintaining the degree of freedom of the specifications of the external interface of each simulator when simulating a plurality of simulators in cooperation. An object of the present invention is to provide an information processing apparatus.

  The present invention can be realized as an information processing apparatus, for example. The information processing apparatus includes a plurality of simulators that respectively simulate the operations of a plurality of components included in the simulation target apparatus, and a connection unit that interconnects the plurality of simulators and transmits signals between the plurality of simulators, An information processing apparatus that simulates the operation of a simulation target apparatus by operating a plurality of simulators in cooperation with each other, and a connection unit identifies each signal and a signal output by simulation from each connected simulator And a plurality of simulators for holding signal information including first signal identification information uniquely assigned in each simulator and second signal identification information uniquely assigned in connection means for identifying each signal From either of these, the signal with the first signal identification information added Is newly output, the acquisition means for acquiring the second signal identification information for identifying the output signal from the signal information held in the holding means, and among the plurality of simulators A specifying means for specifying a transmission target simulator identified by the second signal identification information using management information held in advance, and a new signal held in the holding means for the specified simulator is output. Updating means for updating to the updated signal, determination means for determining whether or not to immediately notify the updated signal from the timing updated by the updating means to the identified simulator, and immediately for the updated signal If it is determined to notify, the updated signal is notified, and if it is determined not to immediately notify the updated signal, the specified simulation is performed. In over data that can handle timing and characterized in that it comprises a notifying means for notifying the updated signal.

  According to the present invention, for example, when a simulation is performed in cooperation with a plurality of simulators, it is possible to provide an information processing apparatus that prevents a decrease in simulation speed while maintaining the degree of freedom of the specifications of the external interface of each simulator.

1 is an example of a functional block diagram of a simulation system 100 according to a first embodiment. It is an example of a functional block diagram of information processor 200 with which simulation system 100 concerning a 1st embodiment is mounted. 1 is an example of a schematic cross-sectional view relating to an image forming apparatus 300 to be simulated by the simulation system 100 according to the first embodiment. 2 is an example of a functional block diagram relating to an image forming apparatus 300 to be simulated by the simulation system 100 according to the first embodiment. FIG. It is a figure which shows an example of the wiring definition information 124 which concerns on 1st Embodiment. It is a figure which shows an example of the notification content to the outside in the CPU simulator 102 which concerns on 1st Embodiment, and the content of the instruction | indication from the outside. It is a figure which shows an example of the notification content to the outside in the paper conveyance simulator 103 which concerns on 1st Embodiment, and the content of the instruction | indication from the outside. FIG. 10 is a diagram illustrating an example of a screen display of a simulation result by the paper conveyance simulator 103 according to the first embodiment. It is a figure which shows an example of the notification content to the outside in the process unit simulator 104 and image simulator 105 which concern on 1st Embodiment, and the content of the instruction | indication from the outside. It is a figure which shows an example of the content of the signal management information 118 which concerns on 1st Embodiment. It is a figure which shows an example of the content of the signal information 113-116 corresponding to each simulator which concerns on 1st Embodiment. It is a flowchart which shows the procedure of the signal transmission process by the signal management part 117 which concerns on 1st Embodiment. It is a flowchart which shows the procedure of the signal transmission process by each simulator I / F107-110 which concerns on 1st Embodiment. It is a flowchart which shows the process sequence with respect to the lead event by simulator I / F107 for CPU simulator 102 which concerns on 1st Embodiment. It is a figure which shows an example of the content of the virtual memory information contained in the signal information 113 which the simulator I / F107 which concerns on 2nd Embodiment hold | maintains. It is a flowchart which shows the process sequence with respect to the read event by simulator I / F107 for CPU simulator 102 which concerns on 2nd Embodiment. It is a figure which shows the modification of the signal management information 118 shown in FIG.

  An embodiment of the present invention is shown below. The embodiments described below will help to understand various concepts such as the superordinate concept, intermediate concept and subordinate concept of the present invention. Further, the technical scope of the present invention is determined by the scope of the claims, and is not limited by the following embodiments.

[First Embodiment]
<Configuration of Information Processing Device 200>
The first embodiment of the present invention will be described below with reference to FIGS. First, a configuration example of the information processing apparatus 200 according to the present embodiment will be described with reference to FIG. The information processing apparatus 200 can be realized as a computer system such as a personal computer or a workstation. The simulation system according to the present invention is realized as a program executed by the information processing apparatus 200.

  The central processing unit (CPU 201) accesses each unit (202 to 209) in the information processing apparatus 200 via the bus 220 and controls their operation. The ROM 202 is a read-only memory that can be accessed from the CPU 201 via the bus 220. The RAM 203 is a readable / writable memory. The input interface 204 receives input from the user via an input device 205 such as a keyboard, a mouse, or a tablet. The output interface 206 is an interface for displaying and outputting data to the output device 207. The output device 207 includes a display device 207a such as a CRT or LCD, and an output device 207b such as a printer or plotter. The external storage device interface 208 is an interface for inputting / outputting data to / from the external storage device 210. In addition to the hard disk (HDD) 209, the external storage device 210 may be an FD, CD-ROM, MO, CF, or the like. The external storage device 210 including the HDD 209 stores a processing program 209a for realizing each function of the simulation system according to the present invention on the information processing device 200. The external storage device 210 further stores various setting data 209b for simulation including information on the device to be simulated, and control software (firmware) 209c that is actually incorporated into the device to be simulated.

  In the present embodiment, when a simulation is executed in the information processing apparatus 200, a processing program 209a, various setting data 209b, and firmware 209c are loaded from the external storage device 210 to the RAM 203. The CPU 201 executes a simulation described later using these data loaded in the RAM 203.

<Configuration of Image Forming Apparatus 300 to be Simulated>
Next, a schematic configuration of an electrophotographic image forming apparatus 300 to be simulated by the simulation system according to the present embodiment will be described with reference to FIG. The image forming apparatus 300 includes four photosensitive drums 303a, 303b, 303c, and 303d (303a to 303d) as image carriers on which toner images of colors of yellow, magenta, cyan, and black are formed. The photosensitive drums 303a to 303d are arranged in series, and primary chargers 304a to 304d, developing devices 306a to 306d, and cleaning devices 307a to 307d are arranged around the photosensitive drums 303a to 303d, respectively. Further, exposure devices 305a to 305d are arranged above the respective photosensitive drums 303a to 303d. On the other hand, an intermediate transfer belt (ITB) 301 is disposed below each of the photosensitive drums 303a to 303d.

  The ITB 301 is stretched around the rollers 308, 309, and 310 that drive the ITB, and rotates in the direction of the arrow at substantially the same speed as the photosensitive drums 303a to 303d by driving these rollers. The ITB 301 is sandwiched between the photosensitive drums 303a to 303d and the primary transfer rollers 302a to 302d. In addition, the image forming apparatus 300 includes a paper feed conveyance mechanism including a paper storage cassette 312, a pickup roller 313, a registration conveyance roller 314, and a registration sensor 315. Further, the image forming apparatus 300 includes a print transfer mechanism including a secondary transfer roller 316 in contact with the ITB 301 and a fixing device 317, a discharge roller 318, and a discharge tray including a discharge tray 319 downstream of the registration transfer roller 314. A paper transport mechanism is provided.

  Next, the function of each block related to image formation of the image forming apparatus 300 will be described with reference to FIG. The image forming apparatus 300 includes a printer main control unit 401 that controls an image forming function and a video controller 402 that generates image data. The printer main control unit 401 includes a CPU, a ROM, a RAM, a gate element, and the like. The main control by the printer main control unit 401 is realized by the CPU reading out control software (firmware) stored in the ROM inside the printer main control unit 401 to the RAM and executing it.

  The image forming apparatus 300 includes various actuators such as a main motor 404, a pickup solenoid 406, a registration clutch 407, and a fixing paper discharge motor 403. Further, the image forming apparatus 300 includes a process unit 405 in addition to the fixing device 317 shown in FIG. Here, the fixing paper discharge motor 403 is a driving source of the fixing roller 410 and the paper discharge roller 318 of the fixing device 317. On the other hand, the main motor 404 is a drive source for the pickup roller 313, the registration conveyance roller 314, the secondary transfer roller 316, and the mechanical mechanism 415 of the process unit 405. The printer main control unit 401 controls driving of the fixing paper discharge motor 403 and the main motor 404 and controls operations of the pickup solenoid 406 and the registration clutch 407. As a result, the printer main control unit 401 controls the sheet transport operation through the operations of various rollers.

  The fixing device 317 includes a main heater 408 that heats the fixing roller 410, a sub heater 409, and a fixing roller 410 that heats and pressurizes the sheet on which the toner image formed on the ITB 301 is transferred. The fixing device 317 further includes a plurality of temperature sensors 411 and 412 (a central temperature sensor 411 and an end temperature sensor 412) that detect the surface temperature of the fixing roller 410.

  The process unit 405 includes an optical unit 413, a high-pressure unit 414, and a mechanical mechanism 415. The optical unit 413 is provided in each of the photosensitive drums 303a to 303d, the primary chargers 304a to 304d, the developing devices 306a to 306d, the exposure devices 305a to 305d, the ITB301, the primary transfer rollers 302a to 302d, and the secondary transfer roller 316. Generates optical action. On the other hand, the high voltage unit 414 generates an electrical action in each of these devices. The mechanical mechanism 415 gives a mechanical drive to each of these devices.

<Operation of Image Forming Apparatus 300>
Next, a schematic procedure for image formation in the image forming apparatus 300 will be described. When image formation is performed in the image forming apparatus 300, the printer main control unit 401 uses a vertical synchronization signal (/ TOP signal) that is a synchronization signal in the sub-scanning direction (paper transport direction) of the image in the optical unit 413 at a predetermined timing. To output to the video controller 402. Further, the printer main control unit 401 outputs a horizontal synchronization signal (/ BD signal), which is a synchronization signal in the main scanning direction of the image in the optical unit 413, to the video controller 402 at a predetermined timing. Based on these synchronization signals, the video controller 402 outputs an image signal to the printer main control unit 401. For example, the video controller 402 outputs an image signal of each color to the printer main control unit 401 at a predetermined timing after outputting the / TOP signal on the basis of the / TOP signal. The printer main control unit 401 controls a process unit 405 in synchronization with the / TOP signal to sequentially execute known image forming processes such as exposure, development, and primary transfer. As a result, a toner image is formed on the ITB 301.

  The printer main control unit 401 further controls the conveyance of the paper 311 by controlling each actuator. Specifically, the printer main control unit 401 temporarily stops the paper 311 at the timing when it detects that the leading edge of the paper has reached the registration sensor 315 after feeding the paper from the paper storage cassette 312. The printer main control unit 401 starts feeding the paper 311 stopped at the position of the registration sensor 315 to the secondary transfer unit at a predetermined timing based on the / TOP signal. As a result, the printer main control unit 401 transfers the toner image formed on the ITB 301 to a predetermined position on the paper 311 in the secondary transfer unit. Further, the printer main control unit 401 controls the two heaters 408 and 409 based on the temperature detection results by the temperature sensors 411 and 412, thereby controlling the temperature of the fixing roller 410 to a predetermined temperature for fixing. After that, the printer main control unit 401 controls the paper 311 on which the toner image is secondarily transferred to the fixing device 317 to fix the toner image on the paper 311.

  As described below, the simulation system according to the present embodiment is referred to as a “target CPU” in order to distinguish it from the CPU of the printer main control unit 401 in the image forming apparatus 300 (hereinafter, the CPU 201 of the information processing apparatus 200). .) Is a simulation system for verifying and evaluating the operation of the firmware executed. Specifically, the simulation system simulates on the information processing apparatus 200 the execution of instructions by the firmware, the conveyance of paper according to the execution of the instructions, and the operation of each load for image formation. The simulation system also simulates the operation of returning a feedback signal from each load to the firmware, as in the actual machine.

<Configuration of Simulation System 100>
Next, an example of a functional configuration of the simulation system 100 realized by the information processing apparatus 200 will be described with reference to FIG. In the present embodiment, the simulation system 100 includes a CPU simulator 102, a paper transport simulator 103, a process unit simulator 104, and an image simulator 105 as a plurality of simulators that simulate each unit of the image forming apparatus 300. Furthermore, the simulation system 100 includes a simulator connection unit 101 that connects the plurality of simulators and operates them in cooperation.

  In the present embodiment, the simulation system 100 includes individual simulators corresponding to the components of the image forming apparatus 300 as described above. This is because the purpose and implementation method of the simulator are different for each component of the image forming apparatus 300. Such a configuration is reasonable as a simulator for verifying and evaluating the operation of the firmware of the image forming apparatus 300 from any viewpoint of creation, operation, and maintenance.

  The simulator connection unit 101 has a role of operating a plurality of simulators corresponding to different functions as a single simulation system on the information processing apparatus 200 by operating them in cooperation. The simulator connection unit 101 includes a core unit 106 and an I / F to which each simulator is connected (a simulator I / F 107 for the CPU simulator 102, a simulator I / F 108 for the paper transport simulator 103, and a simulator I for the process unit simulator 104). / F109, and a simulator I / F110) for the image simulator 105.

  The core unit 106 includes a synchronization module 111 and a wiring module 112. The wiring module 112 includes a signal management unit 117 and holds signal management information 118 managed by the signal management unit 117. Moreover, simulator I / F107-110 hold | maintains the signal information 113-116 corresponding to each simulator, respectively. The signal management information 118 and the signal information 113 to 116 will be described later.

  In the present embodiment, when the simulation is executed, the CPU simulator 102, the paper transport simulator 103, the process unit simulator 104, and the image simulator 105 are executed as independent processes on the information processing apparatus 200. The plurality of simulators have external I / Fs 119 to 122 for connecting to other simulators via the simulator connection unit 101, and these may have different specifications. In the present embodiment, the simulator connection unit 101 has a multi-thread configuration. For this reason, the processing by the core unit 106 and the simulator I / Fs 107 to 110 in the simulator connection unit 101 can be executed in parallel as separate threads in the information processing apparatus 200.

  The setting data 209b stored in the external storage device 210 includes simulator configuration definition information 123 and wiring definition information 124 that are set in advance by the user as definition information necessary for execution of simulation in the simulation system 100. . The simulator configuration definition information 123 is definition information related to the configuration of a plurality of simulators (102 to 105) connected to the simulator connection unit 101. The wiring definition information 124 defines wiring information between simulators of signal lines used for transmitting signals between simulators connected to the simulator connection unit 101.

<Operation of Simulation System 100>
Next, the operation of each part of the simulation system 100 executed in the information processing apparatus 200 will be described. Hereinafter, functions and operations of the simulator connection unit 101, the CPU simulator 102, the paper transport simulator 103, the process unit simulator 104, and the image simulator 105 will be described in order.

(Simulator connection unit 101)
The simulator connection unit 101 connects various simulators to each other and operates them in cooperation as one simulation system 100. As a result, the information processing apparatus 200 simulates the operation of the image forming apparatus 300 to be simulated. In the simulator connection unit 101, the core unit 106 performs basic control regarding data transmission processing and synchronization processing among the CPU simulator 102, the paper transport simulator 103, the process unit simulator 104, and the image simulator 105. The core unit 106 implements these controls using the synchronization module 111 and the wiring module 112. The simulator I / Fs 107 to 110 are interfaces for connecting the core unit 106 and each simulator. Specifically, each of the simulator I / Fs 107 to 110 performs connection processing with the simulator to be connected that conforms to the specifications of the external I / F of the simulator. On the other hand, each of the simulator I / Fs 107 to 110 performs connection processing with the core unit 106 based on the specifications common to all the simulator I / Fs.

  These programs for the simulator I / F are stored in advance in the external storage device 210 as a simulator I / F library included in the processing program 209a. This simulator I / F library is prepared for each simulator constituting the simulation system 100 and is provided as a dynamic link library (DLL). Thus, by preparing a simulator I / F library corresponding to a simulator connected to the simulator connection unit 101, a new simulator can be incorporated into the simulation system 100 as necessary.

  The synchronization module 111 executes control to synchronize the operation of each simulator at a unit time interval on the simulation system 100 based on information (interval notification) notified from the simulator I / Fs 107 to 110. Here, in the present embodiment, the plurality of simulators 102 to 105 included in the simulation system 100 operate so as to execute a predetermined simulation for each unit time on the simulation under time management unique to each simulator. . That is, each simulator operates in its own virtual time. For example, in the paper transport simulator, when a paper transport state at a speed of 200 mm / second in the image forming apparatus is simulated, the virtual time is advanced by 1 second with respect to the paper transport simulation for 200 mm. In this case, the progress of the virtual time in the paper transport simulator is not related to the processing time of the computer system required for the paper movement simulation for 200 mm. That is, the progress of the virtual time is determined by the relationship between the motion of the simulation object in the real world and the time required for the motion. The processing time required for executing the simulation for the same virtual time differs for each simulator. For this reason, in order to operate these simulators in cooperation as one simulation system, each simulator performs synchronization processing with the outside every unit time, and the synchronization module 111 sets the virtual time of each simulator to a common virtual time. Execute the process to synchronize. Note that the synchronization processing by the synchronization module 111 can be realized by a known method, and thus detailed description thereof is omitted.

  The wiring module 112 controls signal value transmission processing among a plurality of simulators in cooperation with the simulator I / Fs 107 to 110 on the basis of preset wiring definition information 124. Here, a signal (virtual signal) transmitted between the simulators is defined in advance as the wiring definition information 124 included in the setting data 209 b stored in the external storage device 210. Hereinafter, an example of the definition format and definition contents in the wiring definition information 124 will be described with reference to the table shown in FIG.

  In the wiring definition information 124, as shown in FIG. 5, in addition to the virtual signal name, data size, signal type, and initial value, signal identification information necessary for identifying (specifying) the signal in each simulator , I / O, logic, and the like. In FIG. 5, “virtual signal name” is defined as a character string indicating a signal name. However, the character string is converted into a unique numerical value (signal ID) for each signal in the wiring module 112 and handled. “Data size” represents the data size of each signal in the number of bits. “Signal type” represents the type of each signal, B is defined as bit information, D is defined as digital multi-value information, and A is defined as analog (floating point) information. The “initial value” represents an initial value of each signal at the start of the simulation. Here, “0x” used in each numerical expression in FIG. 5 indicates a hexadecimal notation and conforms to the C language format. Other numerical expressions indicate decimal notation. Each definition format in the present embodiment can use only decimal numbers and hexadecimal numbers. Even when “0” is added to the beginning of a numerical character string, the definition is not a octal number but a decimal number. Represents.

  The definition of the signal identification information for identifying each virtual signal is different for each simulator as shown in FIG. For example, “address” and “bit” in the CPU simulator 102, “type” and “individual ID (ID for each type)” in the paper transport simulator 103, “information ID” in the process unit simulator 104, and “function” in the image simulator 105 It is defined using “ID”.

  In the “address” in the CPU simulator 102, a virtual address in the CPU simulator 102 (that is, an address on the address map in the target CPU) is defined. “Bit” is a definition that is valid only when the signal type is B (bit information), and the bit position in the address is defined. For “type” and “individual ID” in the paper transport simulator 103, information set in advance as definition information regarding the model of each component in the paper transport simulator 103 is used. In FIG. 5, a character string indicating the type of each model is defined in “Type”, and a unique numerical value set for each model is defined in “Individual ID”.

  In the “information ID” in the process unit simulator 104, a unique numerical value is defined as an ID for each input / output information (signal) of the process unit simulator 104, which is separately set as definition information of the process unit simulator 104. In the “function ID” in the image simulator 105, a numerical value unique to each function of the image simulator 105 set separately as definition information of the image simulator 105 is defined as an ID.

  In “I / O” of each simulator, the input and output of each signal in each simulator are defined as I for input and O for output. In “logic”, the logic of each signal in each simulator is defined, and positive logic is defined by a numerical value of 1 and negative logic is defined by a numerical value of 0. For example, when the “registration paper presence sensor” is 1 and indicates the presence of paper, the logic is positive, and when 0 indicates the presence of paper, the logic is negative. “Logic” is a definition that is valid only when “signal type” is B (bit information). The logical conversion of the virtual signal corresponding to the logic for each simulator is performed by each of the simulator I / Fs 107 to 110. The wiring definition information 124 may be stored in advance in the external storage device 210 as a text file in which character string information of each definition is delimited by delimiters (space, tab, line feed, etc.).

  For the “secondary transfer high voltage level determination” signal, “B” indicating that the signal is a bidirectional signal is set in “I / O” of the CPU simulator 102 and the process unit simulator 104. The signal lines of each signal defined in FIG. 5 can basically transmit signals in one direction between simulators, but for signal lines that are bidirectional signals, signals are transmitted bidirectionally between simulators. be able to.

  As described above, the definition information of the signals used in each simulator included in the wiring definition information 124 is different for each simulator even for the same signal due to the difference in the specifications of the simulator. The definition information corresponding to each simulator includes definition information unique to the connected simulator, and the definition format of these information is set for each simulator. At the time of simulation in the simulation system 100, the wiring module 112 reads the wiring definition information 124, generates signal management information 118 from the information, and provides virtual signal name-signal ID correspondence information to each simulator I / F. introduce. Each simulator I / F generates signal information 113 to 116 described later from the received correspondence information and the wiring definition information 124. Through such processing, the simulation system 100 can easily incorporate a new simulator. Details of the signal management information 118 held by the wiring module 112, the signal information 113 to 116 held by each simulator I / F, and the virtual signal value transmission process between simulators will be described later.

(CPU simulator 102)
The CPU simulator 102 is a simulator that simulates the operation of the target CPU on the information processing apparatus 200. Specifically, the CPU simulator 102 loads the firmware 209 c of the target device (image forming apparatus 300) stored in the external storage device 210 into the RAM 203. In addition, the CPU simulator 102 executes reading and writing of a target CPU register, memory, input / output signals, various calculations, and the like, which are defined in a pseudo manner on the RAM 203 in accordance with the firmware 209c. Furthermore, the CPU simulator 102 calculates the number of execution cycles that proceed in the target CPU along with the execution of these instructions.

  Here, the CPU simulator 102 executes the simulation of the firmware instruction under a virtual time different from the simulation execution time (real time) on the computer system. The virtual time in the CPU simulator 102 is obtained from the number of execution cycles of the target CPU calculated every time the firmware instruction is simulated and the operating frequency of the target CPU.

  The CPU simulator 102 notifies the content of an event that occurs with the execution of the simulation to the outside via the external I / F 119 and accepts various instructions from the outside via the I / F. Below, with reference to FIG. 6, an example of the information which CPU simulator 102 transmits / receives between simulator connection parts 101 via external I / F119 is demonstrated. FIG. 6A shows an example of the content of an event notified from the CPU simulator 102 to the simulator connection unit 101 via the external I / F 119. When the generation condition indicated by 602 is satisfied, the CPU simulator 102 notifies the outside that the event indicated by 601 has occurred, using 603 as the notification content.

  For example, “simulation start” and “simulation end” are events that occur when the CPU simulator 102 starts and ends execution of a simulation by a user operation or an external instruction. Along with the occurrence of these events, the CPU simulator 102 notifies the outside of the simulation as notification content 603 to the outside.

  Further, “read access” and “write access” occur when data is read from and written to a predetermined virtual address (address on the target CPU) area by executing firmware simulation. It is an event. (Hereinafter, these events are also referred to as “read event” and “write event”.) These events occur immediately before the execution of the read command for the target virtual address area or immediately after the execution of the write command. Accompanying these occurrences, the CPU simulator 102 is notified of the occurrence of an event, the address and size to be read or written, and the value to be read or the value to be written to the outside via the external I / F 119. Note that examples of the virtual address area targeted for a read event or a write event include a memory and a register (such as a control register of a CPU peripheral circuit) mapped in the address space. The signal identification information for the CPU simulator 102 included in the wiring definition information 124 is defined according to such mapping of the virtual address area.

  “Interrupt” is an event that occurs when simulation execution of an interrupt is started in response to an instruction from the outside. The event occurs immediately before the firmware interrupt handler process starts. Accompanying the occurrence of the event, the occurrence of the interrupt event and the number of the interrupt are notified to the outside via the external I / F 119. Here, the interrupt number is a number defined in advance for each of various interrupts of the target CPU.

  “Execution of predetermined number of cycles (timer event)” is an event that occurs when the total number of execution cycles on the target CPU, which is counted in accordance with the firmware execution instruction simulation, reaches the number of cycles specified from the outside. . If the number of cycles reaches a specified value during execution of one instruction, the event occurs after the simulation of the instruction being executed is completed. Along with the occurrence of the event, the occurrence of the timer event and the timer event number are notified to the outside via the external I / F 119. Here, the timer event number is a number designated for each event when the generation condition of the timer event is designated.

  When the CPU simulator 102 according to the present embodiment notifies the occurrence of each event to the outside, the CPU simulator 102 temporarily stops executing the firmware simulation. Further, the CPU simulator 102 waits for an instruction to resume execution from the outside, and resumes execution of the simulation.

  Next, FIG. 6B shows an example of an instruction that the CPU simulator 102 receives from the outside via the external I / F 119. Here, the CPU simulator 102 receives an instruction 611 including designation information 613 with the instruction content 612 from the outside via the external I / F 119. When the “simulation start”, “simulation end”, “simulation pause”, and “simulation restart” instructions are received via the external I / F 119, the CPU simulator 102 executes an operation corresponding to the instructions. The “read event area designation” and “write event area designation” instructions are instructions for designating a virtual address area that is a target of a read event and a write event. The

  The “predetermined area read” instruction is an instruction to request reading of the value of the virtual address area, and the instruction specifies the target virtual address, read size, and area for storing the read data. When the CPU simulator 102 receives the instruction, the CPU simulator 102 reads data of a specified size from the specified virtual address and writes it in the specified storage area. The “predetermined area write” instruction is an instruction to request writing of a value in the virtual address area, and the target virtual address, write size, and write value are designated by the instruction. When the CPU simulator 102 receives the instruction, the CPU simulator 102 writes the specified value at the specified size at the specified virtual address.

  The “register read” instruction is an instruction to request reading of the value of the designated virtual register, and the target register ID is designated by the instruction. Here, the register ID is unique identification information assigned by the CPU simulator 102 to each of the registers of the target CPU. When receiving the instruction, the CPU simulator 102 notifies the value of the virtual register designated by the register ID to the outside.

  The “register write” instruction is an instruction for requesting writing of a value to a designated virtual register, and a target register ID and a write value are designated by the instruction. When receiving the instruction, the CPU simulator 102 changes the value of the virtual register specified by the register ID to the specified value.

  Note that the registers specified by the “register read” and “register write” instructions to the CPU simulator 102 according to the present embodiment are registers (registers not defined on the address map) included in the target CPU. For this reason, the CPU simulator 102 accesses the peripheral circuit control registers and the like defined on the address map according to the “predetermined area read” and “predetermined area write” instructions.

(Paper transport simulator 103)
Next, the sheet conveyance simulator 103 performs operations of the sheet conveyance mechanism of the image forming apparatus 300 including a motor, an actuator, a sensor, and the like and conveyance of an image (toner image) formed by an electrophotographic method on the information processing apparatus 200. It is a simulator to simulate. Specifically, the paper conveyance simulator 103 can display the simulation result as a two-dimensional or three-dimensional graphic on the display device 207a, and can output the sensor information of the simulation result to the outside via the external I / F 120. Further, since it is assumed that the paper transport simulator 103 executes a simulation in response to various instructions input from the outside via the external I / F 120, the simulation is performed in cooperation with the external CPU simulator 102 and the image simulator 105. Execute.

  Hereinafter, specific processing by the paper transport simulator 103 will be described. The paper transport simulator 103 acquires a virtual signal value related to the motor and the actuator for each unit time on the virtual time via the external I / F 120 by setting a preset time as one unit time, and designates these operations. I do. Further, the sheet conveyance simulator 103 acquires the image forming state of the image forming unit based on the simulation by the process unit simulator 104 via the external I / F 120. Further, the paper transport simulator 103 is configured to perform the operation after the unit time elapses based on the designated operation regarding the motor and the actuator and the definition information regarding the interaction between the motor, the actuator, the mechanical component, the paper, and the sensor set in advance. Analyze the condition.

  Further, each time the above analysis processing is completed, the paper transport simulator 103 advances the virtual time by one unit time, updates the graphic display on the display device 207a using the analysis result, and also external I / O. The sensor state is notified to the outside via F120. Information relating to these analysis processes, information on the graphic display image forming apparatus 300, and various initial setting information are stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b. In the paper transport simulator 103, the unit time of analysis is also used as a time unit for synchronizing virtual time with an external simulator. That is, the paper transport simulator 103 performs a synchronization process with an external simulator every time one unit time simulation is executed.

  Hereinafter, with reference to FIG. 7, an example of information transmitted and received by the sheet conveyance simulator 103 to and from the simulator connection unit 101 via the external I / F 120 will be described. FIG. 7A shows an example of the contents of an event notified from the paper transport simulator 103 to the simulator connection unit 101 via the external I / F 120. When the generation condition indicated by 702 is satisfied, the sheet conveyance simulator 103 notifies the outside that the event indicated by 701 has occurred with 703 as notification content.

  “Simulation start” and “Simulation end” are events that occur when the paper transport simulator 103 starts and ends the execution of the simulation by a user operation or an external instruction. Along with the occurrence of these events, the paper transport simulator 103 notifies the outside of the simulation as the notification content 703.

  “Synchronization wait” is an event that occurs when an analysis process for one unit time is completed and a synchronization wait state is entered. Along with the occurrence of the event, the paper conveyance simulator 103 is notified of the occurrence of the synchronization waiting state and the virtual time in the paper conveyance simulator 103 at the time point to the outside via the external I / F 120. “Sensor state change” is an event that occurs when the state of a model defined as a sensor changes as a result of analysis processing for one unit time. Along with the occurrence of the event, the paper conveyance simulator 103 notifies the outside via the external I / F 120 that a change in the sensor state has occurred, and the sensor ID and sensor state information after the change. To do.

  Next, FIG. 7B shows an example of an instruction that the paper transport simulator 103 receives from the outside via the external I / F 120. The sheet conveyance simulator 103 receives an instruction 711 including designation information 713 with the instruction content 712 as an instruction content from the outside via the external I / F 120. When receiving the “simulation start” and “simulation end” instructions via the external I / F 120, the sheet transport simulator 103 executes an operation corresponding to the instructions. “Unit time processing execution” is an instruction to cancel the synchronization waiting state and execute unit time processing. When the sheet conveyance simulator 103 receives the instruction via the external I / F 120, the instruction is executed according to the instruction. Perform the action. In the sheet conveyance simulator 103 according to the present embodiment, the simulation being executed enters a synchronization waiting state when the execution of the one unit time process is completed.

  The “motor operation” instruction is an instruction for designating the motor operation, and the instruction designates the motor ID and the motor operation (drive / stop) in the next one unit time. Here, the motor ID is identification information uniquely assigned in advance to each of the motor models defined in the paper transport simulator 103. Information relating to the association between the motor model and the motor ID and speed information at the time of driving each motor are set when the user defines the configuration of the image forming apparatus 300 with respect to the simulation system 100. The set information is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b.

  The “solenoid operation” instruction is an instruction for designating the solenoid operation. The instruction designates the solenoid ID and the operation (drive / stop) of the solenoid in the next one unit time. Here, the solenoid ID is identification information uniquely assigned in advance to each solenoid model defined in the paper transport simulator 103. Information regarding the association between the solenoid model and the solenoid ID is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b.

  The “clutch operation” instruction is an instruction to specify the clutch operation, and the instruction specifies the clutch ID and the operation (drive / stop) of the clutch in the next one unit time. Here, the clutch ID is identification information uniquely assigned in advance to each of the clutch models defined in the paper transport simulator 103. Information regarding the association between the clutch model and the clutch ID is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b.

  When receiving the “motor operation” instruction in the synchronization waiting state, the sheet conveyance simulator 103 determines that the motor model of the specified motor ID is the operation state specified in the next one unit time. The operation of each component in the next one unit time is analyzed. In addition, when the paper conveyance simulator 103 receives a “motor operation” instruction in a state other than the synchronization waiting state, the sheet conveyance simulator 103 ignores the instruction. Note that the sheet conveyance simulator 103 operates in the same manner when the “solenoid operation” and “clutch operation” instructions are received.

  The “image forming state” instruction is an instruction for designating an image forming state at a predetermined image forming position. Here, the image forming position is a position that can be arbitrarily set as a position where an image is formed in the graphic display of the simulation result by the image simulator 105. This image forming position serves as a reference for the paper transport simulator 103 to obtain the positional relationship between the formed image and the paper from the graphic display. The designation is performed based on a simulation result by an image simulator 105 described later. When the sheet conveyance simulator 103 receives an “image formation state” instruction in the synchronization waiting state, it determines that the image formation state at the image formation position designated in advance is the state designated by the instruction for the next one unit time. To do. As a result, the paper transport simulator 103 sets a range for drawing an image in the graphic display after the one unit time has elapsed. On the other hand, when the sheet conveyance simulator 103 receives an instruction for an image forming state in a state other than the synchronization waiting state, the sheet conveying simulator 103 ignores the instruction.

  Next, FIG. 8 shows an example of a two-dimensional graphic display of a simulation result by the paper transport simulator 103 according to the present embodiment. FIG. 8 shows an ITB unit composed of a paper discharge tray 1001, a paper transport roller 1002, a motor 1003, a paper transport path 1004, a photosensitive drum 1005, an ITB 1006, and an ITB drive roller, a sensor 1007, a clutch 1008, a solenoid 1009, and a paper feed. A state is shown in which a tray 1010, an image (toner image range) 1011 and a paper 1012 are graphically displayed so that they can be visually confirmed. Here, a straight line shown in a circle corresponding to the roller 1002, the motor 1003, and the photosensitive drum 1005 is a display for allowing the user to check the rotation state, and the straight line is drawn along with the rotation operation. The angle changes.

  In the example shown in FIG. 8, the image forming position designated in advance is defined as the position of the contact point between the photosensitive drum 1005 and the ITB 1006 (position 1020). In the simulation by the paper transport simulator 103, the leading edge of the image 1011 occurs at the image forming position at a timing when the image forming state changes from non-image forming to image forming according to an instruction via the external I / F 120. Further, the rear end of the image 1011 is generated at the image forming position at a timing when the image forming state is changed from the image forming state to the non-image forming state by an instruction via the external I / F 120. Further, the image 1011 moves on the ITB 1006 to the secondary transfer position 1021 in accordance with the operation of the ITB 1006.

  On the other hand, the paper 1012 moves from the paper feed tray 1010 to the paper discharge tray to the secondary transfer position 1021 along the paper transport path 1004 according to the operation of the paper transport roller 1002. If an overlap occurs between the image 1011 and the paper 1012 at the secondary transfer position, the display of the image 1011 and the paper 1012 overlaps to indicate that the image 1011 has been transferred to the paper 1012. In this state, the sheet 1012 moves together with the image 1011 to the sheet discharge tray 1001 along the sheet conveying path 1004 according to the operation of the sheet conveying roller 1002. Note that the display color of the sensor 1007, the clutch 1008, and the solenoid 1009 may change depending on the state so that the operation state and the stop state can be confirmed.

(Process unit simulator 104)
Next, the process unit simulator 104 is a simulator that simulates the operations of the fixing device 317 and the process unit 405 on the information processing apparatus 200. Specifically, the process unit simulator 104 simulates a feedback signal returned to the target CPU in accordance with control signals from the target CPU of the image forming apparatus 300 to the fixing device 317 and the process unit 405, and It notifies the operating state of the electrophotographic process.

  The configurations of the fixing device and the process unit differ depending on the model of the image forming apparatus. In the process unit simulator 104, only an external I / F is prepared as a standard for exchanging simulation information with the outside and synchronizing processing. The process unit simulator 104 executes a specific simulation process according to a command statement (hereinafter referred to as “process macro”) describing a simulation operation with a predetermined grammar.

  This process macro is created by the user for each target model as a text format file, and is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b. When the process unit simulator 104 starts execution of the simulation, the process unit simulator 104 reads a process macro file including a process macro from the external storage device 210 into the RAM 203 and interprets instructions described in the file. Further, the process unit simulator 104 simulates the operation of various process units according to the interpreted instructions.

  Specifically, the process unit simulator 104 reads data received from the outside via the external I / F 121 in accordance with an instruction included in the process macro, executes predetermined processing, and performs external processing via the external I / F 121. Output data to. For example, when the temperature state of the fixing device 317 is simulated, the process macro includes a description for the process unit simulator 104 to execute the following processing.

  The process unit simulator 104 displays information indicating the driving state of the main heater 408 and the sub-heater 409, information indicating the driving state of the fixing paper discharge motor 403, and information indicating the presence / absence of paper in the fixing roller unit on the virtual time. Received via the external I / F 121 every unit time. Next, when the process unit simulator 104 starts executing the processing for each unit time, based on a predetermined arithmetic expression, the process unit simulator 104 determines the temperature sensors 411 and 412 after one unit time from the history information of the main heater and sub heater driving state changes. Obtain the basic temperature value. Further, the process unit simulator 104 corrects the temperature value of each temperature sensor according to the driving state of the fixing paper discharge motor and the presence / absence of paper in the fixing roller unit. Thereafter, information regarding the temperature values of the temperature sensors 411 and 412 is output to the outside via the external I / F 121. Similarly, the simulation processing corresponding to the contents of the process macro described by the user is executed for the other various process units. The process unit simulator 104 performs a synchronization process with an external simulator after advancing the virtual time by one unit time after the end of the simulation process for one unit time for all process units described in the process macro.

  As described above, the input / output information in the process unit simulator 104 changes for each process macro. For this reason, definition information regarding input / output information handled by the process unit simulator 104 is created in accordance with a process macro created by the user. This definition information includes an information ID, a data size, and a signal type (bit / digital / analog), is defined in an input / output definition file associated with a process macro file, and is stored in the external storage device 210 as one of setting data 209b. Stored. The process unit simulator 104 inputs and outputs information using a process macro by designating an information ID for an input / output module prepared in advance. Further, the signal identification information of the process unit simulator included in the wiring definition information 124 is defined according to this information ID as described above.

  Hereinafter, an example of information that the process unit simulator 104 transmits / receives to / from the simulator connection unit 101 via the external I / F 121 will be described with reference to FIG. FIG. 9A shows an example of the content of an event notified from the process unit simulator 104 to the simulator connection unit 101 via the external I / F 121. When the generation condition shown in 902 is satisfied, the process unit simulator 104 notifies the outside that the event shown in 901 has occurred, with 903 as the notification content.

  Here, “simulation start”, “simulation end”, and “synchronization waiting” in FIG. 9A are the same as those in the paper conveyance simulator 103 in FIG. 7A. The “output state change” is an event that occurs when information defined as output information of the process unit simulator 104 changes in the definition of input / output information. Along with the occurrence of the event, the process unit simulator 104 changes the output information to the outside via the external I / F 121, the information information ID in which the change has occurred, and the value after the change. To be notified.

  Next, FIG. 9B shows an example of an instruction received from the outside via the external I / F 121 of the process unit simulator 104. The process unit simulator 104 receives an instruction 911 including designation information 913 with the instruction content 912 as an instruction content from the outside via the external I / F 121. In this figure, the “simulation start”, “simulation end”, and “unit time processing execution” instructions are the same as those in the paper conveyance simulator 103 in FIG. 7B.

  The “input information” instruction is an instruction for specifying a value of input information to the process unit simulator 104, and an information ID and a set value of the input information are specified by the instruction. The process unit simulator 104 ignores the instruction even when the simulation is stopped. On the other hand, if the process unit simulator 104 receives the instruction during the synchronization waiting state and the simulation process for one unit time, the process unit simulator 104 receives the instruction. Note that the timing at which the input information designated by the instruction is reflected in the simulation depends on the process described in the process macro.

(Image simulator 105)
Next, the image simulator 105 is a simulator that analyzes the image forming state of the process unit 405. Here, in the image forming apparatus 300 to be simulated, an image is formed by performing image forming processes such as exposure, development, primary transfer, and secondary transfer at different positions on the image forming apparatus 300 at different timings. Formed in stages. In the image forming apparatus 300, the image forming process proceeds while the image being formed moves through the apparatus, and the finally formed toner image is transferred onto the paper at the contact point between the ITB 301 and the secondary transfer roller 316. The As described above, the image simulator 105 according to the present embodiment analyzes the position of the image formed in stages in the image forming apparatus 300 and the formation state (formation stage).

  The analysis by the image simulator 105 is performed on the assumption that a simulation is executed in accordance with signal information input from an external system via the external I / F 122. The information input from the outside includes the optical unit for the process unit 405, the control information for the high-pressure unit, and the control information for the mechanical mechanism. Further, the analysis by the image simulator 105 is performed based on the definition of the electrophotographic process such as an image formable condition, a mechanical configuration position, and a speed determination condition for each type of process defined in advance. The image simulator 105 executes acquisition of an electrophotographic process control signal from the outside and analysis of an image formation state for each preset unit time. Then, after the analysis of the image formation state for one unit time is completed, the image simulator 105 advances the virtual time by one unit time and then performs a synchronization process with an external simulator.

  The definition information of this electrophotographic process is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b. The image simulator 105 executes the above-described analysis based on the timing of changing the values of various electrophotographic process control signals and the changed values. Further, when the image formation state changes at the position designated from the outside via the external I / F 122 as the position to be analyzed, the image simulator 105 outputs information on the image formation state to the outside as a result of the analysis. To do.

  Here, in order to facilitate understanding of the invention, the concept of “position” related to the image and apparatus configuration handled in the image simulator 105 will be described. In the image forming apparatus 300 to be simulated, the image forming process is executed in stages as described above. The specific position where the image forming process is executed in the image forming apparatus 300 is, as shown in FIG. 3, the position irradiated with the laser beam from the exposure apparatuses 305a to 305d on the photosensitive drums 303a to 303d and the primary charger 304a. -D and developing units 306a-d and the contact portions of the photosensitive drums 303a-d, the primary transfer rollers 302a-d, the secondary transfer roller 316 and the ITB 301. On the other hand, the “position” handled in the image simulator 105 means a position on a path along which the image formed in the image forming process moves in accordance with the execution of the process, and from a predetermined reference position. Can be expressed by the relative distance and station information.

  The reference position is a position defined in advance on the path along which the image to be formed moves, and is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b together with the reference position information. Further, the station information is information for specifying the position in the different range because the paths until the toner images of the respective colors of yellow, magenta, cyan, and black are primarily transferred on the path are different from each other. It is. In the following, as station information, yellow, magenta, cyan, and black station information is expressed as Y, M, C, Bk, and P, which is the common path station information for primary transfer and lower.

  Next, the above-described “position” will be specifically described with reference to FIG. 3 as an example. In FIG. 3, the yellow exposure position is defined as the reference position 321. Thus, the yellow exposure position (321 in FIG. 3) is represented as [distance: 0 mm, station: Y] with respect to the distance and station information. Here, the distance from the reference position 321 through the yellow primary transfer position 323 along the yellow photosensitive drum surface to the black primary transfer position 323 along the ITB is set to 200 mm. In this case, the primary transfer position of black (322 in FIG. 3) is expressed as [distance: 200 mm, station: P].

  Further, the yellow primary charging position (324 in FIG. 3) is expressed as [distance: -20 mm, station: Y] when the distance between the yellow primary charging position 324 and the reference position 321 is 20 mm. The reason why the distance is expressed by a negative numerical value is that the position 324 is located upstream of the reference position 321 in the image forming direction. Further, the magenta development position (325 in FIG. 3) is set such that the distance from the reference position 321 to the magenta primary transfer position 326 is 100 mm, and the distance from the primary transfer position 326 to the magenta development position 325 is 30 mm. Distance: 70 mm, station: M].

Hereinafter, with reference to FIG. 9 again, an example of information that the image simulator 105 transmits / receives to / from the simulator connection unit 101 via the external I / F 122 will be described. FIG. 9C shows an example of event contents notified from the image simulator 105 to the simulator connection unit 101 via the external I / F 122. When the generation condition shown in 922 is satisfied, the image simulator 105 notifies the outside that the event shown in 921 has occurred with 923 as the notification content.
Here, “simulation start”, “simulation end”, and “synchronization waiting” in FIG. 9C are the cases in the paper transport simulator 103 in FIG. 7A and the process unit simulator 104 in FIG. 9A. It is the same. “Image formation state change” is an event that occurs when there is a change in the image formation state at the position specified by the “image state information notification position” instruction in FIG. It is. Along with the occurrence of the event, the image simulator 105 is notified of the change in the image forming state, the target position, and the image state information of the target position via the external I / F 122. The Here, the image state information is expressed using a code defined for each image forming state analyzed by the image simulator 105, and the relationship between the image forming state and the code is stored in the external storage of the information processing apparatus 200 as setting data 209b. Stored in the device 210.

  Next, FIG. 9D shows an example of an instruction received from the outside via the external I / F 122 of the image simulator 105. The image simulator 105 receives an instruction 931 including designation information 933 with the instruction content 932 as an instruction content from the outside via the external I / F 122. In this figure, “simulation start”, “simulation end”, and “unit time processing execution” instructions are the same as those in the sheet conveyance simulator 103 in FIG. 7B and the process unit simulator 104 in FIG. 9B. It is the same. The “electrophotographic process control state” instruction is an instruction for designating a control state of the electrophotographic process, and a function ID and a control value are designated by the instruction. Here, examples of the designated control state include control states (high voltage output level, drum operation state, etc.) of each function of the optical unit 413, the high pressure unit 414, and the mechanical mechanism 415 of the process unit 405. The function ID is identification information uniquely defined in advance for each function of the process unit 405 in the image simulator 105. The association information between each function and the function ID is stored in the external storage device 210 of the information processing apparatus 200 as setting data 209b. The signal identification information of the image simulator included in the wiring definition information 124 is defined according to the function ID.

  When the image simulator 105 receives the “electrophotographic process control information” instruction in the synchronization waiting state, the image on the image forming apparatus 300 after one unit time is based on the history of simulation up to that point and the specified control value. The formation position and the image formation state are analyzed. Further, when the image simulator 105 receives an instruction of the electrophotographic process control information in a state other than the synchronization waiting state, the image simulator 105 ignores the instruction.

  The “image state information notification position” instruction is an instruction to specify, to the image simulator 105, a position where image state information as an analysis result by the image simulator 105 is notified to the outside. A position on the image forming process is designated. The position is specified using a relative distance from the reference position and station information. When the image simulator 105 receives the instruction in the synchronization waiting state, the image simulator 105 sets the designated position as a notification target position in the image forming state. In the image simulator 105, when the image state at the specified position changes in the subsequent simulation execution results, an “image forming state change” event occurs according to the instruction. On the other hand, when the image simulator 105 receives an instruction for an image state information notification position request in a state other than the synchronization waiting state, the image simulator 105 ignores the instruction.

<Signal transmission processing between multiple simulators>
As described above, in the simulation system 100, each simulator connected to the simulator connection unit 101 has a different function and a different external interface specification. In the simulation system 100, in order to transmit signals between such a plurality of simulators, it is necessary to match the specifications of the external interface in each simulator with the specifications of the external interface in the simulator connection unit 101. Therefore, in order to maintain the degree of freedom of the specifications of the external interface of each simulator and realize signal transmission without changing the specifications, the signals are transmitted at the simulator connection unit 101 to which each simulator is connected. Some processing is required.

  More specifically, each simulator generally manages by assigning unique identification information to signals handled in the simulator. For this reason, in order to appropriately transmit signals between simulators, the simulator connection unit 101 specifies identification information uniquely assigned by another simulator for signals uniquely assigned identification information by one simulator. It is necessary to transmit the signal value to the simulator to be transmitted.

  In addition, when the signal value of a signal changes in any simulator, the simulator connection unit 101 transmits the changed signal value to another simulator that uses the signal. At that time, if a signal transmission process is executed each time a signal change occurs, the signal is transmitted at a timing that does not require the signal depending on the situation of the receiving simulator, and the load on the receiving simulator is reduced. There is a risk of increasing it as necessary. As a result, the simulation speed of the entire simulation system 100 may be reduced. On the other hand, instead of actively notifying each simulator of the change in signal value from the simulator connection unit 101, each simulator monitors the change in the signal value held in each simulator connection unit 101, and It can also be assumed that a signal value is obtained. However, in that case, the processing load in each simulator increases, and there is a possibility that the simulation speed is lowered as described above.

  Thus, in the present embodiment, the simulator connection unit 101 associates signal identification information that is uniquely assigned to each signal in each simulator with signal identification information that is uniquely assigned to handle each signal in the simulator connection unit 101. 113 to 116 are held in the simulator I / Fs 107 to 110, respectively. Furthermore, the simulator connection unit 101 holds signal management information 118 used for specifying a simulator to which each signal is to be transmitted based on wiring information of each signal line between the simulators. The simulator connection unit 101 can appropriately transmit a signal between simulators using these pieces of information. Hereinafter, the signal management information 118, the signal information 113 to 116, and the signal transmission processing using them will be described in more detail.

(Signal management information 118)
An example of the signal management information 118 held in the wiring module 112 will be described with reference to FIG. The signal management information 118 is generated by the signal management unit 117 based on the wiring definition information 124 in the initialization process after the simulator is started. In the signal management information 118, as shown in FIG. 10, the correspondence information of the input signals of each simulator is defined together with the signal ID and the data size. In FIG. 10, for convenience of explanation, virtual signal names are shown corresponding to each signal ID. However, the actually generated signal management information 118 does not include virtual signal names, and virtual signal names are not included. The signal ID converted from the name is included. Further, the signal management information 118 does not include signal type information. This is because when the signal management unit 117 transmits a signal between simulator I / Fs, it transmits bit pattern data of a predetermined size as it is and does not identify the type of signal.

  The signal management unit 117 identifies each simulator with identification information (simulator ID) and transmits a signal between simulators using the identification information. The simulator ID is a numerical value uniquely assigned to each simulator connected to the simulator connection unit 101, and is included in the signal management information 118. For example, different numerical values are set in the simulator ID in the order of simulator definitions included in the wiring definition information 124. In the present embodiment, 0, 1, 2, and 3 are set as simulator IDs in order for the CPU simulator 102, the paper transport simulator 103, the process unit simulator 104, and the image simulator 105 based on the wiring definition information 124 shown in FIG. Assigned. The simulator I / Fs 107 to 110 also generate simulator IDs based on the wiring definition information 124, respectively, and execute signal transmission with the signal management unit 117 using the simulator IDs.

  In the signal management information 118 in FIG. 10, a value of “0” or “1” is defined for each simulator for each signal ID. Here, when “1” is defined, a signal corresponding to the signal ID is defined as an input signal to the simulator. On the other hand, when “0” is defined, the signal corresponding to the signal ID is not defined as an input signal for the simulator, or the signal itself is not defined in the simulator. In FIG. 10, the “secondary transfer high voltage level confirmation” signal of signal ID: 42 is a bidirectional signal between the CPU simulator 102 (simulator: 0) and the process unit simulator 104 (simulator: 2). For this reason, “1” is defined in the data corresponding to these simulators, and is defined as an input signal for any simulator. By defining the signal management information 118 in this way, it is possible to realize transmission of signals regarding bidirectional signals in the simulation system 100.

(Signal information 113-116)
Next, with reference to FIG. 11, signal information 113 to 116 held in the simulator I / Fs 107 to 110 will be described. The signal information 113 to 116 is generated by each simulator I / F 107 to 110 in the initialization process after the simulator is started. Here, the simulator I / Fs 107 to 110 generate signal information 113 to 116 from the virtual signal name-signal ID correspondence information received from the wiring module 112 and the wiring definition information 124. Any information shown in FIGS. 11A to 11D is included in the signal information 113 to 116 as numerical information.

  As shown in FIGS. 11A to 11D, the signal information 113 to 116 corresponding to each simulator includes “I / O”, “data size”, “logic”, “ An “initial value” and a “signal value” are included in common. Further, the signal information 114 to 116 excluding the signal information 113 corresponding to the CPU simulator 102 includes “signal type” in common. In the present embodiment, “signal type” is set to 0 for bit information and digital multilevel information, and 1 for analog information. The reason why the “signal type” is not included only in the signal information 113 is that data (signal value) handled by the target CPU to be simulated by the CPU simulator 102 is a digital value. Each definition included in the signal information 113 to 116 corresponds to each definition having the same name included in the wiring definition information 124 (FIG. 5).

  In FIG. 11, I / O is set to 1 and 0 for signals defined as input signals and output signals in the corresponding simulator, respectively. 1 is set to I / O for a signal defined as a bidirectional signal. In the corresponding simulator, “−1” is set in I / O for an undefined signal that is not used for either an input signal or an output signal. Furthermore, the part displayed as “*” in FIG. 11 represents an indefinite value in which no value is set, and these are not referred to in the simulation.

  As the “signal value”, the “initial value” included in the signal information 113 to 116 is set to the “signal value” at the start of the simulation in the simulation system 100. This “signal value” is updated by storing a signal value that changes in each simulator as the simulation progresses. In addition, in the signal information 113 to 116, signal identification information uniquely assigned in each simulator for identifying each signal corresponding to each “signal value”, and a signal uniquely assigned in the simulator connection unit 101 Identification information (signal ID) is included. Below, with reference to FIG. 11, the signal identification information uniquely allocated in each simulator in order to identify each signal is demonstrated.

  The signal information 113 (FIG. 11A) corresponding to the CPU simulator 102 held in the simulator I / F 107 includes “address” and “bit” as signal identification information uniquely assigned by the CPU simulator 102. It is. In addition, signal information 114 (FIG. 11B) corresponding to the paper transport simulator 103 held in the paper transport simulator I / F 108 includes “model identification” as signal identification information uniquely assigned by the paper transport simulator 103. Value ”and“ Individual ID ”are included. These “model identification values” and “individual IDs” are basically the same as the definitions included in the wiring definition information 124 (FIG. 5), but the “model identification values” are sensors: 1, motors: 2, solenoids. : 3, clutch: 4, image: 5, and the like are numerical data according to "type".

  The signal information 115 (FIG. 11C) corresponding to the process unit simulator 104 held in the process unit simulator I / F 109 includes “information ID” as signal identification information uniquely assigned by the simulator. . Further, the signal information 116 (FIG. 11D) corresponding to the image simulator 105 held in the image simulator I / F 110 includes “function ID” as signal identification information uniquely assigned by the simulator. .

(Signal transmission processing between simulators)
Next, an interface between the signal management unit 117 and each of the simulator I / Fs 107 to 110 for transmitting signals between simulators will be described. The signal management unit 117 has an interface for receiving a signal output notification from each simulator I / F. Each of the simulator I / Fs 107 to 110 notifies the signal management unit 117 of a change in the output signal from the corresponding simulator by the signal output notification function. The contents notified by the signal output notification function are, for example, a simulator ID, a signal ID, a signal value, and a size.

  On the other hand, each of the simulator I / Fs 107 to 110 has an interface for receiving a signal value notification from the signal management unit 117. In response to the signal value notification, the signal management unit 117 notifies the corresponding simulator of the signal value. The content notified by the notification is, for example, a simulator ID, a signal ID, a signal value, and a size. Upon receiving the notification, each simulator I / F 107 to 110 updates the signal value of the corresponding signal included in the signal information 113 to 116 to a specified value. Below, the signal transmission process by the signal management part 117 and each simulator I / F107-110 is demonstrated in detail.

(Signal transmission processing by the signal management unit 117)
Next, with reference to FIG. 12, the procedure of signal transmission processing by the signal management unit 117 in the simulator connection unit 101 will be described. First, in S2001, the signal management unit 117 generates the signal management information 118 when the simulation by the simulation system 100 is started and the initialization process of each simulator is started. As described above, the signal management information 118 is generated based on the wiring definition information 124 stored in the external storage device 210. Thereafter, the signal management unit 117 notifies each simulator I / F 107 to 110 of correspondence information between the virtual signal name and the signal ID included in the generated signal management information 118 in S2002. Thereafter, the process proceeds to S2003.

  In step S2003, the signal management unit 117 determines whether any of the simulator I / Fs 107 to 110 has received a signal output notification that notifies the signal management unit 117 that a signal has been output from the corresponding simulator. . Here, as long as it is determined that the notification is not received, the signal management unit 117 repeats the determination process and waits until the notification is received. On the other hand, if the signal management unit 117 determines that the notification has been received, the signal management unit 117 proceeds to the process of S2004. In the present embodiment, the signal output notification includes the signal ID, the signal value, and the data size among the information included in the signal information 113 to 116 illustrated in FIG.

  In S2004, the signal management unit 117 acquires a signal ID, a signal value, and a data size included in the notification by a signal output notification from any of the simulator I / Fs 107 to 110. Subsequently, in step S2005, the signal management unit 117 uses the signal management information 118 to identify one or more transmission target simulators of the signal output from the received simulator corresponding to the signal output notification. That is, the signal management unit 117 specifies a simulator having the signal as an input signal with reference to the signal management information 118. In the case of the signal management information 118 shown in FIG. 10, a simulator having “1” as a value corresponding to the acquired signal ID corresponds to the transmission target simulator. Therefore, the signal management unit 117 specifies the simulator ID of the simulator to be transmitted from the signal management information 118. In step S2006, the signal management unit 117 notifies the simulator I / F corresponding to the specified simulator ID of the signal ID, the signal value, and the data size. In addition, the simulator I / F that has received the notification executes the processing after S2110 in FIG.

  With the above processing, the signal management unit 117 ends the signal transmission processing between the simulator I / Fs, returns the processing to S2003, and waits again until a signal output notification is received from any of the simulator I / Fs. Further, the signal management unit 117 continues to execute the processes of S2003 to S2006 until the simulation in the simulation system 100 ends.

(Signal transmission processing by each simulator I / F 107-110)
Next, with reference to FIG. 13, the signal transmission process by each simulator I / F 107-110 in the simulator connection part 101 is demonstrated. Although the simulator I / F 107 for the CPU simulator 102 is described here, the same applies to the other simulator I / Fs 108 to 110.

  First, in S2101, when the simulation by the simulation system 100 is started and the initialization process of the CPU simulator 102 is started, the simulator I / F 107 is notified from the signal management unit 117 in the process of S2002 (FIG. 12). Get information. Further, in S2102, the simulator I / F 107 generates signal information 113 using the acquired correspondence information. Thereafter, the process proceeds to S2103.

  In S2103 and S2109, the simulator I / F 107 stands by until a signal is received from either the CPU simulator 102 or the signal management unit 117. Specifically, the simulator I / F 107 first determines whether or not a signal output notification has been received from the CPU simulator 102 in S2103. In the case of the CPU simulator 102, the signal output notification corresponds to notification by a “write access” event (write event) shown in FIG. In the case of the simulator I / Fs 108, 109, and 110, the signal output notification includes “sensor state change” event (FIG. 7A), “output state change” event (FIG. 9A), and “image”. It corresponds to the notification by the “state change” event (FIG. 9C).

  If the CPU simulator 102 determines in S2103 that a signal output notification has been received, the process proceeds to S2104. If it is determined that the signal has not been received, the process proceeds to S2109. In step S2109, the simulator I / F 107 determines whether a signal output notification has been received from the signal management unit 117 (based on the processing in step S2006 in FIG. 12). Here, when the simulator I / F 107 determines that the signal output notification has been received, the process proceeds to S2110. On the other hand, when the simulator I / F 107 determines that the signal output notification has not been received, the process proceeds to S2103. repeat.

  When the signal output notification is received from the CPU simulator 102 in S2103, the simulator I / F 107 executes the following processing. First, in S2104, the simulator I / F 107 acquires a signal value included in the notification and signal identification information (first signal identification information) added to the signal value. Here, the signal identification information is identification information uniquely assigned to each signal in order to identify each signal in the CPU simulator 102. As described above, in the present embodiment, “address” and “bit” Corresponds to this. Thereafter, the process proceeds to S2105.

  In step S <b> 2105, the simulator I / F 107 searches the signal information 113 for a signal having signal identification information uniquely assigned in the CPU simulator 102. Here, only address information is provided as signal identification information from the CPU simulator 102, whereas in the CPU simulator 102, a plurality of signals having the same address are defined as bit information (information of size 1). There is a case. For this reason, the simulator I / F 107 searches for all signals having the signal identification information (address) in S2105. For simulators other than the CPU simulator 102, the simulator I / Fs 108 to 110 can uniquely specify a signal having signal identification information notified from the corresponding simulator.

  In step S2106, the simulator I / F 107 determines whether a signal corresponding to the signal identification information exists by the search. Here, if the simulator I / F 107 determines that the corresponding signal does not exist, the process proceeds to S2109. If the simulator I / F 107 determines that the corresponding signal exists, the process proceeds to S2107.

  In step S <b> 2107, the simulator I / F 107 acquires the signal ID of the searched signal from the signal information 113 held by the simulator I / F 107. Here, the signal ID corresponds to signal identification information (second signal identification information) uniquely assigned to each signal in the simulator connection unit 101. Further, in S2108, the simulator I / F 107 notifies the signal management unit 117 of a signal output notification including the signal ID, the signal value, and the data size, and the process proceeds to S2103. As a result, the signal management unit 117 receives the notification in S2003 (FIG. 12), and executes the processing from S2004 onward.

  On the other hand, when the simulator I / F 107 determines that the signal output notification is received from the signal management unit 117 in S2109, the simulator I / F 107 executes the following processing. In step S2110, the simulator I / F 107 determines whether or not the simulator ID specified by the notification matches the simulator ID of the simulator connected to the simulator I / F 107. If the simulator I / F 107 determines that these IDs do not match, the simulator I / F 107 ignores the notification and proceeds to S2103, and again waits for a signal output notification from the signal management unit 117 or the CPU simulator 102. On the other hand, if the simulator I / F 107 determines that these IDs match, the process proceeds to S2111.

  In S <b> 2111, the simulator I / F 107 updates the signal value of the signal having the signal ID specified by the signal output notification among the signal values held in the signal information 113 to the notified signal value. In step S2112, the simulator I / F 107 determines whether the signal is a signal (immediate notification signal) that needs to be immediately notified to the CPU simulator 102 at the timing when the signal value is updated. To do. When an event for acquiring an updated signal value does not occur from the simulator to the corresponding simulator I / F, it is necessary to notify the updated signal value to such a simulator. Done for. In this case, every time a change occurs in the signal value of the signal included in the signal information 113 to 116, the signal value is notified from the simulator I / F to the corresponding simulator.

  In this embodiment, the signal values updated from the corresponding simulator I / F are immediately notified to the simulators other than the CPU simulator 102 at the timing of signal value change. On the other hand, the CPU simulator 102 may be notified at an optimal timing according to the state of simulation in which the CPU simulator 102 can process the signal. In the present embodiment, the simulator I / F 107 reads out a necessary signal value from the signal information 113 and notifies the CPU simulator 102 when a read event requiring the updated signal value occurs in the CPU simulator 102. As a result, it is possible to prevent the simulation speed from being lowered by notifying the CPU simulator 102 of the signal value from the simulator I / F 107 at an inappropriate timing. Whether or not to notify each simulator of the signal value of the updated signal at the signal change timing is set in advance in the simulator configuration definition information 123 for each simulator connected to the simulator connection unit 101. .

  In S2112, each simulator I / F proceeds to S2113 when the signal to be updated is an immediate notification signal, and notifies the corresponding simulator of the updated signal value, but not the immediate notification signal. Shifts to S2114. Here, as described above, the simulator I / F 107 proceeds to S2114. In S <b> 2114, the simulator I / F 107 notifies the simulator of the updated signal value at an optimal timing (that is, when a read event occurs) according to the simulation state in which the CPU simulator 102 can process the signal. After the process in S2113 or S2114, the process returns to S2103. With the above processing, the signal value of the signal output from any simulator can be transmitted to the simulator using the signal as an input signal.

<Processing for Read Event of CPU Simulator 102>
As described above, the simulator I / F 107 notifies the updated signal value to the CPU simulator 102 when a read event occurs from the CPU simulator 102. At this time, if the signal format in the simulator connection unit 101 is different from the signal format in the signal notification simulator, it is necessary to convert the signal format to the format in the notification target simulator for notification. . Below, with reference to FIG. 14, the signal transmission process with respect to the lead event in simulator I / F107 is demonstrated. In the other simulator I / Fs 108 to 110, when the signal formats in the simulator connection unit 101 and the simulator to be notified are different, the same processing is required. Here, processing in the simulator I / F 107 and the CPU simulator 102 will be described as an example.

  First, when a read event is notified from the CPU simulator 102, the simulator I / F 107 acquires a read address, a read size, and a read value in S2201. Next, in S2202, the simulator I / F 107 refers to the signal information 113 and searches for a signal having an address that matches the acquired read address. The signal information 113 may have a plurality of addresses that match the read address. For this reason, the simulator I / F 107 searches for the addresses of all the signals included in the signal information 113 and extracts all the signals with the matching addresses.

  Thereafter, in S2203, the simulator I / F 107 determines whether there is a signal having an address that matches the read address. Here, if the simulator I / F 107 determines that there is no matching address, the simulator I / F 107 ends the process, whereas if it determines that the address exists, the process proceeds to S2204. If the read size specified by the read event notification is larger than the data size of each signal set in the signal information 113, an address in the range of “read address” to “read address + read size” is used. Make a comparison. When the read size is smaller than the data size of each signal set in the signal information 113, addresses are compared at addresses in the range of “read address” to “read address + virtual signal data size”. . Note that such address search processing is similarly performed when not only a read event but also a write event is notified.

  In S2204, the simulator I / F 102 determines the CPU based on the bit information, data size information, and signal value of the signal information 113 and the read size and read value acquired in S2201 for all the signals extracted in S2202. Data for updating data in the virtual address area in the simulator 102 is generated. Specifically, the generated data includes information on addresses, bits, and signal values of all acquired signal IDs.

  Here, the simulator I / F 107 converts the format of the signal to be notified in accordance with the format of the signal in the CPU simulator 102 that is the signal notification target. For example, when the data size of the virtual signal in the simulator connection unit 101 and the data size in the CPU simulator 102 are different, the simulator I / F 107 converts the data size of the signal to be notified. When the endian is different between the simulator connection unit 101 and the CPU simulator 102, the simulator I / F 107 converts the endian of the signal to be notified.

  Thereafter, the simulator I / F 107 notifies the CPU simulator 102 of the signal after the signal format conversion. The CPU simulator 102 updates the signal value of the corresponding signal to the notified signal value, and executes a simulation with reference to the signal value. As described above, the simulator I / F 107 ends the signal transmission process corresponding to the light event.

<Specific example>
Next, as a specific example of signal transmission processing between a plurality of simulators constituting the simulation system 100 according to the present embodiment described above, processing relating to a main motor drive signal and a registration sheet presence sensor signal will be described.

(In case of main motor drive signal)
First, a write event is notified from the CPU simulator 102 to the simulator I / F 107. As a result, the simulator I / F 107 recognizes the virtual address area where the value is written by the write event. That is, the simulator I / F 107 writes the specified value to the virtual address area specified by the virtual address and bit information specified in the notification, and thereby the signal of the signal corresponding to the virtual address area Recognize that the value changes. Here, as an example, it is assumed that virtual address: 0x0003, bit: 0, and value: 1 are specified in the notification. Next, the simulator I / F 107 obtains the signal ID: 5 by searching for the signal having the virtual address and the bit information as signal identification information from the signal information 113 for the CPU simulator 102 (FIG. 11A). To do. Thereafter, the simulator I / F 107 notifies the signal management unit 117 of the signal ID: 5 and the value: 1 as a signal output notification.

  Next, the signal management unit 117 identifies, from the signal management information 118, a simulator that uses the signal having the signal ID: 5 specified by the signal output notification received from the simulator I / F 107 as an input signal. Thereby, the signal management part 117 specifies the simulator of the transmission target of a signal. In this case, the signal management unit 117 acquires simulator IDs 1 and 2 using the signal ID: 5 as an input signal from the signal management information 118 (FIG. 10). Furthermore, the signal management unit 117 issues a signal output notification to the simulator I / Fs 108 and 109 corresponding to these simulator ID simulators (the paper transport simulator 103 and the process unit simulator 104).

  Next, the simulator I / Fs 108 and 109 update the signal information 114 and 115 held by each according to the signal output notification received from the signal management unit 117. Specifically, the signal value of the signal having the signal ID: 5 included in the notification is updated to the value 1. Further, the simulator I / Fs 108 and 109 notify the changed signal values to the paper transport simulator 103 and the process unit simulator 104, which are connection destination simulators, respectively.

(In the case of sensor signal with register paper)
First, the occurrence of a sensor signal change event is notified from the sheet conveyance simulator 103 to the simulator I / F 108. By this notification, the simulator I / F 108 recognizes that the signal value of the signal having, for example, sensor ID: 1 (model identification value: 0, individual ID: 1) as signal identification information has changed to value: 1. Then, the simulator I / F 108 searches for the signal ID (signal ID: 3) of the signal having the signal identification information from the signal information 114 (FIG. 11B). Thereafter, the simulator I / F 108 notifies the signal management unit 117 of the acquired signal ID: 3 and value 1: as a signal output notification.

  Next, the signal management unit 117 specifies a simulator (the CPU simulator 102 with the simulator ID: 0) having the signal having the signal ID: 3 specified by the signal output notification received from the simulator I / F 108 as an input signal. Further, the signal management unit 117 issues a signal output notification with a signal ID of 0 and a signal value of 1 to the simulator I / F 107 corresponding to the CPU simulator 102 with the simulator ID of 0.

  Next, the simulator I / F 107 updates the signal information 113 in accordance with the signal output notification received from the signal management unit 117. Specifically, the signal value of the signal having the signal ID: 3 included in the notification is updated to the value 1 included in the notification. Thereafter, when the read event from the CPU simulator 102 to the address 0x000002 occurs as described above, the simulator I / F 107 notifies the CPU simulator 102 of the updated signal value and instructs the data update.

  As described above, in the information processing apparatus 200 according to the present embodiment, the simulator connection unit 101 corresponds to each of a plurality of connected simulators, and is assigned to the signal output from each simulator. Signal information including identification information is held. The signal information includes a signal output from each simulator and signal identification information uniquely assigned in each simulator and simulator connection unit 101 in order to identify each signal. The simulator connection unit 101 further holds signal management information for managing signal wiring information for specifying a simulator to which a signal is to be transmitted. When a signal to which the first signal identification information unique to the simulator is added from any simulator, the simulator connection unit 101 outputs a second signal unique to the simulation connection unit 101 for identifying the signal. Identification information is acquired from signal information. Furthermore, the simulator connection unit 101 specifies the simulator to which the signal is to be transmitted using the signal management information, and updates the signal value included in the signal information corresponding to the specified simulator with the output signal value. . After that, the simulator connection unit 101 determines the timing of notifying the simulator of the signal according to the signal transmission target simulator, and notifies the signal at the determined timing.

  Through the above processing, the information processing apparatus 200 according to the present embodiment can appropriately transmit signals between simulators having different specifications while maintaining the degree of freedom of the specification of the interface for connection to the outside in each simulator. . In addition, since the information processing apparatus 200 transmits the output signal from each simulator only to the identified simulator to be transmitted, the frequency of inter-process communication can be reduced for a plurality of simulators executed in different processes, Efficient simulation can be realized.

  Further, in the information processing apparatus 200, it is not necessary for each simulator to constantly monitor the change in the signal value held in the simulator connection unit 101, so that the simulation load can be reduced. Furthermore, since the simulator connection unit 101 notifies the simulator of the signal value at a timing at which each simulator can process a signal, notification according to the simulation status in the simulator is possible. For this reason, it is possible to prevent an increase in the simulation load accompanying the notification of the signal value from the simulation connection unit 101 to each simulator, and to prevent a decrease in the simulation speed.

  Various modifications can be made to the above-described embodiment. For example, the signal information 113 to 116 held by the simulator I / Fs 107 to 110 may be held in, for example, the core unit 106 or the wiring module 112. Even in that case, an effect equivalent to the above-described effect can be obtained. Further, as shown in FIG. 17, the signal management unit 117 may manage the signal management information 118 as different pieces of information different for each simulator. In FIG. 17, only the signal defined as the input signal is included in each signal management information for each simulator. Thereby, for example, when a large number of input signals are biased and defined in any one of the simulators, it is possible to reduce the load when referring to (searching) the signal management information and to improve the execution efficiency of the simulation.

[Second Embodiment]
In the first embodiment, the simulator I / F 107 needs to search the signal information 113 for a signal ID corresponding to the notified address (signal identification information) in response to a read event or a write event from the CPU simulator 102. is there. In that case, since there may be a plurality of signals corresponding to the same address in the signal information 113, the simulator I / F 107 must always search for the address over the entire area of the signal information 113. Further, when the access size to the memory in the CPU simulator 102 and the access size to the memory in the simulator connection unit 101 are different, it is necessary to perform address comparison in consideration of the size difference, so that the comparison process is complicated. There is a risk of becoming.

  Therefore, in the second embodiment, the simulator I / F 107 corresponding to the CPU simulator 102 includes the address information of the virtual memory in the CPU simulator 102, the signal ID, and the signal information 113 according to the first embodiment. Further correspondence information is retained. By using the information, the signal transmission process for the read event and the write event by the CPU simulator 102 in the simulator I / F 107 is simplified. In the following, only parts different from the first embodiment will be described for the purpose of simplifying the description.

  The configuration of the simulation system 100 according to the present embodiment is basically the same as that in FIG. 1, but there is a difference in information included in the signal information 113 held by the simulator I / F 107 corresponding to the CPU simulator 102. In the present embodiment, the signal information 113 includes information related to the virtual memory of the CPU simulator 102 (virtual memory information) in addition to the information illustrated in FIG. 10 in the first embodiment.

  Here, the virtual memory information 1501 included in the signal information 113 will be described with reference to FIG. In this embodiment, the virtual memory information 1501 is correspondence information between address information on the memory area of the virtual memory used by the CPU simulator 102, data of each address area, and signal ID of a signal corresponding to each address area. It is. In the virtual memory information 1501 shown as an example in FIG. 15, 15 pieces of signal ID information can be associated with each address information, but the number of associated signal IDs can be changed as appropriate.

  Similar to the generation of the signal information 113 in the first embodiment, the virtual memory information 1501 is generated by the simulator I / F 107 in the initialization process after starting the simulator. Specifically, the simulator I / F 107 generates virtual memory information 1501 by associating all signal IDs defined for each address area with each address area. When there is no signal ID corresponding to the address area, “−1” is set as the correspondence information as shown in FIG.

  Next, a signal transmission process using the virtual memory information 1501 will be described. In the present embodiment, the signal transmission processing by the signal management unit 117 is the same as that in the first embodiment (FIG. 12), and thus description thereof is omitted. Further, signal transmission processing by the simulator I / Fs 107 to 110 is basically the same as that of the first embodiment (FIG. 12), and only different parts will be described below.

  In this embodiment, the simulator I / F 107 refers to the virtual memory information 1501 when searching for the signal identification information from the signal information 113 in S2105 of FIG. 12, and the signal identification information uniquely assigned in the CPU simulator 102 Search for (address). In this embodiment, the simulator I / F 107 updates the data in the address area corresponding to the signal ID specified by the signal output notification to the notified signal value by referring to the virtual memory information 1501 in S2111. . Further, in S2114, the simulator I / F 107 notifies the CPU simulator 102 of the signal value obtained by referring to the virtual memory information 1501.

  Next, with reference to FIG. 16, a process for the read event of the CPU simulator 102 using the virtual memory information 1501 will be described. First, when a read event is notified from the CPU simulator 102, the simulator I / F 107 acquires a read address, a read size, and a read value in S2601. Next, in S2602, the simulator I / F 107 refers to the virtual memory information 1501 and acquires data corresponding to the acquired read address. Further, in S 2603, the simulator I / F 107 notifies the CPU simulator 102 of the data in response to an instruction from the external I / F 120 of the CPU simulator 102. At that time, the simulator I / F 107 notifies the data together with instruction information for instructing the CPU simulator 102 to update the data to the address area of the CPU simulator 102 corresponding to the read address and the read size acquired in S2601. . As described above, the simulator I / F 107 ends the signal transmission process corresponding to the light event.

  With the above processing, the information processing apparatus 200 according to the present embodiment can simplify the address information search processing in the simulator I / F 107 and can execute signal transmission processing to the CPU simulator 102 at higher speed. become. Thereby, the execution of the simulation in the simulation system 100 can be further accelerated as compared with the first embodiment.

[Other Embodiments]
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (7)

A plurality of simulators for simulating the operations of a plurality of constituent elements of the apparatus to be simulated, and a connection means for interconnecting the plurality of simulators and transmitting signals between the plurality of simulators, An information processing apparatus that simulates the operation of the simulation target apparatus by operating a simulator in cooperation with each other,
The connecting means includes
A signal output by simulation from each connected simulator, first signal identification information uniquely assigned in each simulator to identify each signal, and uniquely assigned in the connection means to identify each signal Holding means for holding signal information including second signal identification information;
When a signal to which the first signal identification information is added is newly output from any of the plurality of simulators, the second signal identification information for identifying the output signal is held in the holding unit. Obtaining means for obtaining from the signal information;
Among the plurality of simulators, a specifying unit that specifies a simulator that is a transmission target of a signal identified by the acquired second signal identification information, using management information held in advance,
For the identified simulator, an update means for updating the signal held in the holding means to the newly output signal;
Determination means for determining whether to immediately notify the updated signal from the timing updated by the update means to the identified simulator;
When it is determined that the updated signal is to be notified immediately, the updated simulator is notified, and when it is determined that the updated signal is not immediately notified, the specified simulator can be processed. An information processing apparatus comprising: notification means for notifying the updated signal at a proper timing. Each simulator
When it is time to process the signal held in the holding means, the apparatus further comprises request means for requesting the connection means to notify the held signal,
The notification means includes
If it is determined that the updated signal is not immediately notified to the specified simulator, the signal held in the holding unit is sent to the specified simulator in response to a request from the request unit. The information processing apparatus according to claim 1, wherein notification is performed. The connecting means includes
From the wiring information for transmitting signals among the plurality of simulators set by the user, a simulator for transmitting signals to which each of the second signal identification information unique to the connection means and the second signal identification information is assigned. The information processing apparatus according to claim 1, further comprising a generation unit configured to generate the management information in association with the management information. The notification means includes
For the updated signal, if the format of the signal held in the holding means is different from the format of the signal that can be processed by the simulator to be notified, the format of the updated signal is changed to the simulator to be notified. The information processing apparatus according to any one of claims 1 to 3, wherein the information processing apparatus converts the information into a format that can be processed by the notification. The signal information is
Further includes correspondence information between address information on a memory area in which data of each signal is stored in the simulator connected to the connection means and second signal identification information assigned to each signal;
The notification means includes
The updated simulator is notified to the specified simulator together with instruction information for updating data in a memory area specified by address information included in the signal information corresponding to the updated signal. The information processing apparatus according to any one of claims 1 to 4. A plurality of simulators for simulating the operations of a plurality of constituent elements of the apparatus to be simulated, and a connection means for interconnecting the plurality of simulators and transmitting signals between the plurality of simulators, An information processing apparatus control method for simulating the operation of the simulation target apparatus by operating a simulator in cooperation with each other,
In the connection means,
The holding means includes a signal output in simulation from each connected simulator, first signal identification information uniquely assigned in each simulator for identifying each signal, and in the connection means for identifying each signal. Holding step for holding signal information including second signal identification information uniquely assigned;
When the acquisition unit newly outputs a signal to which the first signal identification information is added from any of the plurality of simulators, the holding unit stores the second signal identification information for identifying the output signal. Obtaining from the signal information held by
A specifying step for specifying a simulator to be transmitted of a signal identified by the acquired second signal identification information among the plurality of simulators using management information held in advance;
An updating step for updating the signal held by the holding means to the newly output signal for the identified simulator;
A determination step of determining whether or not to immediately notify the updated signal to the identified simulator from the timing updated in the update step;
When it is determined that the notification means immediately notifies the updated signal, the notification means notifies the updated signal, and when it is determined not to notify the updated signal immediately, the specified And a notification step of notifying the updated signal at a timing that can be processed by the simulator.   A program for causing a computer to execute the control method of the information processing apparatus according to claim 6.

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