JPH02101487U - - Google Patents
Info
- Publication number
- JPH02101487U JPH02101487U JP998489U JP998489U JPH02101487U JP H02101487 U JPH02101487 U JP H02101487U JP 998489 U JP998489 U JP 998489U JP 998489 U JP998489 U JP 998489U JP H02101487 U JPH02101487 U JP H02101487U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- insulating substrate
- pin terminal
- mounting
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 238000003491 array Methods 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Connecting Device With Holders (AREA)
Description
第１図および第２図はそれぞれ本考案半導体装
置の一実施例を示すピン端子近傍の断面図および
その一部を切欠いた拡大平面図、第３図および第
４図は本考案ソケツトの一実施例を示す斜視図お
よびその導出ピン端子の断面構造図である。
１……半導体チツプ、２，３……外部リード端
子、４……絶縁物、５……封止樹脂、６……内側
導電膜、７……外側導電膜、８……内側配列ピン
、９……外側配列ピン、１０……絶縁基板。
1 and 2 are a cross-sectional view of the vicinity of a pin terminal and a partially cutaway enlarged plan view showing an embodiment of the semiconductor device of the present invention, respectively, and FIGS. 3 and 4 are an embodiment of the socket of the present invention. FIG. 2 is a perspective view showing an example and a sectional structural view of a lead-out pin terminal thereof. 1... Semiconductor chip, 2, 3... External lead terminal, 4... Insulator, 5... Sealing resin, 6... Inner conductive film, 7... Outer conductive film, 8... Inner array pin, 9 ...Outer array pin, 10...Insulating board.
Claims (1)
出される複数個の外部リード端子と、前記外部リ
ード端子の互いに隣接する２つを絶縁物を介しそ
れぞれ互いに対向させて形成する積層リード構造
のピン端子とを含むことを特徴とする半導体装置
。 (2) 絶縁基板と、前記絶縁基板の上面に孔内導
電膜をそれぞれ２分割して配列される複数個の半
導体装置装着用ピン端子挿入孔と、前記孔内導電
膜のそれぞれと導通し前記絶縁基板の底面から内
側及び外側の２つの配列で導出されるピン端子配
列とを含むことを特徴とする半導体装置装着用ソ
ケツト。[Claims for Utility Model Registration] (1) A semiconductor chip, a plurality of external lead terminals drawn out from the semiconductor chip, and two adjacent external lead terminals facing each other through an insulator. 1. A semiconductor device comprising: a pin terminal having a laminated lead structure. (2) an insulating substrate, a plurality of pin terminal insertion holes for mounting a semiconductor device arranged on the upper surface of the insulating substrate by dividing the in-hole conductive film into two, and electrically conductive with each of the in-hole conductive films; 1. A socket for mounting a semiconductor device, comprising a pin terminal array led out from the bottom surface of an insulating substrate in two arrays, inner and outer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP998489U JPH02101487U (en) | 1989-01-30 | 1989-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP998489U JPH02101487U (en) | 1989-01-30 | 1989-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02101487U true JPH02101487U (en) | 1990-08-13 |
Family
ID=31217214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP998489U Pending JPH02101487U (en) | 1989-01-30 | 1989-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02101487U (en) |
-
1989
- 1989-01-30 JP JP998489U patent/JPH02101487U/ja active Pending
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