JPH0199260A - Manufacture of high breakdown voltage mos semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a contact and a diffused resistance by forming both an output necessary for high breakdown voltage and large current and a logic unit necessary for high speed, formed on the same substrate in a silicide structure. CONSTITUTION:A silicon oxide film 102 is grown on a silicon substrate 101. Then, an antioxidation film 103 is patterned, and impurity ions are implanted into channel stopper 104 and a drain low concentration impurity region 106. With the film 103 as a mask the silicon substrate 101 is selectively oxidized, and a gate oxide film 108 and gate electrodes 109, 110 are formed. Then, source, drain high concentration impurity regions 105, 106 are formed, and a silicon oxide film 121 is grown on the side face of the gate electrode. Thereafter, the gate electrode, source, drain high concentration impurity region silicon substrate surfaces are opened, and metal or silicides 25, 127 disposed thereat are formed in a self-alignment manner.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is particularly applicable to MOS transistors having different drain breakdown voltages arranged on the same semiconductor substrate, and a gate electrode and a highly doped drain region formed using salicide (self-concentration line). The present invention relates to a method of manufacturing a high voltage MaS type semiconductor device having a silicide structure.

[Conventional technology]

In general, ICs that drive display devices, thermal heads for thermosensitive recording, etc. have a drain breakdown voltage of several tens of sevens in the drive output section.
The high power MO3) transistor and the logic part that controls it are MOS that operates at a low voltage of about 7V or less.
Circuits consisting of transistors are arranged on the same semiconductor substrate, and many improvements have been made to the MO3 type high-voltage semiconductor devices and manufacturing methods conventionally used for these drive devices, such as miniaturization and contact migration. From the viewpoint of performance, a salicide structure has been proposed that can lower the contact resistance and the sheet resistance of the diffusion layer.

The manufacturing method is, for example, as shown in Fig. 2 (α).
After growing a first silicon oxide film 202 on a mold silicon substrate 201, an oxidation-resistant film 20 made of a silicon nitride film is grown.
3 is vapor-phase grown and photoetched into a predetermined shape, and boron is deposited 5x using the photoresist and oxidation-resistant film 203 as a mask.
After forming a channel stopper 204 in a predetermined region by ion implantation with a degree of 10 "cm-", phosphorous is ion-implanted using a new photoresist and an oxidation-resistant film 206 as a mask, and the source and drain of the high voltage NQh) transistor are ion-implanted. Concentrated impurity regions (off-cellar) 205 and 2C16 are formed. The dose at this time is arbitrarily selected depending on the drain breakdown voltage of the high voltage transistor, and is 1X1012 to IX1
At 0.14cmf 9 degrees, the concentration is lower than the source and drain electrode number area. Further, the channel length of the high voltage transistor is determined by the dimensions of the oxidation-resistant film 2030 sandwiched between the low concentration impurity regions 205 and 206. Next, oxidation-resistant film 2
03 as a mask, 5oo by steam oxidation at 1000℃
A field oxide film 20 is formed by forming an oX silicon oxide film.
7, then as shown in Figure 2(b), oxidation-resistant film 20.5
After completely removing the first silicon oxide film 202 and forming a gate oxide film 20B, implanting channel doping ions and adjusting the threshold voltage, polycrystalline silicon is grown in a vapor phase of about 4000× and the gate is etched by photoetching. Regarding the electrodes 209 and 210, the width of the gate electrode 209 in the logic section is at least 2 μm, and the width of the gate electrode 210 in the high voltage output section is about 7 μm. Using the gate oxide films 209 and 210 and the field oxide film 207 as masks, phosphorus is applied to the N-type high concentration impurity regions 212 and 213, which will become the source and drain, through the gate oxide film 208 in an approximately 4×1 manner.
After 0"m"22 ion implantation, heat treatment for activation is performed.

Next, as shown in FIG. 2(C), a second silicon oxide film 221 is deposited by vapor phase growth, and then photoetched to form the silicon oxide film 221 in the high voltage part and the gate oxide film on the source and drain. After removing 208, 40% titanium 222
After 0~1oo-oX sputtering and nitrogen annealing at 700°C using a halogen lamp, the high breakdown voltage output section 220
The titanium in contact with the highly concentrated sources and drains 212 and 213 and the silicon of the gate electrode 210 is converted into monosilicide, and the surface on the oxide film becomes titanium nitride. This silicon oxide film 221 is necessary in order to prevent the logic portion from being damaged between the gate electrode, source, and drain during the salicide process.

Next, as shown in FIG. 2(d), for example, when immersed in a mixture of hydrogen peroxide and ammonia water, only titanium nitride is removed, and then annealed with a halogen lamp at 800°C, the remaining monosilica The id is made of titanium disilicide or polycide 225.226, and a sheet resistance of about 3Ω/hole is obtained.

Next, as shown in FIG. 2(-), a vapor phase grown silicon oxide film is formed to serve as an interlayer insulating film 215, a contact hole is formed, a metal wiring 216 is formed, and then a PSG film is formed as a passivation film 217. The film and plasma nitride film are grown in a vapor phase, and holes are provided to expose several electrodes to the outside.

[Problem that the invention seeks to solve]

However, in the conventional technology, although the high breakdown voltage output section is salicided, the logic section is not salicided, which hinders speeding up and miniaturization of the logic section. The present invention solves these problems, and provides a method for manufacturing a high-voltage MO3 type semiconductor device in which a control logic circuit is formed on the same semiconductor substrate, which makes it possible to improve electric characteristics and downsize the device. It is something to do.

[Means for solving problems]

The method of manufacturing a high breakdown voltage MO3 type semiconductor device of the present invention includes at least a step of patterning an oxidation-resistant film, a step of ion-implanting impurities into low concentration impurity regions of a channel stopper and a drain, and using the oxidation-resistant film as a mask. The method includes a step of selectively oxidizing a silicon substrate, a step of forming a gate oxide film and a gate electrode, a step of forming high concentration impurity regions of a source and a drain, and then forming sidewalls of a silicon oxide film on the sides of the gate electrode. Process and source and drain high concentration impurity regions After going through the process of opening holes on the silicon substrate surface, and after going through the process of opening holes on the silicon substrate surface of the gate electrode and source and drain high concentration impurity regions, It is characterized in that metal or its silicide is formed in a self-aligned manner in the high concentration impurity region.

〔Example〕

FIG. 1 (α) to (-) show a thermal head drive construction C according to an embodiment of the present invention, which has a low voltage withstand voltage MOS logic circuit driven by, for example, 5V, and whose output section is an open drain high voltage MehMo S transistor. 120 is a high breakdown voltage output section, and 130 is a low breakdown voltage logic section.

First, as shown in FIG. 1 (α), a first silicon oxide film 102 of approximately 800× is grown on a P-type silicon substrate 101 with a specific resistance of 5 to 25 Ω, and then an oxidation-resistant film made of a silicon nitride film is grown. The film 103 is grown in a vapor phase, photoetched into a predetermined shape, boron ions are implanted at 5×10 cm using the photoresist and the oxidation-resistant film 103 as a mask, and a channel stopper 104 is formed in a predetermined region. Using the resist and oxidation-resistant film 103 as a mask, ion implantation of 1×10130-2 phosphorus is performed to obtain a high breakdown voltage (NCh).
Low concentration impurity regions (off-cellar) 105 and 106 of the source and drain of the transistor are formed. The dose amount at this time can be arbitrarily selected depending on the drain breakdown voltage of the high voltage transistor. In addition, the channel length of the high voltage transistor is determined by the oxidation-resistant film 10 sandwiched between the low concentration impurity regions 105 and 106.
3, and was set to 5 μm. Subsequently, using the oxidation-resistant film 103 as a mask, ao
Field oxide film 1 is formed by forming a silicon oxide film of ooX.
It was set as 07.

Next, as shown in FIG. 1Cb), the oxidation-resistant film 103 and the first silicon oxide film 102 are completely removed, and then the gate oxide film 1 is removed.
After forming 08, implanting channel doping ions and adjusting the threshold voltage, polycrystalline silicon was deposited at 4000 nm.
The gate electrodes 109 and 110 are formed by X vapor phase growth, doping with impurities, and photoetching. At this time, the width of the gate electrode 1090 in the logic part is at least 2 μm, and the width of the gate electrode 110 in the high voltage output part is 7 μm. did. Using the gate electrodes 109 and 110 and the field oxide film 107 as a mask, phosphorus is applied to the N-type high concentration impurity regions 112 and 113, which will become the source and drain, through the gate oxide film 108.
After X 10""cm-" ion implantation, steam oxidation at 850° C. for 40 minutes is performed as activation and oxidation heat treatment to form a second silicon oxide film 121 on the polycrystalline silicon.
grow. When performing this activation and oxidation treatment, in order to prevent bunch-through of transistors in the logic area and to limit the diffusion depth, a heater heat treatment furnace is used at a temperature of 800°C or more.
The temperature is regulated to 1000°C, or 900°C to 1100°C in an instantaneous annealing furnace such as a halogen lamp. On the other hand, ion implantation may be performed after an oxidation treatment is performed in advance, and then an activation treatment may be performed.

Next, as shown in FIG. 1<c>, a second silicon oxide film 121 is formed.
B engineering 1! t (Reactive on Tit
The side walls of the gate electrode are formed by anisotropic etching with chθr). At this time, the high concentration impurity regions of the source and drain and the silicon oxide film on the gate electrode are removed.
It is best to perform light etching with dilute hydrofluoric acid to the extent that the sidewalls are not reduced more than necessary to ensure that the silicon surface is exposed. Further, the second silicon oxide film 121 can also be a vapor-grown film whose thickness is controlled. Next, after sputtering 6 oals of titanium 12.2, nitrogen annealing is performed at 700° C. using a halogen lamp, and the titanium in contact with the silicon of the highly concentrated sources and drains 112 and 113 and the gate electrodes 109 and 110 is converted to monosilicide. Titanium nitride is on the oxide film.

Next, as shown in FIG. 1(d), for example, when immersed in a mixture of hydrogen peroxide and ammonia water, only titanium nitride is removed, and then annealed with a halogen lamp at 800°C, the remaining monosilicide is removed. is titanium disilicide 125, 127 or polycide 126, 128, and a sheet resistance of about 3 Ω/hole is obtained.

Next, as shown in FIG. 1 (#), a vapor phase grown silicon oxide film is formed to form an interlayer insulating film 115, a contact hole is formed, a metal wiring 116 is formed, and then a passivation film 117 is formed by vapor phase growth. Grow a silicon oxide film,
1 to the outside! Equipped with a pole extraction hole.

In this way, the thermal head driving structure O having a metal salicide structure is formed in the high voltage withstanding section and the logic section as well. The actual resistance of this source and drain is 55Ω with a 2μm opening.
It is as follows. The gate electrode, high concentration impurity region source, and drain regions of the logic section are made of polycide or silicide, improving response speed and miniaturization. In addition, it is not limited to the NQhMO3 structure shown in the embodiment, but the logic section or the output section may be Pch or cMos, or a combination thereof, or DMO8 (Double Diffused
It can also be applied to a MOS (MOS) structure, and has also been applied to driving liquid crystals, plasma, and fluorescent displays in addition to thermal head drive technology C. Also, since the polycrystalline silicon film and high concentration impurity regions used as electrostatic protection for the input/output terminals of logic circuits are silicided, it is necessary to selectively leave a silicon oxide film or select titanium before the salicidation process. Alternatively, a low concentration impurity region, a diffusion layer similar to a stopper, or a well layer such as OMO3 may be used instead.

Furthermore, silicides, or metal silicides, include not only titanium but also tungsten, tantalum, and cobalt.

High melting point metals 4 such as molybdenum and platinum are also applicable.

〔Effect of the invention〕

As described above, the present invention enables a salicide structure for both the output section, which requires a high withstand voltage and large current, and the logic section, which requires high speed, to be formed on the same substrate, thereby reducing contact and diffusion resistance, and making it possible to High power.

This enables miniaturization and improved electrical characteristics and reliability. Furthermore, since side walls are formed on the gate electrode, the level difference is improved and there is also the effect of improving the coverage of metal wiring such as aluminum.

[Brief explanation of the drawing]

FIGS. 1(α) to 1(-) are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIGS. 2(α) to 2(-) are schematic cross-sectional views showing a conventional semiconductor device manufacturing process. 101.201...Silicon substrate 102.20
2...First silicon oxide film 105.205.
...Oxidation-resistant film 104.204...Channel stopper 105.205...Source low concentration impurity region 106.206...Drain low concentration impurity region 107. 207...7' yield oxide film 108.208...gate oxide film 10
9.209... Gate electrode 110 of low breakdown voltage section.
210... Gate electrode 112.21 of high voltage part
2...Source high concentration impurity region 113.215
...Drain high concentration impurity region 115.215
. . . Interlayer insulating film 116.216 . . . Metal wiring 117.217 . . . Passivation film 121.
221.°...Second silicon oxide film 122.22
2...Titanium 125.127・Si・2・25...Silicide 126.128,226...Polycide 120
．． 220...High voltage resistance part 130. 230...Low voltage resistance part and above Applicant Seiko Epson Corporation Figure 1(b) Figure 1cc) Figure 1(d) Figure 1( e) Figure 2 (α) Figure 2 (b) Figure 2 (C) Figure 2 (J) Figure 2 (6)

Claims (1)

[Claims] At least, a step of patterning an oxidation-resistant film, a step of ion-implanting impurities into low concentration impurity regions of a channel stopper and a drain, a step of selectively oxidizing a silicon substrate using the oxidation-resistant film as a mask, a gate oxide film and a gate electrode. and a step of forming high-concentration impurity regions of the source and drain, followed by a step of forming sidewalls of a silicon oxide film on the side surfaces of the gate electrode and a step of forming high-concentration impurity regions of the source and drain on the silicon substrate surface. 1. A method of manufacturing a high-voltage MOS type semiconductor device, characterized in that metal or its silicide is formed in a self-lined manner in high-concentration impurity regions of a gate electrode, source, and drain after a step of opening a hole.