JPH0196853A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To execute a stable auto tracking by storing the reference phase of a tracking variable means for sampling data in a storing means and sending the reference phase to the tracking variable means as the last reference phase. CONSTITUTION:A regenerative envelope signal from a rotary head 8 or 9 is inputted to a comparator 19 through amplifying circuits 14 and 16, detecting circuits 15 and 17, and a switching circuit 18, and the envelope signal is compared with the counting up signal of a reference clock signal from an ADC 3 of a microprocessor (MP) 10 and inputted to a terminal 25. On the other hand, the output signals of a frequency generator 3, a phase detector 4, a control head 5, and a frequency generator 7 are inputted to terminals 21-25. The signals of terminals 21-26 are sent to a data bus 600 through a CTRL 800 and a register 700 and fetched in a RAM 200. The difference among the sampling data in the detector 4 is calculated the plural numbers of times through an ALU 300, the reference phase is stored in the RAM 200, and the reference phase is sent to a capstan motor 6 through a DAC 1400 and a driver 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a magnetic recording/reproducing device having an auto-tracking function, and in particular provides a device that can be easily implemented at low cost using a microprocessor.

BACKGROUND OF THE INVENTION In recent years, microprocessors have become widespread and are now being used in many household electrical appliances. Home video tape recorder (hereinafter abbreviated as VTR)
Microprocessors are no exception, and microprocessors are actively used at the center of systems such as controlling the loading mechanism that pulls the magnetic tape out of the cassette and winding it around the rotating head, and the program reservation system that combines a timer. However, precision rotation control devices for the cylinder motor that drives the rotating head and the capstan motor that runs the magnetic tape at a constant speed require complex judgment operations and rapid processing of detection signals, so microprocessors are not required. It has relied on specialized hardware.

FIG. 10 is a block diagram showing the configuration of a servo mechanism during playback of a conventional VTR, which includes a cylinder motor 2 that drives a rotary head 8 and a first frequency generator that detects the rotational speed of the cylinder motor 2. 3, a phase detector 4 that detects the rotational phase of the cylinder motor 2, and a phase detector 4 that detects the rotational phase of the cylinder motor 2;
a first frequency discriminator 40 for detecting an error in the output signal of the frequency generator 3 with respect to a reference period; and a reference signal generator 4.
2, a first phase comparator 41 for detecting a phase error between the rotational phase signal obtained from the phase detector 4 and the reproduced reference signal obtained from the reference signal generator 42; a first adder 43 that mixes the phase error output of 41 and the speed error output of the first frequency discriminator 40; a first amplifier 44; and a first drive circuit 12 that drives the cylinder motor 2. , a capstan motor 6 that runs the magnetic tape at a constant speed, a second frequency generator 7 that detects the rotational speed of the capstan motor 6, and the magnetic tape 1.
a control head 5 that detects a control signal recorded at the lower end of the second frequency generator 7; a second frequency discriminator 45 that detects an error in the output signal of the second frequency generator 7 with respect to a reference period; A tracking monomulti circuit 46 whose delay time is varied by a variable resistor 50 triggered by the output signal of 42 detects the phase error between the control signal obtained from the control head 5 and the output signal of the tracking mono multicircuit 46. a second adder 48 that mixes the phase error output of the second phase comparator 47 and the speed error output of the second frequency discriminator 45; An amplifier 49 and a second drive circuit 13 that drives the capstan motor 6.

The operation of the VTR configured as described above will be briefly explained using the configuration diagram shown in FIG. 10 and the timing chart of the main parts shown in FIG. 11.

111mN is the output waveform of the reference signal generator 42 in FIG. .

The trapezoidal wave signal of FIG. 11O is an internal waveform of the first phase comparator 41, and is the phase reference signal of the cylinder motor triggered by the rising edge of FIG.
The rotary phase signal obtained from the phase detector 4 of FIG. 1, that is, the falling edge of FIG. is mixed with the speed error signal by the first adder 43, and is mixed with the speed error signal by the first adder 43, and then
is supplied to the drive circuit 12 of. Therefore, the cylinder motor, that is, the rotary head 8 rotates in phase synchronization with the reference signal shown in FIG. 11N.

Figure 11 Q is the tracking seven-way multi-circuit 4 in Figure 10.
Figure 11 is a charging/discharging waveform of a capacitor (not shown) in Figure 6, triggered by the rising edge of Figure 11,
By changing the time constant with the variable resistor 50 shown in the figure,
The delay time can be varied.

11R is the output waveform of the tracking monomulti circuit 46, the trapezoidal wave signal of FIG. 11S is the internal waveform of the second phase comparator 47 of FIG. 10, and the falling edge of FIG. The capstan motor phase reference signal triggered by the control rad 5 in FIG.
The hold signal (not shown) sampled by the rising edge of T in FIG. 11 and the speed error signal obtained from the second frequency discriminator 45 in FIG. The mixture is mixed by an adder 48 and sent to the second drive circuit 13 via a second amplifier 49.
is supplied to Therefore, the capstan motor 6 is
It rotates in phase synchronization with the output signal of the tracking monomulti circuit 46 shown in FIG. 11R, which is obtained by phase-shifting the reference signal shown in FIG. 1N.

As described above, during VTR playback, by synchronizing the phases of the rotary head 8 and the playback control signal (Fig. 11), the rotary head 8 can optimally track the trunk recorded on the magnetic tape 1. .

Problem to be Solved by the Invention If the format 1 of the tracks recorded on the magnetic tape is compatible, the variable resistor 50 may be a fixed resistor, but if the magnetic tape is damaged due to environmental changes such as temperature changes. Other VTs that have expanded or contracted or have mechanical errors.
When reproducing a tape recorded in R, it is necessary to change the tracking state during reproduction, that is, the phase relationship between the rotary head and the reproduction control signal. For this purpose, the variable resistor 50 shown in FIG. 10 is necessary. Additionally, this variable resistor needs to be a volume with a click point to release it to the user.

Generally, the resistance value at the click point of a volume with a click point varies, and in order to correct the variation, another variable resistor is required. Therefore, conventional VTRs not only require adjustment volume for tracking, but also require improvements in operability, ie, user experience.

Means for Solving the Problems In order to solve the above-mentioned problems, the magnetic recording and reproducing apparatus of the present invention has a magnetic recording and reproducing apparatus in which a frequency-modulated wave signal is recorded by a rotating head, and a control signal having a constant period is recorded by the control head. When reproducing a recorded signal from a recorded recording medium, an error with respect to a reference phase of a phase difference between a head switching signal indicating the rotational phase of the rotary head and the reproduced control signal is detected, and based on the error signal. A magnetic recording/reproducing device for controlling the rotation of a motor for running the recorded recording medium, the magnetic recording/reproducing device comprising: a tracking variable means for varying the reference phase; and a frequency modulated wave signal reproduced from the recorded recording medium. sampling means for sampling a signal based on the head switching signal at each constant phase, and a plurality of sampling data obtained by the sampling means when the reference phase is varied at constant intervals by the tracking variable means. A comparison means for performing a comparison, a calculation means for determining a difference between the consecutive sampling data and comparing the differences, and a calculation means for calculating the difference between the data N times (N≧2, N is an integer) consecutively by the comparison means and the calculation means. a selection means for selecting detection when the difference between the two is within a certain value; a data storage means for taking in a reference phase of the tracking variable means for the sampling data obtained by the selection means; and means for sending the reference phase obtained as a final reference phase to the variable tracking means.

The above-described structure of the present invention provides stability even when the magnetic tape expands and contracts due to environmental changes such as temperature changes, and even when tapes with deteriorated compatibility are recorded on other VTRs with mechanical errors. It is possible to obtain a magnetic recording/reproducing device that realizes an auto-tracking function.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a VTR having an auto-tracking function according to an embodiment of the present invention, which drives two pairs of rotary heads 8.9 for recording and reproducing video signals and audio signals, respectively. Cylinder motor 2 and tape 1
II? A microprocessor 10 that realizes an auto-tracking function, and a first drive circuit 12 that drives the cylinder motor 2 by a signal output from the microprocessor 10 via a first analog signal output terminal 27. , a second drive circuit 13 that drives the capstan motor 6 by a signal output from the microprocessor 10 through a second analog signal output terminal, and a reproduction envelope signal obtained from the rotary head 8.9. amplification circuits 14 and 16 that amplify the signals, respectively, and a detection circuit 1 that peak-detects the amplified reproduction envelope signal.
5.17 and the detection output of its detection circuit 15.17 are input, and the detection circuit 17 is controlled by a signal that detects whether or not an audio signal is recorded. A switch circuit 18 selects the output of the detection circuit 15 when the level is below a certain value, and selects the output of the detection circuit 17 when an audio signal is recorded. The entire structure is composed of a signal output from the microprocessor 10 via the third analog signal output terminal 26 and a comparator 19 to which the signal is input. generator 3, first phase detector 4 and control head 5
, the second frequency generator 7 and the output of the comparator 19 are connected.

The inside of the microprocessor 10 includes a register 100 for storing data and a random access memory (indicated by the abbreviation "RAM" in the figure, hereinafter referred to as R).
AM) 200, and a 16-bit arithmetic unit (A in the figure) that executes arithmetic and logical operations on digital data.
The ALU 300 (indicated by the abbreviation LU (hereinafter abbreviated as ALU)) stores instructions to be executed sequentially, and based on the instructions, the register 100, the RAM 200, and the ALU 300 are stored via the control bus 450. The instruction execution circuit that controls the operation (in the figure, P
400 (indicated by the abbreviation LA), and a 17-bit time base counter (indicated by TB in the figure) that counts down the reference clock signal applied to the clock terminal 20.
C) 500 and a counter bus 550, the count data of the time base counter 500 is supplied to the register 100, the RAM 200. A capture register block (indicated by the abbreviation CAPREG in the figure) 700 that is sent to a data bus 600 connected to the ALU 300, and first to fifth input terminals 21, 22, 2
3, 24, and 25, and transfers the count data of the time base counter 500 to the capture register block 700 when the edges of six types of capture symbols, each having a different generation source, arrive. 800 (indicated by the abbreviation CAPTIICTIIL).

Further, the reference clock signal applied to the clock terminal 20 is transmitted to the instruction execution circuit 4 via a timing generator (indicated by the abbreviation TG in the figure) 900.
00, and the data bus 600 includes a read-only memory (indicated by the abbreviation ROM in the figure, hereinafter abbreviated as ROM) 1000. I10 boat 1
100° first ODA converter 1200. A second DA converter 1300 and a third DA converter 1400 are connected, and furthermore, the RAM 200 and the ROMlooO each have an address decoder 250.1050.

Note that the capture controller 800 and the capture register block 700 take in count data from the time base counter 500 when the edge of the capture signal arrives, and the minimum decomposition accuracy is higher than the instruction execution cycle, and A capture circuit is configured to send the result to the ALU 300, the register 100, or the RAM 200 according to a specific instruction from the ALU 300.

Regarding the VTR configured as described above, the configuration diagram shown in FIG. 1 and the capture controller 8 shown in FIG.
The operation will be explained with reference to a specific configuration diagram of 00 and a timing chart of the main parts shown in FIG.

First, FIG. 2 shows the capture controller 800 of FIG.
is a logic circuit diagram showing a specific example of the configuration, and control units 810 to 850 having the same configuration are connected to the first to fifth input terminals 21, 22, 23° 24.25, and the control units 810 to 850 have the same configuration. Each of the units 810-850 has a common reference clock input terminal 801 and a data transfer lock input terminal 802 to the capture register block 700, and also has individual reset terminals 811-850.
51, individual flag output terminals 812-852, and individual data transfer terminals 813-853.

Next, FIG. 3 shows a control unit 850 that constitutes the third DA converter 1400 and comparator 11 in FIG. 1 as well as the capture controller 800 shown in FIG.
3A shows a timing chart for explaining the operation of an AD conversion mechanism constituted by a capture register block 700, and FIG. 3A shows a clock signal waveform applied to the clock terminal 20 in FIG. B is a signal waveform obtained by frequency-dividing the signal waveform of FIG. 3A, and this signal is used as a reference clock signal at the reference clock input terminal 8 of FIG.
01.

Furthermore, FIG. 3C shows the count clock signal waveform of the time base counter 500, which is constituted by a synchronous counter whose unit stage is a master-slave type flip-flop. ), the output of the master part of the flip-flop of each unit stage changes, and the output of the slave part changes at the trailing edge.

The third diagram shows a clock signal waveform for data transfer created from the signal waveforms of FIGS. 3A and 3B, and is supplied to the data transfer a clock input terminal 802 of FIG.

Furthermore, FIG. 3E is an analog output signal of the third DA converter 1400 applied to the non-inverting input terminal of the comparator 11 in FIG. 1, and FIG. 3F is an analog output signal output from the detection circuit 10 in FIG. This is an output signal obtained by comparing the peak detection signal of the regenerated enherobe signal and the signal of FIG. 3E by the comparator 11.

Now, when the signal waveform shown in FIG. 3F is applied to the fifth input terminal 25 in FIG.
'', the output level of the NAND gate 854 transitions to ``1'' as shown in FIG. When the output level of the NAND gate 856 shifts to "1" as shown in FIG. As in, it shifts to "1". Each of the NAND gates 854, 855° 856 is connected to another NAND gate as a pair.
Since it forms a bistable circuit with an ND gate, when the output level shifts to "1", it maintains that state until another NAND AD converter cut signal is applied.
When the output level of the AND gate 856 shifts to "1", the output level of the paired NAND gate 857 shifts to "1".
0", and the output level of the AND gate 858 also becomes "0".
”, so the NAND gate 854.855
The output level of returns to "0".

In this way, when the leading edge of the external signal arrives at the fifth input terminal 25, the leading edge of the external signal arrives at the second data transfer terminal 8.
53, a signal waveform as shown in FIG. 3J is sent through an AND gate 859, and this signal causes count data to be transferred from the time base counter 500 in FIG. 1 to the capture register block 700.

That is, in the signal waveform of FIG. 3F, the timing at which the level shifts from "0" to "1" depends on the potential of the output signal of the detection circuit IO of FIG. The count data of the time base counter 500 also depends on the potential of the output signal of the detection circuit 10.

The output signal of the NAND gate 856 is sent to the flag output terminal 852 and is used as a capture flag signal indicating that the time base counter 5000 count data has been transferred.
1, a reset signal is applied after software (program) confirms that this capture flag is set.

Next, FIG. 4 is a configuration diagram showing a specific example of the capture register block 700, in which each data input terminal is connected to the DO terminal to the D7 terminal, and the data output terminal is connected to the Q1 terminal to the Q8i terminal. The unit register 750 is composed of eight memory cells, and the unit register 750 is composed of 16 memory cells whose data input terminals are connected to Do terminals to D15 terminals, and whose data output terminals are connected to Q1 terminals to QL6 terminals. unit register 740.7
30 and a unit register 720°710 constituted by 16 memory cells whose data input terminals are connected to the D1 terminals to D16 terminals, respectively, and whose data output terminals are connected to the Q1 terminals to Q16 terminals. There is.

Note that each unit register 710 to 750 has two control signal input terminals, a read terminal 711 and a read terminal 711.
~751 are respectively applied with data transfer signals from the capture controller 800 shown in FIG. The output side of the register is activated, and a select signal for reading is applied to the data bus 600 in FIG. 1 via the data output terminals Q1 to Q16.

Now, the transfer control signal from the data transfer terminal 853 in FIG. 2 is supplied to the read terminal 751 in FIG. However, in the embodiment of the present invention shown in FIG. 1, the scan counter for conversion and the register for storing the conversion result are provided as a capture circuit, so that the hardware is not required. The burden will be much lighter.

By the way, in FIG. 4, unit registers 730 to 750
The connection position between the data input terminal and the data output terminal is shifted by one bit for the following reason.

First, the input section of the 8-bit unit register 750 has a first
The same 8-bit count data as that supplied to the DA converter 1400 in the figure is supplied, but in order to increase the sampling rate, the DA converter 1400 and unit register 750 are supplied with count data closer to the LSB (least significant bit). It is preferable to supply count data for the time base counter 500.

Regarding the unit registers 730 to 740, the LSB of the time base counter 500 and the LSB of the unit register are
Although the SBs are matched, the unit registers 710 to 720
For the unit registers 730 to 740, the data input terminal is shifted to the left by one bit so that twice as many intervals can be processed at once with the same number of bits as the unit registers 730 to 740.

With such a bit shift configuration of the unit registers 730 to 740, for example, the frequency of the reference clock signal can be changed by 2.
When MHz is selected, count data with a resolution of 500 ns is obtained from the unit registers 730 to 740, while count data with a resolution of 1 usec is obtained from the unit registers 710 to 720.
count data with a resolution of 30)
The arrival period of an external signal having a frequency of about 1z can be measured in one process.

The operation of the VTR having the auto-tracking function configured as described above will be explained with reference to the configuration diagram shown in FIG. 1, the operation flowcharts and operation waveform diagrams shown in FIGS. 5 to 8.

FIG. 5 shows a control means for operating the capstan motor 6 by processing the count data obtained when the leading edge of the control signal recorded on the magnetic tape arrives as magnetic tape running phase detection data. 2 is a flowchart showing an example in which phase control during reproduction is realized by a program built into the microprocessor 10 of FIG. 1.

Regarding the flowchart in Figure 5, the conventional VT in Figure 11
This will be explained with reference to the operation waveform diagram of R.

Processing blocks 451, 453 and branch 452 in FIG.
A reference signal for VTR playback, that is, a signal corresponding to N in FIG. 11 is created by R in the processing block 453.
EF and TR'M are constants, and are the repetition period of the reference signal and the center value of the tracking thick amount, respectively.
Memory 1 stores the count value corresponding to the leading edge of the next reference signal, that is, the time corresponding to the rising edge of FIG. 11N, and memory 2 stores the tracking shift amount, that is, the time corresponding to the falling edge of FIG. 11R. is written.

As will be explained in detail later, the amount of change in the tracking shifter amount from the center value is written in the memory 3 for the auto-tracking function.

Processing blocks 454 and 456 and branch 455 then generate a phase reference signal for the capsun motor, that is, S in FIG.
A trapezoidal wave signal corresponding to is created, and processing block 4
54 and branch 455, it is determined whether the count value of the time base counter 500 in FIG. 1 does not exceed the tracking thick amount written in the memory 2,
If it exceeds the 11
A count value corresponding to the boundary point between the high level (hereinafter abbreviated as H level) period and the slope section of the trapezoidal wave signal in FIG. S is written. Therefore, the TPZ in processing block 456
is a constant corresponding to the H level period.

Next, in branch 457, a check is made to see if a reproduction control signal has arrived. This indicates that the capture controller 800 has transferred the count value of the time base counter 500 to the capture register block 700 at the leading edge of the playback control signal applied to the third input terminal 23 of the microprocessor 10 in FIG. This can be done by checking whether the CTL flag is sent. If the CTL flag is set, processing next proceeds to block 458 where the accumulator (hereinafter A
(abbreviated as cc) via the register file, i.e. the first
The count value latched in the capture register block 700 shown in the figure is transferred to the memory 5.

After checking the NL flag in branch 459, processing block 460. Branch 461 determines whether the time when the control signal arrives is earlier than the time written in memo U4, that is, the boundary point between the H level section and the slope section in FIG. 11S. If yes, proceed to processing block 463 and set Ace to a value corresponding to the H level in FIG. 11S; if not, proceed to processing block 462.

Processing block 462 and branch 464 now check whether the arrival time of the control signal has passed the slope section of FIG. 11S. Processing block 46
KEI SHA in 2 is a count value (constant) corresponding to the slope section of FIG. 11S. If the incline section has been passed, the process proceeds to processing block 465 where the first
A value corresponding to the low level (hereinafter abbreviated as L level) of the trapezoidal wave signal in FIG. 1S is set.

Then, processing blocks 469 and 470 cause Acc
The value corresponding to the phase error left behind is written into the memory 6, and the NL flag is set.

If the control signal 48 has not arrived in branch 457, that is, if the CTL flag is not set, processing block 466 and branch 467 change the count value of time base counter 500 to the 11th
Check whether the time corresponding to the boundary point between the slope section and the L level section in FIG. , proceeding to processing block 469 .

As described above, the phase control of the capsun motor 6 is performed.

Next, the auto-tracking operation will be explained using the flowcharts shown in FIGS. 6 and 8 and the operation waveform diagram shown in FIG. 7.

FIG. 6 shows a reproduction envelope signal obtained from the rotary head 8 or 9 of FIG. 2 is a flowchart showing an example in which a means for importing digital data AD-converted into a memory is realized by a program built into the microprocessor 10 of FIG. 1.

FIG. 7 shows a head switching signal for the pair of rotating heads 8 or 9 attached to the cylinder motor.
The figure shows the reproduced envelope signal obtained from the rotary head 8 or 9, and FIG. That is, the signal in FIG. 7M is the signal applied to the inverting input terminal of the comparator 19 in FIG. 1, and as explained above, the signal in the capture controller 800. The signal is AD converted by the capture register block 700 or the like.

Branches 401, 405, and 410 in FIG. 6 are processes for branching the flow according to the value of the state variable A set in the RAM, that is, the memory.

First, when A=O, process bronch 4 by branch 401.
02, the head switching signal (H5W, K in FIG. 7, hereafter H3W) is input to the I10 port 1100 in FIG.
After the signal level of the H3W signal (abbreviated as signal) is taken into Acc, it is detected that the H3W signal is at the 1,0 level, and the state variable A is set to 1 by processing block 404.

When A=1, processing block 40 is executed by branch 405.
6, the signal level of the H3W signal is loaded into the ACC, a rising edge of the H3W signal is detected in branch 407, and the process proceeds to processing block 408, where approximately 3 m
Set a timer to detect after s. This is because, as can be seen from the envelope signal shown in Figure 7, the envelope signal output obtained from the rotating head is not constant due to variations in the head, non-linearity of the recording track, etc., so it is a point to compare the envelope output. This is to ensure that the signal is always at the same position, approximately 13 m5 after the rising edge of the H5W signal.

Further, the timer setting is realized by using the time base counter 500 shown in FIG. 1, or by using a soft counter that is determined based on the number of times a specific command on the program is passed.

Processing then proceeds to block 409 where state variable A is incremented by two.

When A=2, processing block 41 is executed by branch 410.
1, and it is determined whether the timer that entered when Δ=1 has completed counting.

If yes, the process proceeds to processing block 412, and as explained in FIGS. 3 and 4, the register file containing the digital value obtained by AD converting the signal (M in FIG. 7) obtained by detecting the peak of the reproduced envelope signal (M in FIG. 7). The count value latched in the capture register block 700 in FIG. 1 is transferred to the memory 7.

In other words, the register file data approximately 8 ms after the rising edge of the H3W signal (R, R2 in FIG. 7) is taken into the memory 7. Next, in processing block 413, state variable A is reset to zero.

By repeating the above flow, it is possible to always capture the amplitude level of the envelope signal after a certain period of time from the rising edge of the H3W signal into the memory.

Next, the main flow of auto tracking is explained in Part 8.
This will be explained using the flowchart shown in the figure.

First, branch 414 determines whether auto tracking is being executed, and if yes, proceeds to branch 418,
If not, proceed to branch 415.

In branch 415, it is determined whether the VTR is in recording mode or playback mode, and in the playback mode, the process proceeds to branch 416, where it is determined whether or not the first switch circuit 31 of FIG. (Switch ON
(If so), proceed to processing block 41T, clear variable B set on memory, memory 6, and memory 3, set variable C to 15, and proceed to branch 420. Also, if no in branch 415 and branch 416, the program moves to the next program.

Next, depending on the value of state variable B, branches 420, 423.
430.444 branches the flow.

First, when B is O, the process proceeds to processing block 421 via branch 420, and in processing block 412 of the flow shown in FIG.
Store in. Then, in the processing program 722, the state variable B is incremented to 1.

When B is 1, processing block 42 is executed by branch 423.
Proceeding to step 4, in order to shift the tracking shifter amount by 1 ms, the value corresponding to the tracking fJ l m s is subtracted from the data in the memory 3 described in the explanation of FIG.

The process then proceeds to processing block 425 where the variable RI is set to 2.
7, the value of variable C is decremented by 1 in processing block 426, it is determined in branch 427 whether the value of variable C has become 1, and if yes, processing block 42
At step 9, state variable B is set to 3; otherwise, at process block 428, state variable B is set to 2.

When B is 2, processing block 43 is executed by branch 430.
1, the variable RI is decremented by 1, and then in branch 432 it is determined whether the variable RI is 0 or not.

That is, using the variables, the processing blocks 425, 4
31 and branch 432 implement a soft timer, which delays the time required for the program to pass through processing block 431 twice. This means that the tracking shifter amount is set to 1ms in processing block 424.
This is because it takes time for the capstan motor 6 shown in FIG. 1 to complete phase pull-in after shifting.

After a predetermined time has elapsed, the process proceeds to processing block 433, and the amplitude level of the reproduction envelope at R in FIG. 7, approximately 8 ms after the rising edge of the H3W signal after changing the tracking shifter amount, is captured by the flow in FIG. 6. The data in the memory 7 is transferred to the ACC, and the data and processing block 421 are processed approximately 8 ms from the rising edge of the H3W signal before changing the tracking thick amount.
The difference between the amplitude level of the subsequent reproduced envelope signal and the captured data in the memory 6 is calculated.

Then, in branch 434, it is determined whether the value remaining in Acc is positive or negative. If it is positive, that is, if the envelope signal level after changing the tracking shifter amount is higher, processing block 435 transfers the amplitude level of the reproduced envelope signal after changing the tracking shifter amount to the memory 6, and also transfers the amplitude level of the reproduced envelope signal after changing the tracking shifter amount to the memory 6. The data in the memory 3 in which the shift amount is stored is transferred to the memory 8.

In other words, memory 6 and memory 8 contain H3W up to that point.
Approximately 8 ms after the rising edge of the signal, that is, the maximum envelope signal level at R in FIG. 7 and the tracking shift amount at that time are stored.

Next, the process proceeds to processing block 436, and the difference between the amplitude level of the playback envelope after changing the tracking thick amount, that is, the value obtained by adding 1 to memory 7, and memory 6 is calculated, and in branch 437, the difference is determined to be a positive number of 2 or less. It is determined whether or not.

That is, it is determined whether the absolute value of the difference in the amplitude level of the reproduction envelopes of the memory 6 and the memory 7 that have been successively captured is within 1. If not, the process advances to processing block 441; if yes, the process advances to processing block 438, where the memory 10 is incremented.

Next, in branch 439, when memory 10 is greater than 3, the process proceeds to processing block 441, when it is less than 3, the process proceeds to processing block 442, and when it is 3, processing block 440 adds 3 to the tracking shifter amount memory 3. Transfer to memory 11. That is, when the difference in the amplitude level of the reproduction envelope is within 1 three times in a row, the first consecutive tracking shift amount is stored.

FIG. 9 is a graph showing the relationship between the tracking shifter amount and the amplitude level of the entropy signal when the tracking amount is varied during playback of a triple recording tape. In the case of 3x recording tape, mark! # Although the trunk width is narrower than that of the recording tape, since both use heads of the same width, the reproduced envelope signal level becomes a waveform with a flat part as shown in FIG. Furthermore, when considering the image quality and the SN ratio, the best point is near the click point in FIG. 9, that is, the point where it starts to become flat. Therefore, processing blocks 436, 437° 438, 439 on a triple recording tape
, 440 provides the best tracking position.

Next, a processing block 441 clears the memory 10, and a processing block 442 transfers the memory 7 to the memory 6. Also, in processing block 443, state variable B
is set to 1.

When B is 3, processing block 44 is executed by branch 444.
5, the data in the memory 11 in which the best tracking shifter amount for R in FIG. 7 is stored is transferred to Ace.

Next, in branch 446, it is determined whether the memory 11 is 0 or not. If yes, the data in the memory 8 storing the tracking thick amount when the amplitude level of the reproduced envelope signal reaches the maximum is transferred to the memory 3; if not, the data in the memory 11 is transferred to the memory 3. and processing block 44
At step 9, variables B, C and memory 10 are cleared.

Through the above flow, the tracking shifter amount is shifted 15 times in 1 ms increments, and the playback envelope signal level is compared each time, and the first tracking shifter amount for which the difference in the three consecutive playback envelope signal levels is within 1 is selected as the final tracking shifter amount. tracking shifter amount.

However, if the above tracking shift amount is not detected, the tracking thick amount that is the maximum value of the reproduction envelope signal level approximately 3 ms after the rising edge of the H3W signal (R in Figure 7) among the 15 times is set as the final tracking shift amount. Let the tracking thickness be the amount of tracking thick.

Effects of the Invention As is clear from the above description, in the magnetic recording and reproducing device having an auto-tracking function of the present invention, a frequency-modulated wave signal is recorded by a rotating head, and a control signal of a constant period is recorded by a control head. When reproducing a recorded signal on a recorded recording medium (represented by magnetic tape 1 in the embodiment), a head switching signal (H3W signal) indicating the rotational phase of the rotary head and the reproduced control signal are generated. (in the embodiment, the phase control means is configured according to the flowchart of FIG. 5), and based on the error signal, the motor for driving the recorded recording medium (in the embodiment) is detected. A magnetic recording/reproducing device that controls the rotation of a capsun motor 6 (in the example, represented by a capsun motor 6), the tracking variable means for varying the reference phase (in the embodiment, the tracking variable means is controlled by the processing block 424 in FIG. 8). a signal based on the frequency modulated wave signal (expressed as a reproduction envelope signal in the embodiment) reproduced from the recorded recording medium.
In the embodiment, the sampling means (in the embodiment, the sampling means is configured according to the flowchart of FIG. 6) samples the head switching signal (represented by a detection signal) at a constant phase with the head switching signal, and the tracking variable means. Comparison means (in the embodiment, processing blocks 433 and 435 and branch 4 in FIG.
34), a calculating means (consisting of the processing block 436 and branch 437 in FIG. 8 in the embodiment) for determining the difference between the consecutive sampling data and comparing the differences; and the comparing means. and N by calculation means.
detecting means (consisting of the branch 437 in FIG. 8 in the embodiment) for detecting that the difference between the data is within a certain value repeatedly (N≧2, N is an integer); Selection means for selecting the first sampling point detected by the detection means (in the embodiment, processing block 4 in FIG. 8)
38°441 and branch 439),
Data storage means (in the embodiment, processing block 435 in FIG. 8
, 440), and means for sending the reference phase stored in the data storage means to the tracking means as the final reference phase (in the embodiment, processing blocks 445, 447, 448 and branches in FIG. 8). 446), and is characterized by the fact that the magnetic tape expands and contracts due to environmental changes such as temperature changes, or is recorded on other VTRs that have mechanical errors. It is possible to obtain a magnetic recording/reproducing device that realizes a stable auto-tracking function even for tapes with degraded compatibility. Of course, since there is no need for an adjustment volume like in a conventional VTR, operability can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a magnetic recording/reproducing device having an auto-tracking function in an embodiment of the present invention, FIG. 2 is a specific logic circuit diagram of the capture controller 800 shown in FIG. 1, and FIG. A timing chart explaining the circuit operation shown in the figure, Fig. 4 is a capture registration screen 700.
Fig. 5, Fig. 6, and Fig. 8 are flowcharts showing the operation of the main parts of Fig. 1, Fig. 7 is a timing chart to explain the flowchart of Fig. 6, and Fig. 9 is a tracking diagram. A graph showing the relationship between the shifter amount and the playback envelope signal level. Fig. 10 is a block diagram showing the configuration of the servo mechanism during playback of a conventional VTR. Fig. 11 is a graph showing the operation of the main parts of Fig. 10. This is a timing chart. 1...Magnetic tape, 2...Cylinder motor, 6...Capstan motor, 19...
... Comparator, 100 ... Register, 2
00...RAM, 300...ALU,
400... Instruction execution means, 500...
Quim base count, 700... Capture register controller, 800... Capture controller, 1000... ROM, 1400
...DA converter. Figure 2
5 m5

Claims (1)

[Claims] A head switching signal indicating a rotational phase of the rotary head when reproducing a recorded signal of a recorded recording medium in which a frequency modulated wave signal is recorded by a rotary head and a constant period control signal is recorded by the control head. In a magnetic recording and reproducing device that detects an error with respect to a reference phase of a phase difference between the reproduced control signal and controls the rotation of a motor for running the recorded recording medium based on the error signal, the reference phase is variable. tracking variable means for sampling a signal based on the frequency modulated wave signal reproduced from the recorded recording medium at a constant phase with the head switching signal; a comparing means for comparing the magnitudes based on a plurality of sampling data obtained by the sampling means when the data is varied; a calculating means for determining the difference between the consecutive sampling data and comparing the differences; Detection means for detecting that the difference between the data is a constant value N times (N≧2, N is an integer) consecutively using arithmetic means, and selection for selecting the first sampling point detected by the detection means. means, data storage means for taking in a reference phase of the variable tracking means for the sampling point obtained by the selection means, and sending the reference phase stored in the data storage means to the variable tracking means as a final reference phase. A magnetic recording/reproducing device comprising means.