JPH02218046A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To accomplish the excellent response of the tracking action of even a tape whose interchangeability is deteriorated by modulating a reference speed according to the changing quantity of a phase when the phase of a reference signal is changed by a tracking means. CONSTITUTION:When a capstan FG signal is inputted in an input terminal 24, a counted value is latched in a capture register block 700 from a time base counter 500 through a capture controller 800 and transferred to a memory. After obtaining the difference of the memory where data to which 1/2 of a measured range is added is stored from the expected value (counted value) of the arrival time of the FG signal, speed error data is stored in the memory. Next, the state of a tracking (TR) flag is detected. When the TR is rising, rotating speed is made higher by the ratio of a tracking variable step quantity DELTAT to the cycle T of a head switching signal, DELTAT/T, and when the TR is down, the rotating speed is made lower by DELTAT/T. Thus, the speed of a capstan motor 6 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a magnetic recording/reproducing device having a tracking means, and particularly to a device realized at low cost using a microprocessor.

Conventional technology In recent years, the spread of microprocessors has been remarkable.

It has come to be used in many household electrical products. Home video tape recorders (hereinafter abbreviated as VTRs) are no exception, and are at the heart of the system, including the control of the loading mechanism that pulls out the magnetic tape from the cassette and wraps it around the rotating head, and the timer reservation system. Microprocessors are actively used. However, precision rotation control devices for cylinder motors that drive rotating heads and capstan motors that run magnetic tape at a constant speed require complex judgment operations and rapid processing of detection signals, so microprocessors are not used. have relied on specialized hardware.

FIG. 8 is a block diagram showing the configuration of a servo mechanism during playback of a conventional VTR, which includes a cylinder motor 2 that drives the one-rotation head 8, and a first frequency power generator 813 that detects the rotational speed of the cylinder motor 2. , a phase detector 4 that detects the rotational phase of the cylinder motor 2, and a phase detector 4 that detects the rotational phase of the cylinder motor 2;
a first frequency discriminator 40 for detecting an error in the output signal of the frequency generator 3 with respect to a reference period; and a reference signal generator 4.
2, the rotational phase signal obtained from the phase detector 4, and 0.
1. A first phase comparator 41 for detecting a phase error with the reproduction base S signal obtained from the reference signal generator 42;
a first adder 43 that mixes the phase error output of the phase comparator 41 and the speed error output of the first frequency discriminator 40;
and a first amplifier 44 that amplifies the output of the first adder 43.
The first drive circuit 12 drives the cylinder motor 2 with the output of the first amplifier 44, the capstan motor 6 drives the sharpening tape at a constant speed, and the rotational speed of the capstan motor 6 is detected. a second frequency generator 7; a control head 5 that detects a control signal recorded on the lower end of the mountain tape 1; and a control head 5 that detects an error in the output signal of the second frequency generator 7 with respect to a reference period. 2 frequency discriminator 45, a tracking mono multi-circuit 46 whose delay time is varied by a variable resistor 50 triggered by the output signal of the reference signal generator 42, and a control signal obtained from the control head 5 and the tracking mono A second phase comparator 47 that detects a phase error with the output signal of the multi-circuit 46, and mixing of the phase error output of the second phase comparator 47 and the speed error output of the second frequency discriminator 45. a second adder 48;
a second amplifier 49 that amplifies the output of the second adder 48;
The second drive circuit 13 drives the Yabustan motor 6 with the output of the second amplifier 49.

The operation of the VTR constructed as described above will be briefly explained using the timing chart of the main parts shown in FIG.

Q in FIG. 9 is the output signal waveform of the reference signal generator 42 in FIG. 8, and this signal Q is supplied to the first phase comparator 41 and the tracking monomulti circuit 46 as a reference signal during VTR playback. be done. The trapezoidal wave signal R in FIG. 9 is the internal waveform of the first phase comparator 4I, and is the phase reference signal of the cylinder motor triggered by the rising edge of the signal Q. This phase reference signal R is sampled by the falling edge of the rotating phase signal (S in the whistle 9 diagram) obtained from the phase detector 4, and is obtained from the hold signal (not shown) and the first frequency discriminator 40. The speed error output is mixed in a first adder 43 and supplied to the first drive circuit 12 via a first amplifier 44. Therefore, the rotary head 8 driven by the cylinder motor 2 rotates in phase synchronization with the reference signal Q shown in FIG. T in FIG. 9 is a charging/discharging waveform of a capacitor (not shown) in the tracking monomulti circuit 46, which is triggered by the rising edge of the reference signal Q, and by changing the time constant with the variable resistor 50. The delay time can be varied. 9th
U in the figure is the output signal waveform of the tracking monomulti circuit 46, and the trapezoidal wave signal V in FIG. 9 is the internal waveform of the second phase comparator 47. This is a phase reference signal for the motor 6.

This phase reference signal V is sampled by the rising edge of the reproduction control signal (W in figure r49) obtained from the control head 5, and its hold signal (not shown) and the velocity error output obtained from the second frequency discriminator 45. are mixed in a second adder 48 and supplied to the fJ2 drive circuit 13 via a second amplifier 49. Therefore, the capstan motor 6 rotates in phase synchronization with the output signal U of the tracking monomulti circuit 46, which is obtained by shifting the phase of the reference signal Q. As described above, during VTR reproduction, by synchronizing the phases of the rotary head 8 and the reproduction control signal W, the rotary head 8 can optimally track the tracks recorded on the sharpening tape 1.

Problems to be Solved by the Invention If the formats of the recorded tracks are compatible, the variable resistor 50 may be a fixed resistor, but due to environmental changes such as temperature changes, the other Vs that have expanded or contracted or have mechanical errors.
When reproducing a tape recorded with TR, it is necessary to change the tracking state during reproduction, that is, the phase relationship between the rotary head and the reproduction control signal. For this purpose, the variable resistor 50 is necessary, but the capstan motor 6
In this control system, the speed modulation sensitivity seen from the second phase comparator 47 is necessarily small, so even if the resistance value of the variable resistor 50 is changed, it takes some time to reach the target tracking state. Furthermore, in order to make this variable resistor 50 available to the user, there is a need to improve operability, that is, ease of use, so recently, the variable resistor 50 is equipped with an automatic system that monitors the playback output signal from the rotary head 8 and automatically draws it to the optimal tracking position. - Although a tracking function has been proposed, the current situation is that it takes a long time to settle due to the above reasons.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a reliable recording and reproducing apparatus that can provide a good response in tracking operations even for tapes with degraded compatibility.

Means for Solving the Problems In order to solve the above-mentioned problems, the magnetic recording and reproducing device of the present invention provides a magnetic recording and reproducing device that detects a speed error of a rotational speed detection signal obtained from a capstan motor with respect to a basic speed, and a speed error of a rotational speed detection signal obtained from a capstan motor. In a magnetic recording and reproducing device that controls the rotation of the capstan motor using a phase difference between a control signal obtained from a magnetic medium and a reference signal produced by a tracking means, when the phase of the reference signal is changed by the toggling means, the amount of change is determined by the amount of change. Means for modulating the reference speed accordingly is provided.

Operation With the above-mentioned configuration, when the phase of the reference signal is changed by the tracking means, the reference speed is modulated according to the amount of change, and the magnetic tape is prevented from expanding or contracting due to environmental changes such as temperature changes, or mechanical errors. Fast and stable tracking operations can be performed even on tapes recorded with other VTRs with degraded compatibility, resulting in good responsiveness.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a VTR having tracking means according to an embodiment of the present invention, in which a cylinder motor 2 and a magnetic tape 1 drive a pair of rotary heads 8 and 9 for recording and reproducing video signals. a microprocessor 10 that controls the capstan motor 6 that drives the cylinder at a constant speed and realizes a variable tracking means;
a first drive circuit 12 that drives the capstan motor 6; a second drive circuit 13 that drives the capstan motor 6 from the signal l output from the microprocessor 10 via the second analog signal output terminal 28; The tracking up/down switch circuit 14 connected to the input terminal 26 of the microprocessor 100 for varying the tracking is connected to the input terminal 26 of the microprocessor 100, and the first
The outputs of the frequency'# type machine 3, the first phase detector 4, the control head 5, and the second frequency generator 7 are connected.

Inside the microprocessor 10, there are a register 100 for storing data iF, a random access memory (hereinafter abbreviated as RAM) 200, and a 16-bit arithmetic unit (ALU) that executes arithmetic and logical operations on digital data. ) 300 and instructions to be executed sequentially,
Based on the instruction, the register 100, RAM 200, and arithmetic unit 30 are sent via the control bus 450.
Instruction execution circuit (PLA) that controls the operation of 0
400, a 17-bit time base counter ITB (j) that counts down the reference clock signal applied to the clock terminal 20, and the count data of the time base counter 500 is supplied via the counter bus 550, and its output data is Register 100, RAM 2
00, a capture register block (CAPREG) sent to the data bus 600 connected to the arithmetic unit 300.
) 700 and the first to fifth input terminals 21 to 25, and when the edge of five types of capture signals, each having a different generation source, arrives, the count data of the time base counter 500 is transferred to the capture register block 700. There is a capture controller (PTRCTRL) 80018 that controls the data to be transferred and input. Further, the clock signal applied to the clock terminal 20 is supplied to the instruction execution circuit 400 via a timing generator (TG) 900. In addition, the data bus 600 includes a read-only memory c (abbreviated as ROM) 11000.
% input/output (I101 boat 1100, first DA converter 1200, and whistle 2 DA converter 1300 are connected, and furthermore, RAM 200 and ROM 3000 are separated by address decoder 250° and 1050°, respectively.

Note that the capture controller 800 and the capture register block 700 calculate the minimum resolution t from the time base counter 500 when the edge of the capture signal arrives.
00
Alternatively, it constitutes a capture circuit that sends data to the RAM 200.

Regarding the VTR configured in this way, the specific configuration diagram of the capture controller 800 shown in FIG.
The operation will be explained using the timing chart of the main parts outlined in the figure.

FIG. 2 is a logic circuit diagram showing a specific configuration example of the capture controller 800 shown in FIG. The control units 810-850 each have a common reference clock input terminal 803 and a data transfer lock input terminal 802 to the capture register block 700, and further have individual reset terminals 811-851 and individual flag input terminals. and output terminals 812-852.

It has individual data transfer terminals 813-853.

Figure 3 shows the capture controller 5800 shown in Figure 2.
Five controller units 810 to 850 make up the
This is a timing chart for explaining the operation of , where A in Fig. 3 is the clock signal waveform applied to the clock terminal 20 of rod 1, and B in Fig. 3 is a signal obtained by frequency-dividing the clock signal A. This signal is supplied to the reference clock input terminal 801 in FIG. 2 as a reference clock signal. In addition, C in the m3 diagram shows the count clock signal waveform of the time base counter 500, which is constituted by a synchronous counter with a master-slave type flip-flop as the ■ stage, and the leading edge with an arrow (@ At 1!1 (57 stage, 7 lip, 70 lip), the output of the master part changes, and at the trailing edge (trailing edge), the output of the slave part changes. This shows the clock signal waveform for data transfer generated from the reference clock signal B, which is supplied to the data transfer lock input terminal 802 in FIG. 2. E in FIG. These are capture signals inputted from input terminals 21 to 25 of.

Now, the capture signal E is input to the first input terminal 21 in FIG.
is input, after the leading edge arrives, the level of the reference clock signal B at the reference clock input terminal 801 changes to "NAND gate 8 at the time when the level shifts to the moon".
] As shown at F in FIG. 3, the output level of NAND gate 8 changes to [moon] and the level of signal B at the reference clock input terminal 801 shifts to rOJ. As shown in G in Figure 3, the signal from the reference clock input terminal 801 moves to the moon, and then the signal from the reference clock input terminal 801 @B.
When the level shifts to “1” again, NAND gate 8
The output level of 1G is "1" as shown in H2C in Figure 3.
to move to.

Each of the NAND gates 814, 815, and 816 constitutes a bistable circuit with another NAND gate to be paired with, so when the output level shifts to "1", another NAND gate is activated.
This state is maintained until a reset signal is applied to the gate side, but the output level of the NAND gate 816 is "1".
'', the output level of the paired NAND gate 817 shifts to rOJ, and the output level of the subsequent gate 818 also shifts to rOJ, so that the NAND gate 814
, the output level of 815 is returned to rOJ.

In this way, the leading edge of the capture signal E arrives at the first input terminal 21. Then, a signal waveform shown in 1 in FIG. 3 is sent to the data transfer terminal 813 via the palm gate 819, and this signal causes the count data to be transferred from the time base counter 500 to the capture register block 700 in FIG. Transfer takes place.

Note that the output signal of the NAND gate 816 is sent to the flag output terminal 812 and is used as a capture flag signal indicating that the count data of the time base counter 500 has been transferred, and this capture flag is sent to the reset terminal 811. After the software (program) confirms that it has been set, a reset signal is applied.

Next, FIG. 4 is a configuration diagram showing a specific example of the capture register block 700, in which each data input terminal is connected to the DO terminal to 015 terminal for inputting count data from the time base counter 500. The output terminals are composed of 16 memory cells connected to the Q1 terminal to Q16 terminal for data output to the data bus 600, and the data input terminals are DIS terminals for inputting count data. ~D1
Connected to 6 terminals.

The entire device is constituted by unit registers 730, 740, and 750, which are constituted by 16 memory cells whose data output terminals are connected to data output terminals Q1 to Q16. In addition, each unit register 710 to 750
have two control signal input terminals, read terminals 711 to 751 are respectively applied with data transfer signals from the capture controller 800 shown in Figure 2, and select terminals 712 to 752 are used to input command execution signals. A specific read command stored in the program storage area of the circuit 400 is used to output data by setting the output side of each unit register to an active state.
1 terminal ~ Q] data bus 600 of whistle 1 figure via si child
A select signal for reading is applied.

By the way, in FIG. 4, unit registers 730 to 750
The connection position between the data input terminal and the data output terminal is shifted by one bit for the following reason.

Regarding the unit registers 710 and 720, the LSB of the 1ζ time base counter 500 (7) is made to match the LSB of the unit register in order to improve the resolution of the timing of capturing the edge of the capture signal E, but for the unit registers 730 to 750, the LSB of the unit register is 710°720
The data input terminal is shifted to the left by one bit so that twice as many intervals can be processed at once with the same number of bits. With such a bit shift configuration of the unit registers 710 and 720, for example, the reference clock signal @
When the frequency of B is selected to be 2MI (xlζ), count data with a resolution of 50 Qna is obtained from the registers 710 and 720, while the registers 730 to 720 are obtained from the m registers.
750, the arrival period of the capture signal @E having a frequency of about 36 Hz can be measured in one process.

V having the tracking means configured lζ as described above
Regarding TRlζ, the block diagram shown in Fig. 1 and Figs.
The operation will be explained with reference to the operation flow chart and the operation waveform diagram Iζ shown in FIG. 7.

FIG. 5 shows a control means for operating the capstan motor 6 by processing the count data obtained when the leading edge of the control signal recorded on the magnetic tape arrives as detection data for the running phase of the tape. This is a flowchart showing an example in which the phase control during regeneration of the motor 6 is realized by the program lζ implemented in the microprocessor 101 of FIG.
The flowchart lζ shown in the figure will be explained with reference to the a waveform diagram of a conventional VTR shown in FIG. Processing blocks 401 and 403 and branch 402 in FIG. The ll signal, that is, the reference signal corresponding to Q in FIG. 9, is created and t is performed. RE in processing block 403
F and TRM are constants, and are the center values of the repetition period of the reference signal and the tracking shifter amount, respectively, and the memory 11ζ stores the count value corresponding to the leading edge' of the next basic M signal, that is, the rising edge of Q in FIG. The time corresponding to the edge is written into the memory 2, and the tracking thick amount, that is, the time corresponding to the falling edge of U in FIG. 9 is written into the memory 2. The reference signal from the memory IIζ is of course also the reference signal for the cylinder phase control system C (not shown). As will be explained in detail later, the memory 3 is a tracking variable means, and the amount of change from the center value of the tracking shifter amount is written therein. The next processing blocks 404 and 406 and the branch 405 create a phase reference signal for the capstan motor 6, that is, a trapezoidal wave signal corresponding to V in FIG. It is determined whether the count value of the time base counter 500 shown in the figure does not exceed the tracking shifter amount written in the memory 2, and if it does, the processing block 40
At 61ζ, a flag (hereinafter referred to as PC flag) provided on the memory to check whether or not a reproduction control signal has arrived is set to 3 (indicating non-arrival).
A count value corresponding to the boundary point between the period and the slope section (hereinafter abbreviated as H level below the high level C of the trapezoidal wave signal of the phase reference signal V) is loaded. TPZ in processing block 406
is a constant corresponding to the H level period. Next branch 4
At 071ζ, it is checked whether a reproduction control signal has arrived. This is microprocessor 1 in Figure 1.
At the leading edge 1 of the raw control signal applied to the third input IM terminal 231 of 0, the control unit 830 of the capture controller 800 (not shown in FIG.
This can be realized by checking whether the capture flag c (hereinafter referred to as CTL flag) of the control unit 830, which indicates that the count value of the time base counter 500 has been transferred, is set. If CTL
If the flag is set, the next branch 4081
ζ advance, input terminal 2 of the microprocessor 10 in Figure 1
Tracking up/down switch circuit connected to 4091ζ to vary the tracking] detects the state of 4, and if it is ON (H level or L level), the branch 4091ζ is transferred and the output of the tracking up/down switch circuit 14 is If it is L level (tracking up command), processing block 410.411 subtracts the data stored in the memory 31C7;3 by ΔT,
Set TR flag l (details will be explained later).

If the output of the tracking up/down switch circuit 14 is H level (C tracking down command), processing blocks 412 and 413 add ΔT to the data stored in the memory 3, and TR flag 2 (details will be given later). (explained in ). In the branch 408, the tracking up/down switch circuit 14 is turned off.
If it is in the F state, in processing block 4141ζ, the TR
Both flag 1 and TR flag 2 are reset.

Next, in processing block 415, register 100 of FIG.
The count value latched by the register file, that is, the capture register block 7001 in FIG. 1, is transferred to the memory 5 via the accumulator All+6. After checking the PC flag in a branch 416, a processing block 417 and a branch 4181 determine that the time at which the reproduction control signal arrived is the time written in the memory 4I, that is, the II level interval of the phase reference signal V in FIG. It is determined whether the point is 1 point higher than the boundary point of the slope section. If yes, proceed to processing block 420;
The 7-cumulator Aecl of the register 100 sets a value corresponding to the H level of the phase reference signal @v, and if not, the process proceeds to processing block 419. From the processing block 419 and the branch 4211ζ, the phase base Iy! of the arrival time car of the reproduction control signal in FIG. Checking whether it has passed the slope section of the train @V. Processing block 43
The KEISH person in 9 is a count value (constant) corresponding to one slope section of the phase basis @V. If the slope period has passed, the process proceeds to processing block 4221 and sets a value NL corresponding to the low level (hereinafter abbreviated as L level) of the trapezoidal wave signal of the phase reference signal V in FIG. 9 to the accumulator A (Il+). and then processing block 426
, 427 iζ, the value corresponding to the phase error left in the accumulator A6 (1) of the register 100 is written to the memory 6, and the PC flag is set. In other words, if the CTL flag is not set, processing block 423 and branch 424:
The count value of the time base counter 500 is at the boundary point lζ between the slope section and the L level section of the phase reference signal V in FIG.
It is checked whether the corresponding time has passed, and if so, the register 100 (
1') Phase reference No. 11 VII to accumulator Ace
, sets a value NL corresponding to the IJ L level, and proceeds to the processing block 426#ζ. The phase error amount stored in the memory 61 is added to the speed error amount, which will be explained later, at a certain mixing ratio, and is applied to the capstan motor via the second DA converter 1300 and the drive circuit 13 of the whistle 2. . As described above, phase control of the capstan motor 6 is performed.

Next, the speed f control will be explained using the flowchart of FIG. 6 and the operation waveform diagram of FIG. 7.

FIG. 6 shows the difference between the count data obtained when the FG double signal edge arrives, which is detected according to the rotational speed of the capstan motor 6, and the count data obtained when the previous edge arrived. This is a flowchart showing an example of how the control means for operating the capstan motor 6 by processing it as speed detection data, that is, the speed control of the capstan motor, is realized by the program I incorporated in the microprocessor 101ζ of the Hi diagram.

First, it is checked whether the FG multiplied signal has arrived at branch 4281 in FIG. This means that the capture controller 800 transfers the count value of the time base counter 500 to the capture register block 7001 at the leading edge of the capstan FG signal applied to the fourth input terminal 241 of the microprocessor IO in FIG. It is possible to check whether the FG flag indicating 5 is set by fζ. If the flag is set, processing continues at processing block 429 where the accumulator A e of register 100 of FIG.
The count value latched to the register file, that is, the capture register block 700 via the memory 7
Iζ is being transferred. Normally, the expected value (count value) of the arrival time of the FG double signal is added by 1/032t (measurement range C slope section or dynamic range of detection input), and the difference is calculated from the memory 8 in which the count data is stored. , in branch 430, if the value of accumulator Aae of register 100 is positive, that is, it is outside the measurement range and is rotating faster than the set speed, and processing block 4331ζ determines the maximum deceleration value N of accumulator lζ.
H2 is set and in branch 430 register 1
If the value of the accumulator ice of 00 is negative, a constant 15HA2, which is a count value corresponding to the measurement range t, is added in the processing block 431, and if the value of the accumulator Aca of the register 100 is negative in the branch 432, the processing block Accumulator A of register 100 by 434
661ζ Acceleration strict value NL2 is set. Then, in processing block 435, register 1 is stored in memory 9.
The contents of the accumulator Aca of 00, that is, the speed error data are stored.

The branch 436 detects the states of the TR flag 1 and TR flag 2 explained in the phase control flowchart of FIG. 5, and executes three processing blocks 437, 438,
4391 branches. TR flag I, TR flag 2
When both are 1 and 0, that is, when tracking is not being varied, the constant REF2 corresponding to the set speed is stored in the memory 10 as is in processing block 438, and TR
When the flag ] is 1 and tracking is in progress, a value obtained by multiplying the constant REF2 corresponding to the set speed I by (1-α) is stored in the memory 10 in processing block 437. Here, α is expressed by the following equation using the tracking variable step ΔT and the period T of the head switching signal, which were explained in the phase control flowchart in FIG.

α=△T/T In other words, the constant REF2 is of course a value corresponding to the period T, and now the phase of the tracking amount is advanced by ΔT, and if we look only at this one period, the rotation speed is increased by ΔT/T. It is necessary to do so.

Similarly, when TR flag 2 is 1 and tracking is down, a constant REF21 corresponding to the set speed 1 is stored in the memory 10, and white +
α) The multiplied value is stored. In other words, the amount of tracking is △
The phase is delayed by T, and if we look only at this one cycle, the rotational speed needs to be slowed down by ΔT/Tf. As mentioned above, the lζ memory 104ζ is in each state! The setting speed data according to ζ is stored, and in order to obtain a count value corresponding to the expected time of arrival of the next FG double signal in processing block 440, from the memory 7 in which the current FC signal arrival time is stored, the process is performed. The contents of the memory 10 are subtracted and stored in the memory 8.

By the way, if the F'G flag is not set in branch 428, processing block 441 and branch 4421ζ
at the current time (time base counter 50 in Figure 1)
Check whether the count value (0 count value) has exceeded the count value obtained by subtracting 1/2 of the measurement range (slope section or dynamic range of detection input) from the expected value of the FG double signal arrival time. Processing pro work 443
store the current count value in the memory 71;
In processing block 434, accumulator ice of register 100 is set to acceleration R maximum value NL2. In other words, processing blocks 44], 443, 434 and branch 442 are measures against starting. As described above, the speed of the capstan motor 6 is controlled.

FIG. 7 is an operational waveform diagram for explaining the above two flowcharts in detail, J in FIG. 7 is the output waveform of the tracking up/down switch circuit 14 in FIG. 1, and K in FIG. The switching signal number, Figure 7, is the playback control signal waveform, fA
M and N in FIG. y are logical waveforms representing the states of TR flag 1 and TR flag 2, respectively, and O and P in FIG. At time lζ, tracking up/down switch circuit]
When the output of 4 shifts from the oven (tracking hold) state to the L level (tracking up) state, the TR flag 1 is set at the time of the arrival of the next control signal 2, and at the same time the tracking shift amount is stored in the memory. 3 data is ΔT from the previous value N
Memo 1 in which the set speed data is subtracted by
The data of month 0 is changed from REF 2 to REF 2nd - α) 6 Also, when the next control signal arrives at time (31ζ), the tracking up/down switch circuit 14 maintains the L level state, so 3 is further subtracted by ΔT. At time t4, the output of the tracking up/down switch circuit ]4 becomes L level (
When the state shifts from the (tracking up) state to the H level (tracking down) state, the TR flag 1 is reset at L51 when the next control signal arrives, and the T
At the same time as the R flag 2 is set, the data in the memory 3 storing the tracking shifter amount is added by ΔT, and the data in the memory 10 storing the set speed data changes from REFz(1-α) to REF2(1+α). ) will be changed.

Effects of the Invention As is clear from the above description, the magnetic recording/reproducing device having the tracking means of the present invention can detect the rotational speed of the rotational speed detection signal obtained from the capstan motor (represented by the capstan FG signal in the embodiment). Control obtained by means for detecting a speed error with respect to the reference speed lζ (in the embodiment 1m, the speed control means is configured according to the flowchart in FIG. 6) and the insulating medium transferred by the capstan motor j. signals and tracking means (in embodiment Iζ tracking up/down switch circuit 14 of FIG. 1 and branch 40 of the flowchart of FIG.
8. 409 and a processing block 400.4121ζ) for detecting the phase difference between the reference signal and the reference signal (in the embodiment, the phase control means is constructed according to the flowchart of FIG. 5); and the tracking means. means for modulating the reference speed according to the amount of change when the phase of the reference signal is changed by
Processing blocks 411 and 413 of the flowchart of FIG. 6 and branch 436 of the flowchart of FIG. (consisting of processing blocks 437 to 439), it is possible to realize a fast and stable transition when changing the tracking state, and it is also possible to realize an auto-tracking function.
Regarding ζ, it is possible to shorten the settling time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a speech recording and reproducing device having a tracking means in one embodiment of the present invention, and FIG.
3 is a timing chart explaining the circuit operation of FIG. 2, FIG. 4 is a configuration diagram of the capture register block 700, and FIGS. 6 is a flowchart showing the operation of the main part of FIG. 1, FIG. 7 is an fB5 diagram, a timing chart for explaining the flowchart of FIG. 6,
FIG. 8 is a block diagram showing the configuration of a servo mechanism during playback of a conventional VTR, and FIG. 9 is a timing chart for explaining the operation of the main parts of the whistle. 1...Magnetic tape, 2...Cylinder motor, 3...
・First frequency power generation @, 5...Control head%
6...Capstan motor, 7...Second frequency generator, 10...Microprocessor, 14...Tracking up/down switch circuit, 20...Clock terminal, 21-25...th 1 to 5th input terminals, 1
00... Register, 200... Random access memory, 300... Arithmetic unit, 400... Instruction execution means, 450... Control bus, 500... Time base counter, 600... Data bus ,700...
- Capture register controller, 800... Capture controller, 1000... Read-only memory, 1200.1300... First and second DA converters.

Claims (1)

[Claims] 1. A means for detecting a speed error of a rotational speed detection signal obtained from a capstan motor with respect to a reference speed; and a means for detecting a speed error between a control signal obtained from a magnetic medium transferred by the capstan motor and a reference signal provided by a tracking means. A magnetic recording/reproducing apparatus comprising means for detecting a phase difference, and means for modulating the reference speed according to the amount of change when the phase of the reference signal is changed by the tracking means.