JPH01143055A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To stably execute an auto-tracking even in case of a tape to have an error on a mechanism by comparing the size of differential data, which are between sample data and the sample data just before a reference phase is made variable, and a reference value. CONSTITUTION:The error is detected to the reference value of phase difference between a head switching signal, which shows the revolving phase of revolving heads 8 and 9 of a magnetic tape 1, and the control signal of a head 5 and the revolution of a traveling motor 6 of the tape 1 is controlled. At such a time, the sampling of a signal, which is based on an envelope signal to be reproduced from the tape 1, is executed and the differential data between the sample data, for which the reference phase is made variable by a tracking variable means of a microprocessor 10, and the sample data just before the reference phase is made variable and the reference value are compared. By determining the variable direction of the reference phase of the tracking variable means from this size relation, even when the tape 1 is extended or reduced by a temperature change, or, even in case of the tape to generate the error on the mechanism, stable auto-tracking function can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a magnetic recording/reproducing device having an auto-tracking function, and in particular is something that can be easily realized at low cost using a microprocessor.

(Prior Art) In recent years, microprocessors have become widespread and are being used in many household electrical products. Home video tape recorder (hereinafter abbreviated as VTR)
Microprocessors are no exception, and microprocessors are actively used at the center of systems such as controlling the loading mechanism that pulls the magnetic tape out of the cassette and winding it around the rotating head, and the program reservation system that combines a timer. However, precise rotation control devices for the cylinder motor that drives the rotating head and the capstan motor that runs the magnetic tape at a constant speed require complex judgment operations and rapid processing of detection signals, so microprocessors are required. Instead, they have relied on dedicated hardware.

FIG. 11 is a block diagram showing the configuration of a servo mechanism during playback of a conventional VTR, including a cylinder motor 2 that drives a rotary head 8 and a first frequency generator that detects the rotational speed of the cylinder motor 2. 3, a phase detector 4 that detects the rotational phase of the cylinder motor 2, a first frequency discriminator 40 that detects an error in the output signal of the first frequency generator 3 with respect to a reference period, and a reference signal. a generator 42; a first phase comparator 41 for detecting a phase error between the rotational phase signal obtained from the phase detector 4 and the reproduced reference signal obtained from the reference signal generator 42;
a first adder 43 that mixes the phase error output of the phase comparator 41, a first amplifier 44, a first drive circuit 12 that drives the cylinder motor 2, and a cap that runs the magnetic tape at a constant speed. a stun motor 6, a second frequency generator 7 for detecting the rotational speed of the capstan motor 6, a control head 5 for detecting a control signal recorded on the lower end of the magnetic tape 1, and a second frequency generator 7 for detecting the rotation speed of the capstan motor 6; a second frequency discriminator 45 that detects an error in the output signal of the generator 7 with respect to a reference period; and a tracking monomulti circuit 46 that is triggered by the output signal of the reference signal generator 42 and whose delay time is varied by a variable resistor 50. and a controller obtained from the control head 5.

a second phase comparator 47 that detects a phase error between the troll signal and the output signal of the tracking monomulti circuit 46;
and a second phase error output for mixing the phase error output of the second phase comparator 47 and the speed error output of the second frequency discriminator 45.
, an adder 48 , a second amplifier 49 , and a second drive circuit 13 that drives the capstan motor 6 .

The operation of the VTR configured as described above will be briefly explained with reference to the configuration diagram in FIG. 11 and the timing chart of the main parts shown in FIG. 12.

FIG. 12N shows the output waveform of the reference signal generator 42 in FIG. 11, and this signal is used as a reference signal during VTR playback.
The signal is supplied to the first phase comparator 41 and the tracking monomulti circuit 46. The trapezoidal wave signal in FIG. 120 is an internal waveform of the first phase comparator 41, and
The phase reference signal of the cylinder motor triggered by the rising edge of FIG. N, and the rotational phase signal obtained from the phase detector 4 of FIG.

In other words, the hold signal (not shown) sampled by the falling edge of P in FIG. 12 is mixed with the speed error signal obtained from the first frequency discriminator 40 in FIG. 11 in the first adder 43. , are supplied to the first drive circuit 12 via the first amplifier 44.

Therefore, the cylinder motor, that is, the rotating head 8.

It rotates in phase synchronization with the reference signal N in FIG. 12. 12th
Figure Q is a charging/discharging waveform of a capacitor (not shown) in the tracking monomulti circuit 46 of Figure 11, which is triggered by the rising edge of Figure 12N.

By changing the time constant using the variable resistor 50 shown in FIG. 11, the delay time can be varied.

12R is the output waveform of the tracking monomulti circuit 46, the trapezoidal wave signal of FIG. 12S is the internal waveform of the second phase comparator 47 of FIG. 11, and the falling edge of FIG. The phase reference signal of the capstan motor triggered by the control head 5 of FIG.
The playback control signal obtained from T
A second adder 48 mixes the hold signal (not shown) with the speed error signal obtained from the second frequency discriminator 45 in FIG.

The signal is supplied to the second drive circuit 13 via the second amplifier 49 . Therefore, the capstan motor 6 rotates in phase synchronization with the output signal of the tracking monomulti circuit 46 shown in FIG. 12R, which is obtained by shifting the phase of the reference signal shown in FIG. 12N.
As described above, during VTR playback, by synchronizing the phases of the rotary head 8 and the playback control signal (T in FIG. 12), the rotary head 8 can optimally track the tracks recorded on the magnetic tape 1. Become.

(Problem to be Solved by the Invention) If the formats of the tracks recorded on the magnetic tape are compatible, the variable resistor 50 may be a fixed resistor, but due to environmental changes such as temperature changes, the magnetic tape is expanded or contracted, or other V
When reproducing a tape recorded with TR, it is necessary to change the tracking state during reproduction, that is, the phase relationship between the rotary head and the reproduction control signal. For this purpose, the variable resistor 50 shown in FIG. 11 is necessary. moreover,
This variable resistor needs to be a volume with a click point to release it to the user. Generally, the resistance value at the click point of a volume with a click point varies, and in order to correct the variation, another variable resistor is required.

Therefore, conventional VTRs not only require adjustment volume for tracking.

There is also a need for improvement in operability, or usability.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the magnetic recording/reproducing device of the present invention has a magnetic recording/reproducing device in which a frequency-modulated wave signal is recorded by a rotating head, and a control signal having a constant period is controlled. When reproducing a recorded signal of a recorded recording medium recorded by a head, an error with respect to a reference phase of a phase difference between a head switching signal indicating the rotational phase of the rotary head and the reproduced control signal is detected, and the error is detected. A magnetic recording and reproducing device that controls the rotation of a motor for traveling the recorded recording medium based on a signal, the tracking variable means that varies the reference phase, and the frequency modulation device that is reproduced from the recorded recording medium. sampling means for sampling a signal based on a wave signal at a constant phase with respect to the head switching signal; sample data from the sampling means when the reference phase is varied by the tracking variable means; and sample data immediately before varying the reference phase. It is provided with comparison means for comparing the difference data with the sample data and the reference value.

(Function) With the above-described configuration, the present invention can prevent the magnetic tape from expanding or contracting due to environmental changes such as temperature changes, or tapes with deteriorated compatibility recorded on other VTRs with mechanical errors. It is also possible to obtain a magnetic recording and reproducing device that realizes a stable auto-tracking function.

(Example) An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of a VTR having an auto-tracking function according to an embodiment of the present invention.
It controls the cylinder motor 2 that drives the two pairs of rotating heads 8 and 9 that record and reproduce video and audio signals, respectively, and the capstan motor 6 that runs the tape 1 at a constant speed, and also realizes an auto-tracking function. a first drive circuit 12 that drives the cylinder motor 2 by a signal output from the microprocessor 10 via a first analog signal output terminal z7; a second drive circuit 13 that drives the capstan motor 6 by a signal output through the signal output terminal 28;
Amplifying circuits 14 and 16 that amplify the reproduced envelope signals obtained from the rotating heads 8 and 9, respectively, and a detection circuit 15 that peak-detects the amplified reproduced envelope signals.
．． 17 and its detection circuit 15.The detection output of 17 is input, and the detection circuit 17 is controlled by a signal that detects whether or not an audio signal is recorded. a switch circuit 18 that selects the output of the detection circuit 15 when the value is below a certain value, and selects the output of the detection circuit 17 when an audio signal is recorded; and the output of the switch circuit 18 and the microprocessor. 10 through a third analog signal output terminal 26 and a comparator 11 to which the signal is input, and the input terminals 21 to 25 of the microprocessor 10 are 3, a first phase detector 4 and a control head 5
, the second frequency generator 7 and the output of the comparator 11 are connected.

The inside of the microprocessor 10 includes a register 100 for storing data and a random access memory (indicated by the abbreviation RAM in the figure, hereinafter referred to as R).
AM) 200, and a 16-bit arithmetic unit (A in the figure) that executes arithmetic and logical operations on digital data.
300 (indicated by the abbreviation LU (hereinafter abbreviated as ALU)) stores instructions to be executed sequentially, and based on the instructions, the register 100 and the RAM 200 are stored via the control bus 450. A L U30
The instruction execution circuit 400 (indicated by the abbreviation PLA in the figure) controls the operation of the clock terminal 20, and the 17-bit time base counter (indicated by the abbreviation PLA in the figure) counts down the reference clock signal applied to the clock terminal 20. (indicated by the abbreviation TBC) 500 and the time base counter 500 via a counter bus 550.
count data is supplied, and the output data is sent to the register 100. Said RAM200. Said A L U30
A capture register block (indicated by the abbreviation CAPREG in the figure) 700 and the first to fifth input terminals 21 are sent to a data bus 600 connected to
．． 22.23.24.25, and a capture controller that transfers the count data of the time base counter 500 to the capture register block 700 when the edge of six types of capture symbols, each having a different generation source, arrives; In the figure, CAPTRCT
800 (indicated by the abbreviation RL).

Further, the reference clock signal applied to the clock terminal 20 is supplied to the instruction execution circuit 400 via a timing generator (indicated by the abbreviation TO in the figure) 900, and to the data bus 600. A read-only memory (indicated by the abbreviation ROM in the figure, hereinafter abbreviated as ROM) 1000. I10 port 1100. First (7) DA converter 1200. A second DA converter 1300 and a third DA converter 1400 are connected, and the RAM 200 and the RO
M100O has address decoder 250.105 respectively
It has 0.

Note that the capture controller 800 and the capture register block 700 take in count data from the time base counter 500 when the edge of the capture signal arrives, and the minimum decomposition accuracy is higher than the instruction execution cycle, and A capture circuit is configured to send the result to the ALU 300, the register 100, or the RAM 200 according to a specific instruction from the ALU 300.

Regarding the VTR configured as described above, the configuration diagram shown in FIG. 1 and the capture controller 80 shown in FIG.
Based on the specific configuration diagram of 0 and the timing chart of the main parts shown in FIG.

Let's explain its operation.

First, FIG. 2 shows the capture controller 80 of FIG.
0 is a logic circuit diagram showing a specific configuration example of
The fifth input terminal 21.22.23.24.25 has a control unit 810.820°830 of the same configuration,
840.850 are connected, and the control units 810.820.830.840.850 each have a common reference clock input terminal 801 and a data transfer lock input terminal 802 to the capture register block 700, and , individual reset terminals 811.
821.831.841.851 and one separate flag output terminal 812.822.832.842.852 and one separate data transfer terminal 813.823.833.843.8
It has 53.

Next, FIG. 3 shows a control unit 85 that constitutes the third DA converter 1400 and comparator 11 in FIG. 1 as well as the capture controller 800 shown in FIG.
0 and a capture register block 700. FIG. 3A shows a clock signal waveform applied to the clock terminal 2o in FIG. Figure B is the third
This signal waveform is obtained by frequency-dividing the signal waveform of FIG. A, and this signal is supplied to the reference clock input terminal 801 of FIG. 2 as a reference clock signal. Further, FIG. 3C shows a time base counter 500 constituted by a synchronous counter whose unit stage is a master-slave type flip-flop.
The figure shows the count clock signal waveform of 1. The output of the master part of the flip-flop of each unit stage changes at the leading edge marked with an arrow, and the output of the slave part changes at the trailing edge. output changes. The third diagram shows a clock signal waveform for data transfer created from the signal waveforms of FIGS. 3A and 3B, and is supplied to the data transfer lock input terminal 802 of FIG. Furthermore, FIG. 3E shows the third DA applied to the non-inverting input terminal of the comparator 11 in FIG.
FIG. 3F is an analog output signal of the converter 1400, and FIG. It's a signal.

Now, when the signal waveform shown in FIG. 3F is applied to the fifth input terminal 25 in FIG. 2, the level of the reference clock input terminal 801 becomes "1" after the leap-in edge has arrived.
At the point in time, the output level of the NAND gate 854 shifts to "1" as shown in FIG. 3G, and furthermore,
At the time when the level of the reference clock input terminal 801 shifts to rOJ, the output level of the NAND gate 855 shifts to "1" as shown in FIG. rl'', the output level of the NAND gate 856 transitions to ``1'' as shown in Figure 3. Said NAND gate 8
54.855.856 is another NAN to be paired with
Since it forms a bistable circuit with the D gate, when the output level shifts to "1", it maintains that state until a reset signal is applied to another NAND gate.
When the output level of the AND gate 856 shifts to "1", the output level of the paired NAND gate 857 shifts to "1".
0", and the output level of the AND gate 858 also becomes "0".
”, so the NAND gate 854.855
The output level of returns to "0".

In this way, when the leading edge of the external signal arrives at the fifth input terminal 25, the leading edge of the external signal arrives at the second data transfer terminal 8.
53, a signal waveform as shown in FIG. 3J is sent through an AND gate 859, and this signal causes count data to be transferred from the time base counter 500 in FIG. 1 to the capture register block 700.

That is, in the signal waveform of FIG. 3F, the timing at which the level shifts from rOJ to "1" depends on the potential of the output signal of the detection circuit 15 or 17 of FIG. The counted data of the time base counter 500 also depends on the potential of the output signal of the detection circuit 15 or 17.

The output signal of the NAND gate 856 is sent to the flag output terminal 852 and is used as a capture flag signal indicating that the count data of the time base counter 500 has been transferred.
1, a reset signal is applied after software (program) confirms that this capture flag is set.

Next, FIG. 4 is a configuration diagram showing a specific example of the capture register block 700, in which each data input terminal is connected to the Do terminal to the D7 terminal, and the data output terminal is connected to the Q1 terminal to the Q8 terminal. A unit register 750 is composed of 8 memory cells, each having a data input terminal connected to the DO terminal to the D15 terminal, and 16 memory cells each having a data output terminal connected to the Q1 terminal to the Q16 terminal. unit register 740.
730 and the data input terminals are D1 terminal to D16, respectively.
The unit registers 720 and 710 are configured as a whole by 16 memory cells whose data output terminals are connected to terminals Q1 to Q16. In addition, each unit register 710.720.730.7
40°750 each has two control signal input terminals, read terminals 711.721.731.74
1.751 are respectively applied with data transfer signals from the capture controller 800 shown in FIG. The read command activates the output side of each unit register, and connects the data output terminals Q1 to Q.
A select signal for reading is applied to the data bus 600 in FIG. 1 through the 16 terminals.

Now, the transfer control signal from the data transfer terminal 853 in FIG. 2 is supplied to the read terminal 751 in FIG. However, in the embodiment of the present invention shown in FIG. 1, a mechanism prepared as a capture circuit is used for the scan counter for conversion and the register for storing the conversion result.
The burden on hardware is significantly reduced.

By the way, in FIG. 4, the unit register 730°74
The connection position between the data input terminal and data output terminal of 0 and 750 is shifted by one bit for the following reason.

First, the input section of the 8-bit unit register 750 has a first
The same 8-bit count data as that supplied to the DA converter 1400 in the figure is supplied, but in order to increase the sampling rate, the DA converter 1400 and the unit register 750 are supplied with 8-bit count data close to the LSB (least significant bit). It is preferable to supply count data for the time base counter 500. Furthermore, the unit registers 730 and 740 are used to improve the resolution of the timing of capturing edges of external signals.

Although the LSB of the time base counter 500 and the LSB of the unit register are made to match, the unit registers 710 and 72
Regarding 0, the data input terminal is shifted to the left by one bit so that up to twice the interval can be processed at once with the same number of bits as the unit registers 730 and 740.

With such a bit shift configuration of the unit registers 730 and 740, for example, the frequency of the reference clock signal can be changed to 2MHz.
When z is selected, count data with a resolution of 500 ns is obtained from the unit registers 730 and 740,
On the other hand, from the unit registers 710 and 720, the arrival period of an external signal having a frequency of about 30 Hz can be measured in one process.

The operation of the VTR having the auto-tracking function configured as described above will be explained with reference to the configuration diagram shown in FIG. 1 and the operation flowcharts and operation waveform diagrams shown in FIGS. 5 to 10.

FIG. 5 shows a control means for operating the capstan motor 6 by processing the count data obtained when the leading edge of the control signal recorded on the magnetic tape arrives as magnetic tape running phase detection data, that is, the capstan motor 6. 2 is a flowchart showing an example of phase control during motor regeneration using a program built into the microprocessor 10 of FIG. 1; The flowchart in FIG. 5 will be explained with reference to the operational waveform diagram of a conventional VTR in FIG. 12.

Processing blocks 401 and 403 and branch 402 in FIG.
A reference signal for VTR playback, that is, a signal corresponding to N in FIG. The count value corresponding to the leading edge of the next reference signal, that is, the time corresponding to the rising edge of FIG. 12N, is stored in memory 1, and the tracking shift amount, that is, the time corresponding to the rising edge of The time corresponding to the falling edge is written. As will be explained in detail later, the amount of change in the tracking shifter amount from the center value is written in the memory 3 for the auto-tracking function.

Processing blocks 404 and 406 and branch 405 then generate the capstan motor phase reference signal, i.e. the 12th
A trapezoidal wave signal corresponding to FIG. If it exceeds, the processing block 406 resets the NL flag for checking whether or not the reproduction control signal has arrived (indicating that it has not arrived), and further stores the high level of the trapezoidal wave signal shown in FIG. 12S in the memory 4. A count value corresponding to the boundary point between the level (hereinafter abbreviated as H level) period and the slope section is written. Therefore, T in processing block 406
PZ is a constant corresponding to the H level period.

Next, it is checked in branch 407 whether or not a reproduction control signal has arrived. This indicates that the capture controller 800 has transferred the count value of the time base counter 500 to the capture register block 700 at the leading edge of the playback control signal applied to the third input terminal 23 of the microprocessor 10 in FIG. This can be executed by checking whether the indicated CTL flag is set. If CTL
If the flag is set, then processing block 408
and accumulator A of register 100 in FIG.
The count value latched in the register file, that is, the capture register block 700 in FIG. 1, is transferred to the memory 5 via cc. And branch 409
After checking the NL flag at , processing block 41
0. A branch 411 determines whether the time when the control signal arrives is earlier than the time written in the memory 4, that is, the boundary point between the H level section and the slope section in FIG. 12S. If yes, processing block 413
The process proceeds to step 412, where the accumulator A c c is set to a value corresponding to the H level in FIG.

Processing block 412 and branch 414 now check whether the arrival time of the control signal has passed the slope section of FIG. 12S. Processing block 41
KE 15HA in 2 is a count value (constant) corresponding to the slope section of FIG. 12S. If the slope interval has passed, the process proceeds to processing block 415, where the low level (of the trapezoidal wave signal of FIG.
A value corresponding to the L level (hereinafter abbreviated as L level) is set. Then, according to processing blocks 419 and 420, the value corresponding to the phase error left in the accumulator Ace is written to the memory 6, and the NL flag is set. If the control signal has not arrived in branch 407, that is, if the CTL flag is not set, processing block 416 and branch 417 perform the following steps.
The count value of the time base counter 500 is shown in FIG.
Check whether the time corresponding to the boundary point between the slope section and the L level section has passed, and if yes, set the accumulator A c c to a value corresponding to the L level in FIG. 12 S in processing block 418. and by one or more proceeding to processing block 419 .

The phase of the capstan motor 6 is controlled.

Next, the auto-tracking operation will be explained using the flowcharts shown in FIGS. 6 and 8 and the operation waveform diagram shown in FIG. 7.

FIG. 6 shows that the reproduced envelope signal obtained from the rotary head 8 or 9 of FIG. 7 is a flowchart showing an example in which a means for capturing digital data AD-converted by a comparator into memory is realized by a program built in the microprocessor 10 shown in FIG. 1; The seventh figure is a head switching signal of the rotary head 8 or 9, the reproduction envelope signal obtained from the rotary head 8 or 9, and the signal M in FIG. This shows the signal. That is, the signal M in FIG. 7 is the signal applied to the inverting input terminal of the comparator 19 in FIG.
0. The signal is AD converted by the capture register block 700 and the like.

Branches 421, 424, and 428 in FIG. 6 are processes for branching the flow according to the value of state variable A set in RAM, that is, memory. First, when A=0, processing is performed by branch 421. Proceeding to block 422, it is determined whether the signal level of the head switching signal (H8W, K in FIG. 7) input to the work/○ port 1100 in FIG. The state variable A is set to 1.

When A=1, processing block 42 is executed by branch 424.
Proceeding to step 5, it is determined whether the signal level of the head switching signal (hereinafter abbreviated as H5W signal) is H level, and if it is, it means that the rising edge of the H5W signal has been detected, and processing block 426 Proceed to and set a timer to detect approximately 8 ms after the current time. This is because, as can be seen from the envelope signal shown in Figure 7, the envelope signal output obtained from the rotating head is not constant due to variations in the head and non-linearity of the recording track. This is to keep the point always at the same position, that is, about 8 ms after the rising edge of the H8W signal. Further, the timer setting is realized by using the time base counter 500 shown in FIG. 1, or by using a soft counter that is determined based on the number of times a specific command on the program is passed. Processing block 427 then increments state variable A to two.

When A=2, branch 428 causes processing block 42
9 and determines whether the timer set when A=1 has completed counting. If yes, proceed to processing block 430, FIG.

As explained in FIG. 4, the register file containing the digital value obtained by AD converting the peak-detected signal of the reproduced envelope signal (M in FIG. 7), that is, the count latched in the capture register block 700 in FIG. The processing block 43 transfers the values to the memory 7.
1, the state variable A is reset to O. By repeating the above flow, it is possible to always capture the amplitude level of the envelope signal after a certain period of time from the rising edge of the H5W signal into the memory.

Next, regarding the main flow of auto tracking,
This will be explained using the flowchart shown in FIG.

First, the branch 432 connects to the first switch circuit 3 of FIG.
Determine whether 1 is pressed by the user or not, and if yes (if the switch is ON), process block 433
The process proceeds to branch 439, where the time for determining the auto-tracking operation period is set in a timer, and the variable B set in the memory is cleared (=O)L in processing block 434. Further, if the determination in branch 432 is negative, the process proceeds to branch 435, where it is determined whether or not the timer set in the processing block 433 has completed counting. The flow is branched by branches 439, 442.446.454.458.

First, when B is 0, the process proceeds to processing block 440 via branch 439, and processing block 430 of the flow of FIG.
The data in the memory 7 in which the amplitude level of the reproduced envelope signal has been taken is transferred to the accumulator Acc and stored in the memory 8 again.

Then, in processing block 441, state variable B is incremented to one.

When B is 1, branch 442 causes processing block 44
Proceeding to step 3, in order to shift the tracking shifter amount by +1 μs, a value corresponding to the tracking amount of 1 μs is added to the data in the memory 3 described in the explanation of FIG. Processing then proceeds to processing block 444 .

The variable B is set to 10 and the state variable B is incremented to 2 at processing block 445.

When B is 2, branch 446 causes processing block 44
7, the variable RI is decremented by 1, and then, in branch 448, it is determined whether the variable RI is 0. In other words, the processing block 444.4 is
47 and branch 448 implement a soft timer, which delays the time required for the program to pass through processing block 447 ten times. This means that the tracking shifter amount is set to 1m in processing block 443.
After s shift.

This is because it takes time for the capstan motor 6 shown in FIG. 1 to complete phase pull-in. Then, after a predetermined time has elapsed, the process proceeds to processing block 449, and from the rising edge of the H8W signal after changing the tracking shifter amount, approximately 8
ms later, that is, the amplitude level of the reproduction envelope at point a in FIG. 7, the data in the memory 7 captured by the flow in FIG. 6 is transferred to the accumulator Ace, and the data and processing block 440 or processing block 453
．． 465 (explained later), approximately 8 ms from the rising edge of the H8W signal before changing the tracking shifter amount.
The difference between the amplitude level of the subsequent reproduced envelope signal and the captured data in the memory 8 is calculated. Then, in branch 450, it is determined whether the value remaining in the accumulator Acc is less than or equal to a certain value ε. If no (greater than or equal to), that is, if the envelope signal level after changing the tracking shifter amount is greater than or equal to ε compared to before the change, state variable B is set to 1 by processing block 452, and if true (less than or equal to), In other words, if the envelope signal level after changing the tracking shifter amount is not greater than ε or more than before the change, processing block 451 determines that state variable B
Set to 3. The process then proceeds to processing block 453, where the data in the memory 7 containing the current amplitude level of the reproduced envelope signal is once transferred to the accumulator Acc and then stored in the memory 8.

When B is 3, processing block 45 is executed by branch 454.
Proceeding to step 5, in order to shift the tracking shifter amount by -1 ms, a value corresponding to the tracking amount of 1 ms is subtracted from the data in the memory 3 described in the explanation of FIG.

Processing block 456 then sets variable B to 10, and processing block 457 incremented state variable B to 4.

When B is 4, processing block 45 is executed by branch 458.
Proceed to step 9 and decrement the variable by 1.

Next, in branch 460, it is determined whether the variable is 0 or not. In other words, a soft timer is realized by the processing blocks 456, 45'J and the branch 460 using variables, and the program executes the processing block 459 once.
This means that the time required to pass 0 times is delayed. This is after the tracking shifter amount is shifted by IILI in processing block 455.

This is because it takes time for the capstan motor 6 shown in FIG. 1 to complete phase pull-in. Then, after a predetermined time has elapsed, the process proceeds to processing block 461, and from the rising edge of the H8W signal after changing the tracking shifter amount, approximately 8
ms later, that is, the amplitude level of the reproduction envelope at point a in FIG. 7, the data in the memory 7 captured by the flow in FIG. 6 is transferred to the accumulator Acc, and the data and processing block 453 or processing block 465
Memory 8 stores the amplitude level of the reproduced envelope signal about 8 seconds after the rising edge of the H8W signal before changing the tracking shifter amount (described later).
The difference from the data is taken. And branch 462
The value remaining in the accumulator at is a certain constant value (−
ε) or less is determined.

If no (greater than or equal to), that is, the envelope signal level after changing the tracking shifter amount is not smaller than that before change by ε or more, state variable B is set to 3 by processing block 464, and if true (less than or equal to) That is, if the envelope signal level after changing the tracking shifter amount is smaller than before the change by ε or more, processing block 463 sets state variable B to 1. The process then proceeds to processing block 465, where the data in the memory 7 containing the current amplitude level of the reproduced envelope signal is transferred to the accumulator Ac.
After being temporarily transferred to C, it is stored in memory 8.

By the way, in the branches 450 and 462,
The reason why the size discrimination criteria are set to ε and (-ε) instead of 0 is as follows.

FIG. 9 is a diagram showing the relationship between the recording track of the frequency modulated wave signal recorded on the magnetic tape 1 and the rotary head 8 or 9. The rotating head width WII is wider than the track width WT, and the relationship between the tracking shifter amount and the reproduction envelope output level has a flat characteristic with no peak in the envelope output level, as shown in FIG. 10(a). Moreover, the optimal tracking position is
As shown in FIG. 9, point b in FIG. 10 is desirable because it is necessary to maintain exactly the same state during recording and reproduction. Further, the differential output of the playback envelope output level when shifting the tracking shifter amount in the positive direction, that is, the (memory 7
-Memory 8) is plotted at p in FIG. 10(b), which is the differential output of the reproduction envelope output level when shifting the tracking shifter amount in the negative direction, that is, the (Memory 7-Memory 8) in the processing block 461. 8
) is plotted as r in FIG. 10(b). Therefore, as can be seen from FIG. 10(b), when the difference output of the playback envelope output level is shifted by the tracking shifter amount in the positive direction, use E, and when the tracking shifter amount is shifted in the negative direction, E is used. (−ε) to determine the optimal tracking position (10th
This makes it possible to detect the points shown in the figure.

According to the above flow, when the tracking shifter amount is shifted in the positive direction while the timer set in processing block 433 is counting, if the differential output of the playback envelope output level becomes a certain constant value ε or less, the tracking shifter amount is shifted again. When shifted in the negative direction, the differential output of the playback envelope output level is set to a certain constant value (
-ε) or less, the shift direction is changed.By repeating the above steps, the tracking position is converged to the optimum tracking position, and the auto-tracking operation is stopped when the timer completes counting. , the tracking shifter amount immediately before the stop is set as the final optimal tracking position.

By the way, if the branch 435 is positive, that is, if the auto-tracking operation is not in progress, the process proceeds to a processing block 436, where the reproduced envelope signal is generated approximately 8 ms after the rising edge of the H5W signal detected in the auto-tracking operation described above. The data in the memory 8 where the maximum amplitude level of is taken is transferred to the accumulator A c c , and the data in the accumulator Ace is shifted to the right, that is, halved.
Proceeding to processing block 437, in processing block 430 of the flow of FIG.
8, if the data remaining in the accumulator Ace is positive, that is, the current amplitude level of the reproduced envelope signal is half the maximum amplitude (6d
B) If the following occurs, jump to processing block 433 and enter the auto-tracking state.

Further, the branch 466 is branched depending on the position of the second switch circuit 32 shown in FIG. In other words, the second switch circuit 32 is a 3-position switch, and when its output is at H level, the processing block 4
67, a value corresponding to 0.5 ms is added to the data in the memory 3 via the accumulator A c c in order to add 0.5 ms to the tracking shift amount. If the output level of the second switch circuit 32 is at the L level, the process moves to processing block 468, and the accumulator A is used to subtract the tracking shift amount by 0.5.
cc A value corresponding to 0.5 ms is subtracted from the data in memory 3 via c. This allows manual tracking.

(Effects of the Invention) As is clear from the above explanation, the magnetic recording and reproducing device having an auto-tracking function of the present invention records a frequency-modulated wave signal by a rotating head, and a control signal with a constant period. When reproducing a recorded signal recorded on a recorded recording medium (represented by magnetic tape 1 in the embodiment) by a control head, a head switching signal ( ) (SW signal No. 1) indicating the rotational phase of the rotary head is generated. Detecting the error of the phase difference between the signal and the reproduced control signal with respect to the reference phase (in the embodiment, the phase control means is configured according to the flowchart of FIG. 5).
A magnetic recording and reproducing apparatus that controls the rotation of a motor for traveling the recorded recording medium (represented by a capstan motor 6 in the embodiment) based on the error signal,
tracking variable means for varying the reference phase (in the embodiment, the tracking variable means is constituted by processing blocks 443 and 455 in FIG. 8); and the frequency modulated wave signal reproduced from the recorded recording medium. (
In the example, the signal is based on the signal (represented as a regenerated envelope signal in the example) (represented as a detected signal in the example)
from the sampling means (in the embodiment, the sampling means is configured according to the flowchart of FIG. 6) at a constant phase with the head switching signal, and when the reference phase is varied by the tracking variable means. Difference data between sample data and sample data corresponding to each phase immediately before changing the reference phase (in the embodiment (memory 7 - memory 8)
Comparison means (in the embodiment, the 8th
Processing block 449.461 and branch 450.4 in the diagram
62), and the direction in which the reference phase of the variable tracking means is varied is determined according to the result of the comparing means, and the magnetic tape expands and contracts due to environmental changes such as temperature changes. Furthermore, it is possible to obtain a magnetic recording/reproducing apparatus which realizes a stable auto-tracking function even on tapes recorded with other VTRs having mechanical errors and having deteriorated compatibility. Of course, since there is no need for an adjustment volume like in a conventional VTR, operability can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a magnetic recording/reproducing device having an auto-tracking function in an embodiment of the present invention, FIG. 2 is a specific logic circuit diagram of the capture controller 800 shown in FIG. 1, and FIG. A timing chart explaining the operation of the circuit shown in FIG. 4 is a chapter register block 700.
Fig. 5, Fig. 6, and Fig. 8 are flowcharts showing the operation of the main parts of Fig. 1, Fig. 7 is a timing chart to explain the flowchart of Fig. 6, and Fig. 9 is a magnetic A diagram showing the relationship between the recording track of the frequency modulated wave signal recorded on the tape 1 and the rotary head 8 or 9,
Figure 10(a) plots the playback envelope output level with respect to the tracking thickest, Figure 10(b) plots the difference data of the playback envelope output level, and Figure 11 plots the servo output level during playback of a conventional VTR. A block diagram showing the structure of the mechanism, and FIG. 12 are timing charts for explaining the operation of the main parts of FIG. 11. 1...Magnetic tape, 2...Cylinder motor, 6
...Capstan motor, 11...Comparator, 100...Register, 200...RAM, 30
0...ALU, 400...Instruction execution means, 500
...Time base counter, 700...Capture register block, 800...Capture controller, 1000...ROM, 1400...DA converter. Figure 2: 802-data U ri 0.7 ri in η eaves, 811-851-ri, 7 tots 812-85
2.
i9 mi 13 pus ψ to O q gu -%r dimension♀

Claims (2)

[Claims] (1) A head that indicates the rotational phase of the rotary head when reproducing a recorded signal of a recorded recording medium in which a frequency modulated wave signal is recorded by a rotary head and a control signal of a constant period is recorded by a control head. A magnetic recording and reproducing apparatus that detects an error in a phase difference between a switching signal and the reproduced control signal with respect to a reference phase, and controls rotation of a motor for running the recorded recording medium based on the error signal, tracking variable means for varying the reference phase; sampling means for sampling a signal based on the frequency modulated wave signal reproduced from the recorded recording medium at a constant phase with the head switching signal; and the tracking variable means. a comparison means for comparing the difference data between the sample data from the sampling means when the reference phase is varied and the sample data immediately before the reference phase is varied, and a reference value; A magnetic recording and reproducing apparatus characterized in that a direction in which the reference phase of the tracking variable means is varied is determined. (2) The magnetic recording and reproducing apparatus according to claim (1), wherein the reference value of the comparing means for comparing the magnitudes is changed according to the direction in which the reference phase of the variable tracking means is varied.