JP2558649B2 - Recording speed discriminating device for magnetic tape - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording speed determination device for a magnetic tape, and more particularly, it provides a device that facilitates determination using a microprocessor.

2. Description of the Related Art In recent years, microprocessors have been remarkably popularized and used in many household electric appliances. This is no exception for home video tape recorders (hereinafter abbreviated as VTRs). The central part of the system for controlling the loading mechanism that pulls out the magnetic tape from the cassette and winds it around the head drum, and program reservations that combine timers. Microprocessors are actively used in. However, the precise rotation control device for the head drum motor and capstan motor, and the tape running speed at the time of recording from the control signal recorded on the magnetic tape (in the case of VHS of VHS system, for example, 2 hours mode and 6 hours in Japan There is a mode, and in the United States, a mode for 4 hours is added.) In the recording speed discriminating device for discriminating, the complicated judgment operation and the rapid processing of the detection signal are required. Has relied on hardware.

A typical example in which a recording speed discriminating device for a magnetic tape is constructed by dedicated hardware is disclosed in Japanese Patent Laid-Open No. 56-37856.
The above-mentioned reference 1 introduces an output signal of a rotary pulse generator connected to a capstan for driving a magnetic tape and a control signal recorded on the magnetic tape. An apparatus for discriminating the recording speed is shown by measuring the ratio of the frequency of 1 by a digital circuit mainly composed of a counter.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, in the hardware-based device as described in Document 1, when the reference value for determination is changed or the frequency of the input signal itself is changed, the circuit is changed each time. It was necessary to change the specifications, and this was an obstacle when the system including the peripheral part was integrated into a single-chip LSI.

On the other hand, if a microprocessor can perform a series of discrimination processing, not only dedicated hardware becomes unnecessary, but also many functions can be realized only by changing software, so it is possible to flexibly cope with various specification changes. It becomes possible to do.

Means for Solving the Problems In order to solve the above-mentioned problems, a recording speed discriminating apparatus for a magnetic tape according to the present invention uses a magnetic tape at at least two different speeds based on a command value stored in advance in a memory means. Driving means for running at a constant speed, a capture register to which count data of a time base counter for counting a reference clock signal is supplied, and count data for the capture register when the edge of the identification signal recorded on the magnetic tape arrives. The capture controller, the interval calculation means for causing the calculation means to calculate the difference between the count data previously fetched and the newly fetched count data by the instruction from the instruction execution means, the interval calculation result and the command value. The recording speed of the magnetic tape is determined based on A separate recording speed determining means is provided.

Effects According to the present invention, a magnetic tape recording speed determination device can be obtained not only by eliminating the need for a dedicated and complicated hardware circuit but also by flexibly coping with various specification changes. it can.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a recording speed discriminating apparatus for a magnetic tape according to an embodiment of the present invention. The traveling speed of the magnetic tape is controlled to be constant and the recording speed of the magnetic tape is discriminated. Microprocessors for 10
00, a drive amplifier 100 that amplifies a signal output from the microprocessor 1000 through the first analog signal output terminal 11 to drive the capstan motor 1, and a speed power generation connected to the capstan motor 1. A first amplification amplifier 200 that amplifies the output signal of the machine 2 and sends it to the second input terminal 22 of the microprocessor 1000, and a magnetic tape that is run by the rotation of the capstan motor 1 (not shown). The second amplifying amplifier 300 which amplifies the output signal of the control head 3 which reproduces the control signal recorded in (.) And sends it to the first input terminal 21 of the microprocessor 1000 is entirely constituted.

Inside the microprocessor 1000, a register 1100 for storing data, a random access memory (indicated by an abbreviation symbol RAM in the figure, hereinafter abbreviated as RAM) 1200, and arithmetic of digital data and A 16-bit arithmetic unit that executes logical operations (indicated by an abbreviation symbol ALU in the figure. Hereinafter, abbreviated as ALU.) 1300
And an instruction to be sequentially executed, and based on the instruction, the register 1100 and the register 1100 via the control bus 1450
An instruction execution circuit (indicated by an abbreviation PLA in the figure) 1400 for controlling the operations of the RAM 1200 and the ALU 1300, and a 17-bit time base counter for counting the reference clock signal applied to the clock terminal 20.
1500, the count data of the time base counter 1500 is supplied via a counter bus 1550, and the output data thereof is sent to the register 1100, the RAM 1200, the data bus 1600 connected to the ALU 1300, and a capture register block 1700. , 1st to 6th input terminals 21,22,23,24,2
A capture controller 1800 which transfers the count data of the time base counter 1500 to the chapter register block 1700 when the edges of 6 types of capture signals which are applied to 5, 26 and have respectively different generation sources arrive is provided. . The reference clock signal applied to the clock terminal 20 is supplied to the instruction execution circuit 1400 via a timing generator (indicated by an abbreviation TG in the drawing) 1900, and the data bus 16 is supplied.
00 is a read-only memory (ROM) 2000, I / O port 210
0, a first DA converter 2200, a second DA converter 2300 are connected, and the RAM 1200 and the ROM 2000 have address decoders 1250 and 2050, respectively.

The capture controller 1800 and the capture register block 1700 take in count data from the time-base counter 1500 when the edge of the capture signal arrives, and the count data whose resolution of small quantity is higher than the execution cycle of the instruction. A capture circuit that sends the result to the ALU 1300, the register 1100, or the RAM 1200 by a specific instruction from 1400 is configured.

The operation of the magnetic tape recording speed discriminating apparatus configured as described above will be described with reference to the configuration diagram shown in FIG. 1 and the operation flowchart shown in FIG. FIG. 2 shows the recording speed discrimination means of the magnetic tape and the capstan motor 1 by processing the count data obtained when the leading edge of the control signal recorded on the magnetic tape arrives as the running phase detection data of the magnetic tape. 9 is a flowchart showing an example in which the control means for operating is realized by a program built in the microprocessor 1000 of FIG. 1.

In addition, Table 1 shows the playback of recorded tapes recorded in 2H, 4H, and 6H tape running time modes in VHS system VTRs including Japan and the United States, when playing in each of three running time modes. This figure shows the change in the repeat cycle of the control signal. If the running time mode at the time of recording and the running time mode at the time of reproduction match, the repeat cycle of the playback control signal becomes approximately 33 ms.

Now, in the branch 1401 of FIG. 2, it is checked whether or not the leading edge of the reproduction control signal has arrived. If yes, the process proceeds to the subsequent processing block 1402. If not, the routine of FIG. 2 is exited. But
At the leading edge of the reproduction control signal applied to the first input terminal 21 in FIG. 1, the capture controller 1800 causes the capture register block 1700 to
This can be performed by checking whether or not a flag indicating that the count value of the time base counter 1500 has been transferred is set in. In processing block 1402, RAM1 of FIG.
A count data t _n-1 taken prior to a specific address of 200, the difference between the newly captured count data t _n AL
The calculation is performed by the U1300 and the result is left in the accumulator ACC included in the register 1100 as the calculated value of the interval, and the flag used for the determination in the branch 1401 is reset. In the branch 1403 and the branch 1404 following the processing block 1402, it is checked whether the current traveling time mode held in the RAM 1200 is 2H, 4H or 6H, and the processing is advanced to a different process depending on the result. . If the current running time mode is 2H, branch 1405 and branch 1406 determine from the calculated value of the interval left in the accumulator whether the repeat cycle of the reproduction control signal is longer than 25 ms or shorter than 14 ms. , If the time is longer than 25 ms, the process proceeds to the processing block 1407 without changing the current running time mode, but in other cases, the processing block 1408 or the processing block 14 is determined according to the determination in the branch 1406.
The processing is moved to 09, the traveling time mode is changed to 4H or 6H, the information is stored in the RAM 1200, and the routine of FIG. 2 is ended. On the other hand, if the determination at branch 1404 is 4H, branch 1410 and branch
In 1411, the repetition cycle of the playback control signal is
Determine if it is longer than 50ms or shorter than 28ms,
If it is shorter than 50 ms and longer than 28 ms, the process proceeds to processing block 1407 without changing the current running time mode,
Otherwise, branch 1410 or branch 1411
According to the judgment in step 1, the processing is transferred to processing block 1412 or processing block 1409, and the traveling time mode is set to 2H or
The value is changed to 6H, the information is stored in the RAM 1200, and the routine of FIG. 2 is ended. In addition, the branch
If the determination in 1404 was 6H, in branch 1413 and branch 1414, it is determined whether the repetition cycle of the playback control signal is longer than 75 ms or shorter than 42 ms, and if shorter than 42 ms, the current The processing is moved to the processing block 1407 without changing the traveling time mode, but in other cases, the processing is moved to the processing block 1412 or the processing block 1408 according to the determination in the branch 1413 or the branch 1414, and the traveling time mode is set to 2H or The value is changed to 4H, the information is stored in the RAM 1200, and the routine of FIG. 2 is terminated. Also, processing block 14
In 07, the count data t _n fetched at a specific address of the RAM 1200, that is, the difference between the same data as used in the processing block 1402 and the previously calculated expected value t _S is calculated by the ALU1300, and the result is firstly calculated. It is sent to the first DA converter 2200 in the figure. As a result, the running phase of the magnetic tape is controlled. Actually, it is calculated by another routine based on the phase error data calculated in the processing block 1407 and the output signal of the speed generator 2 applied to the second input terminal 22 of FIG. The velocity error data is combined with each other after being subjected to a time base operation by a digital filter or the like, and is combined into the first DA.
Although transmitted to the converter 2200, only the control process by phase error detection is shown here for the sake of simplicity.

Note that FIG. 3 shows the capture controller 1800 of FIG.
It is a logic circuit diagram showing a specific configuration example of, the control unit 1810, 1820, 1830, 1840, 1850, 1860 of the same configuration is connected to the external signal input terminals 21, 22, 23, 24, 25, 26 Each of the control units 1810 to 1860 has a common reference clock input terminal 1801 and a data transfer clock input terminal 1802 to the capture register block 1700, and further has individual reset terminals 1811 to 1861 and individual flags. Output terminals 1812-1862 and individual data transfer terminals
1813 to 1863. FIG. 4 is a timing chart for explaining the operation of the control unit 1810 constituting the capture controller 1800 shown in FIG. 3, and FIG. 4A is a clock signal waveform applied to the clock terminal 20 of FIG. 4B is a signal waveform obtained by dividing the signal waveform of FIG. 4A, and this signal is supplied to the reference clock input terminal 1801 of FIG. 3 as a reference clock signal. Further, FIG. 4C shows a count clock signal waveform of the time base counter 1500 constituted by a synchronous counter having a master slave type flip-flop as a unit stage, and a leading edge (leading edge) with an arrow is shown. ) Changes the output of the master part of the flip-flop of each unit stage, and changes the output of the slave part at the trailing edge (trailing edge). FIG. 4D shows a clock signal waveform for data transfer created from the signal waveforms of FIGS. 4A and 4B, and is supplied to the data transfer clock input terminal 1802 of FIG.

Now, when the signal waveform shown in FIG. 4E is applied to the external signal input terminal 21 of FIG. 3, when the leading edge comes and then the level of the reference clock input terminal 1801 shifts to "1". At the time when the output level of the NAND gate 1814 shifts to "1" as shown in FIG. 4F and the level of the reference clock input terminal 1801 shifts to "0", the output level of the NAND gate 1815 shifts to the fourth level. As shown in Fig. G, it shifts to "1", and then the reference clock input terminal
When the 1801 level goes to '1' again, NAND gate 1816
Output level shifts to "1" as shown in FIG. Each of the NAND gates 1814, 1815, 1816 is a separate NA
Since the ND gate and bistable circuit are configured, when the output level shifts to '1', that state is held until a reset signal is applied to another NAND gate side, but the output of the NAND gate 1816 Pair when the level shifts to '1'
Since the output level of the NAND gate 1817 shifts to "0" and the output level of the AND gate 1818 shifts to "0", the output levels of the NAND gates 1814 and 1815 return to "0".

In this way, when the leading edge of the external signal (reproduction control signal in the embodiment of FIG. 1) arrives at the external signal input terminal 21, the data transfer terminal of FIG.
A signal waveform as shown in FIG. 4I is sent to 1813 via the AND gate 1819, and this signal causes the time base counter 1500 in FIG.
The count data is transferred to 00. The NA
The output signal of the ND gate 1816 is sent to the flag output terminal 1812 and is used as a capture flag signal indicating that the count data of the time base counter 1500 has been transferred, and the reset terminal 1811 sets this capture flag. The reset signal is applied after it is confirmed by the software (program) that this is done.

Next, FIG. 5 is a block diagram showing a concrete example of the capture register lock 1700, in which the data input terminals are respectively
D ₁ terminal to D ₁₆ units data output terminal is connected to the terminal which is constituted by 16 pieces of memory cells connected to the D ₀ terminal to D ₁₅ terminals each register 1710,1720,1730,1
740, and unit registers 1750 and 1760 each composed of 16 memory cells each having a data input terminal and a data output terminal connected to terminals D _{0 to} D ₁₅ respectively. Each unit register 1710 to 1760 has two control signal input terminals, and the read terminals 1711 to 1761 are respectively applied with the data transfer signal from the capture controller 1800 shown in FIG.
The select terminals 1712 to 1762 are applied with select signals for activating the output side of each unit register and reading out to the data bus 1600 of FIG. 1 via the data output O _{0 to} O ₁₅ terminals. .

Now, in FIG. 5, the connection positions of the data input terminals and the data output terminals of the unit registers 1710 to 1740 are shifted by one bit. This is for the following reason.

That is, for the unit registers 1750 to 1760, the LSB (least significant bit) of the time base counter 1500 is set in order to improve the resolution of the timing of capturing the edge of the external signal
The unit registers 1710 to 1740 have the same number of bits as the unit registers 1750 to 1760, but only one bit of data input terminal can be processed at one time so that a double interval can be processed at one time. It is shifting to the left.

With such a bit shift configuration of the unit registers 1710 to 1740, for example, the frequency of the reference value clock signal is set to 2
When selected to megahertz, the unit registers 1750 to 1760 provide count data with a resolution of 500 nanoseconds, while the unit registers 1710 to 1740 process the arrival cycle of an external signal with a frequency of about 30 hertz once. Can be measured at.

As is apparent from the above description, the magnetic tape recording speed discriminating apparatus of the present invention has a memory means for storing data (in the embodiment, it is constituted by the register 1100 or the RAM 1200) and the operation of the data. And an arithmetic means (in the embodiment, constituted by ALU1300) for executing
An instruction executing means (in the embodiment, constituted by the instruction executing circuit 1400) for storing the instructions to be sequentially executed and controlling the operations of the memory means and the arithmetic means based on the instructions, and the memory means. Drive means for moving the magnetic tape at a constant speed at at least two speeds based on command values such as 2H, 4H, and 6H stored in advance (in the embodiment, constituted by a drive amplifier 100 and a capstan motor 1). ), A time base counter 1500 for counting a reference clock signal, a capture register 1700 to which count data of the time base counter is supplied, and the capture when the edge of the identification signal recorded on the magnetic tape arrives. The capture controller 1800 that causes the register to fetch the count data and the instruction execution Interval calculation means for causing the calculation means to calculate the difference between the count data previously fetched and the newly fetched count data in response to an instruction from the means (in the embodiment, the processing block 1402 in FIG. 2 serves as the interval calculation means). And a recording speed discriminating means for discriminating the recording speed of the magnetic tape based on the interval calculation result and the command value (in the embodiment, the recording speed discriminating means is constituted by the branches 1403 to 1414 in FIG. 2). .) Is provided and the operation mode of the device can be easily changed only by changing the program stored in the instruction executing means, so that a dedicated complex hardware circuit becomes unnecessary. It is possible to obtain a magnetic tape recording speed determination device that can flexibly respond to various specifications changes as well. . Further, in the embodiment shown in FIG. 2, a time base counter incorporated for discriminating the recording speed of the magnetic tape.
Since the count data of 1500 is processed as the traveling phase detection data of the magnetic tape to operate the driving means, the data and the storage area thereof can be shared, which is a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a recording speed discriminating apparatus for a magnetic tape in one embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the main part of FIG. 1, and FIG. 3 is a diagram of the capture controller 1800 of FIG. A concrete logic circuit diagram, FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 3, and FIG.
The figure is a block diagram of the capture register block 1700. 1 ... Capstan motor, 100 ... Drive amplifier, 1100
...... Register, 1200 ...... RAM, 1300 ...... ALU, 1400 ...... Instruction execution circuit, 1500 ...... Time base counter, 1700 ......
Capture register block, 1800 ... Capture controller.

Front page continuation (72) Inventor Satoshi Kunihira 1006 Kadoma, Kadoma City, Matsushita Electric Industrial Co., Ltd. 57-15237 (JP, A) JP 59-22253 (JP, A)

Claims (2)

(57) [Claims] 1. A memory means for storing data, an arithmetic means for executing an arithmetic operation of data, an instruction to store an instruction to be sequentially executed, and an instruction for controlling operations of the memory means and the arithmetic means based on the instruction. The executing means, the driving means for running the magnetic tape at a constant speed at at least two speeds based on the command value stored in advance in the memory means, the time base counter for counting the reference clock signal, and the time base counter. A capture register to which count data is supplied, a capture controller that causes the capture register to capture the count data when the edge of the identification signal recorded on the magnetic tape arrives, and a command from the command execution unit The count data and the newly captured count Recording of a magnetic tape comprising interval calculation means for calculating the difference of data in the calculation means, and recording speed determination means for determining the recording speed of the magnetic tape based on the interval calculation result and the command value. Speed discriminator. 2. A memory means for storing data, an arithmetic means for executing an arithmetic operation of data, an instruction for sequentially executing an instruction, and an instruction for controlling operations of the memory means and the arithmetic means based on the instruction. Execution means, drive means for running the magnetic tape at a constant speed at at least two speeds based on speed command values stored in advance in the memory means, a time base counter for counting a reference clock signal, and the time base counter. Of the count data is supplied, a capture controller that causes the capture register to capture the count data when the edge of the identification signal recorded on the magnetic tape arrives, and an instruction from the instruction executing means. Count data previously captured and newly captured cow Interval calculation means for causing the calculation means to calculate the difference in the data, recording speed determination means for determining the recording speed of the magnetic tape based on the interval calculation result and the speed command value, and the count data for the magnetic tape. 2. A recording speed discriminating apparatus for a magnetic tape, comprising: a control means for processing the traveling phase detection data to operate the driving means.