JPH0191441A - Manufacture of semiconductor device and manufacturing equipment of semiconductor - Google Patents
Manufacture of semiconductor device and manufacturing equipment of semiconductorInfo
- Publication number
- JPH0191441A JPH0191441A JP25012587A JP25012587A JPH0191441A JP H0191441 A JPH0191441 A JP H0191441A JP 25012587 A JP25012587 A JP 25012587A JP 25012587 A JP25012587 A JP 25012587A JP H0191441 A JPH0191441 A JP H0191441A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- light
- laser
- deposition
- lamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000151 deposition Methods 0.000 claims abstract description 32
- 230000008021 deposition Effects 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 30
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 12
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052753 mercury Inorganic materials 0.000 abstract description 5
- 239000007789 gas Substances 0.000 abstract description 4
- 239000012495 reaction gas Substances 0.000 abstract description 4
- 238000007599 discharging Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 36
- 239000011229 interlayer Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は微細な凹凸を有する基板とに低温で薄膜を堆積
し平坦化する半導体装置の製造方法およびそれに用いる
半導体製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a thin film is deposited and planarized on a substrate having fine irregularities at a low temperature, and a semiconductor manufacturing apparatus used therefor.
従来の技術
LSIの集積度が増すにつれ、配線を多層に積み重ねる
技術が用いられている。層間絶縁膜を平坦化する方法と
しては、従来、S OG (Spin onglass
)の塗布法や、絶縁膜を高周波ヌパソタ法で堆積する
ときに基板側にもセルフバイアヌがかかるように高周波
電力を印加することにより、基板上で絶縁膜をエツチン
グしながら堆積するパイアノスパッタ法、及び第3図四
〜(5)に示すように、CVD法とレジストを用いて平
坦化した後、レジストと絶縁膜を同じ速度でエツチング
し、次に層間絶縁膜を堆積するエッチバック法等が用い
られている。第3図において、5oは81基板、62は
Al配線、54.60 ?′i、CV D S 10
2 B、56゜58はレジスト膜である。2. Description of the Related Art As the degree of integration of LSI increases, techniques for stacking wiring in multiple layers are being used. Conventionally, a method for planarizing an interlayer insulating film is SOG (Spin on Glass).
) coating method, piano sputtering method in which the insulating film is deposited while being etched on the substrate by applying high frequency power so that self-bias is applied to the substrate side when depositing the insulating film using the high frequency Nupasota method, As shown in Fig. 3 (4) to (5), after planarization using the CVD method and resist, the resist and insulating film are etched at the same rate, and then an interlayer insulating film is deposited using an etch-back method. It is used. In Fig. 3, 5o is 81 board, 62 is Al wiring, 54.60? 'i, CV D S 10
2B, 56° 58 is a resist film.
発明が解決しようとする問題点
しかしSOGは1μm程度の厚さではグラツクが発生す
るという問題がある。また、バイアスバッタ法ではプラ
ズマが素子特性を損傷する恐れがある。エッチバック法
は工程が複雑であシ、また一般的にA4配線上に絶縁膜
を形成する方法としてプラズマCVD法がよく用いられ
ているが、配線間隔が微細になるにつれ、プラズマCV
Dのステップ・カバレッジが良くないためにエッチバッ
ク法を用いてもボイドが発生するという問題もある。Problems to be Solved by the Invention However, SOG has the problem that cracks occur when the thickness is about 1 μm. Furthermore, in the bias battering method, there is a risk that plasma may damage device characteristics. The etch-back method requires a complicated process, and the plasma CVD method is generally used as a method to form an insulating film on A4 wiring, but as the wiring spacing becomes finer, plasma CVD
There is also the problem that voids occur even when the etch-back method is used because the step coverage of D is not good.
またバイアススパッタ法と同様にプラズマによるダメー
ジも問題となる。光CVD法はプラズマCVD法に比ベ
ステップ、カバレッジも良く、ダメージも少ないが、光
CVD法だけでは下地の段差がそのまま反映されるため
平坦化できない。Also, like the bias sputtering method, damage caused by plasma also poses a problem. Although the photo-CVD method has better step and coverage and less damage than the plasma CVD method, the photo-CVD method alone cannot achieve flattening because the level difference in the underlying layer is reflected as is.
本発明は、このような従来の問題に鑑み、これらの問題
を解決した半導体製造装置及びそれを用いた半導体装置
の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION In view of these conventional problems, an object of the present invention is to provide a semiconductor manufacturing apparatus that solves these problems and a method of manufacturing a semiconductor device using the same.
問題点を解決するための手段
本発明は、かかる問題点を解決すべく、基板に対しその
光が垂直に入射するように位置する第1の光源としての
レーザーと、前記レーザーと前記基板の間に位置し前記
基板の凹部にのみ前記レーザー光が入射するようにパタ
ーンの描かれたマスクと、第2の光源としてのランプと
から構成される光源を有する装置を用いる。そして、こ
の装置を用いて前記レーザー光と前記マスクによる前記
基板の凹部への薄膜の選択堆積と前記ランプ光による前
記基板上への薄膜の全面堆積の組合せによシ、凹凸を有
する前記基板上に平坦な薄膜を堆積することを特徴とす
る、光励起方式による半導体製造装置を提供し、さらに
は、その半導体製造装置を用いた、凹凸を有する半導体
基板上の凹部に第1の薄膜を選択的に堆積する工程と、
前記半導体基板上全面に第2の薄膜を堆積する工程とを
備え、前記第1及び第2の薄膜によシ前記半導体基板上
を平坦化することを特徴とする半導体装置の製造方法を
提供する。Means for Solving the Problems In order to solve these problems, the present invention provides a laser as a first light source positioned so that its light is perpendicularly incident on the substrate, and a laser between the laser and the substrate. A device is used that has a light source consisting of a mask located at the substrate and having a pattern drawn so that the laser beam is incident only on the concave portion of the substrate, and a lamp as a second light source. Using this apparatus, a combination of selective deposition of a thin film in the concave portions of the substrate using the laser beam and the mask, and deposition of the thin film over the entire surface of the substrate using the lamp light is applied to the substrate having irregularities. Provided is a semiconductor manufacturing device based on an optical excitation method, characterized in that a flat thin film is deposited on a semiconductor substrate, and further, the first thin film is selectively deposited on a concave portion of a semiconductor substrate having an uneven surface using the semiconductor manufacturing device. a step of depositing on
and depositing a second thin film on the entire surface of the semiconductor substrate, and flattening the semiconductor substrate using the first and second thin films. .
作用 本発明は上記構成により、次のように作用する。action With the above configuration, the present invention operates as follows.
■ レーザー光CVD法による基板凹部への選択的堆積
とランプ光CVD法による基板全面への堆積を組合せる
ことによって、平坦化できる。(2) Planarization can be achieved by combining selective deposition in the concave portions of the substrate using the laser light CVD method and deposition on the entire surface of the substrate using the lamp light CVD method.
■ レーザー光CVD法による選択堆積に用いるマスク
パターンを変えることによシ、基板のどのような凹凸形
状にも対応できる。(2) By changing the mask pattern used for selective deposition by laser light CVD, it is possible to adapt to any uneven shape of the substrate.
■ 光CVD法を用いているので、バイアススパッタ法
のようにプラズマが素子特性を損傷する恐れは無い。ま
た、低温で堆積できるのでAd配線上への膜堆積に適用
できる。(2) Since the optical CVD method is used, there is no risk of plasma damaging the device characteristics, unlike the bias sputtering method. Furthermore, since it can be deposited at a low temperature, it can be applied to film deposition on Ad wiring.
■ 同一装置内での堆積工程だけで平坦化できるのでエ
ッチバック法に比ベニ程か簡略化できる。■ Flattening can be achieved with just a deposition process in the same device, making it much simpler than the etch-back method.
実施例
まず、はじめに本発明方法に用いる半導体製造装置の構
成例について第1図を用いて説明する。Embodiment First, an example of the configuration of a semiconductor manufacturing apparatus used in the method of the present invention will be described with reference to FIG.
第1図へは、基板12に入射光が垂直に当たるように位
置する第1の光源としてのレーザー2と、選択堆積を行
うために所望の領域の入射光を遮断するマスク4と、第
2の光源としての水銀ランプ6と、ランプ効率を向上す
るため水銀ランプの周囲に位置するミラー8と、光透過
窓1oと、基板12を加熱するためのヒーター14を有
し基板12を固定するサセプタ18と、膜の堆積を行う
反応室16と、原料ガスの導入系及び反応ガスの排気系
とから構成された光CVD装置である。FIG. 1 shows a laser 2 as a first light source positioned so that the incident light hits the substrate 12 perpendicularly, a mask 4 that blocks the incident light in a desired area for selective deposition, and a second laser. A susceptor 18 that has a mercury lamp 6 as a light source, a mirror 8 located around the mercury lamp to improve lamp efficiency, a light transmission window 1o, and a heater 14 for heating the substrate 12 and fixes the substrate 12. This is an optical CVD apparatus composed of a reaction chamber 16 in which a film is deposited, a source gas introduction system, and a reaction gas exhaust system.
この構造によれば、同一反応室内においてレーザー光に
よる選択堆積とランプ光による全面堆積を連続しである
いは同時に行える。According to this structure, selective deposition using laser light and full-scale deposition using lamp light can be performed successively or simultaneously in the same reaction chamber.
あるいは、第1図(至)は、第1の光源としてのレーザ
ー2と、選択堆積を行うために所望の領域の入射光を遮
断するマスク4と、第1の光透過窓10Aと、基板12
Aを加熱するための第1のヒーター14Aと、基板12
Aを固定するサセプタ18Aと、原料ガスの導入系及び
反応ガスの排気系とを有し、選択的膜堆積を行うための
第1の反応室16Aと、第2の光源としての水銀ランプ
6と、ランプ効率を向上するだめのミラー8と、第2の
光透過窓10Bと、基板12Bを加熱するための第2の
ヒーター14Bと、基板12Bを固定するサセプタ18
Bと、原料ガスの導入系及び反応ガスの排気系とを有し
、基板12B全面に膜堆積を行うための第2の反応室と
から構成された光CVD装置である。Alternatively, FIG. 1 (to) shows a laser 2 as a first light source, a mask 4 that blocks incident light in a desired area for selective deposition, a first light transmitting window 10A, and a substrate 12.
A first heater 14A for heating the substrate 12
A susceptor 18A for fixing A, a first reaction chamber 16A having a source gas introduction system and a reaction gas exhaust system and for performing selective film deposition, and a mercury lamp 6 as a second light source. , a mirror 8 for improving lamp efficiency, a second light transmission window 10B, a second heater 14B for heating the substrate 12B, and a susceptor 18 for fixing the substrate 12B.
This is an optical CVD apparatus consisting of a second reaction chamber having a source gas introduction system and a reaction gas exhaust system, and for depositing a film on the entire surface of the substrate 12B.
この構造によれば、第1図式に示す装置のように、レー
ザー光による選択堆積とランプ光による全面堆積を同時
に行うことはできないが、レーザー光CVDとランプ光
CVDとに用いる光透過窓が異なるため、光透過窓にも
膜堆積が起こるために膜の堆積速度が低下する度合は、
第1図(B)に示す装置は第1図四に示す装置に比べ少
ないという利点がある。According to this structure, unlike the apparatus shown in the first diagram, it is not possible to perform selective deposition using laser light and full-surface deposition using lamp light at the same time, but the light transmission windows used for laser light CVD and lamp light CVD are different. Therefore, the degree to which the film deposition rate decreases due to film deposition also occurring on the light-transmitting window is:
The device shown in FIG. 1(B) has the advantage of being smaller than the device shown in FIG. 14.
さらには1本発明の半導体製造装置を用いた半導体装置
の製造方法の実施例を具体例に基づいて説明する。Furthermore, an embodiment of a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus of the present invention will be described based on a specific example.
第2図四〜(qは本発明による実施例で2層配線の製造
工程を示す。81基板100に回路素子が作成され、A
lによってパッドや配線等となる第1の導体102A〜
102Cが形成されている。FIG. 2 4-(q shows the manufacturing process of two-layer wiring in an embodiment according to the present invention. 81 A circuit element is created on the substrate 100,
The first conductor 102A that becomes a pad, wiring, etc.
102C is formed.
まず、第2図へのように、A4配線102の間隔が1μ
m以上の広い部分のSi基板100上にレーザー光CV
D法により選択的に絶縁膜としての第1の8102膜パ
p−7104をAd配線102よりも少し厚く形成する
。この時、例えば1μmの厚さのS iO2膜を形成し
たとすると、レーザー光のマスクパターン端部より2〜
3μm程度の広がシでなだらかな傾斜を有するS 10
2膜パターンとなっている。次に第2図(I3)のよう
に、ランプ光CVD法によりSt基板1oO上全面に第
2の5102膜106を1μm程度形成して、はぼ平坦
な層間絶縁膜が形成される。その後、S z 02膜1
04 、106の所望の領域をエツチングしてヌル−ホ
ールを形成し、次に第2の導体として(7fil配線1
08を形成して第2図(qのように2層配線が得られる
。First, as shown in FIG.
Laser light CV is applied onto the Si substrate 100 over a wide area of m or more.
A first 8102 film P-7104 as an insulating film is selectively formed using the D method to be slightly thicker than the Ad wiring 102. At this time, for example, if a SiO2 film with a thickness of 1 μm is formed, the mask pattern edge of the laser beam will be
S10 with a gentle slope with a spread of about 3 μm
It has a two-layer pattern. Next, as shown in FIG. 2 (I3), a second 5102 film 106 with a thickness of about 1 μm is formed on the entire surface of the St substrate 1oO by the lamp light CVD method, thereby forming a substantially flat interlayer insulating film. After that, S z 02 film 1
04, 106 to form a null-hole and then as a second conductor (7fil wiring 1
08 to obtain a two-layer wiring as shown in FIG. 2 (q).
5i02 膜パターン104を形成することによシ、S
t基板1oo上には幅1μm以内の凹部しか存在しなく
なるため、5102膜106を1μm程度形成すれば、
表面はほぼ平坦になる。5i02 By forming the film pattern 104, S
Since only a recess with a width of 1 μm or less exists on the t-substrate 1oo, if the 5102 film 106 is formed with a thickness of about 1 μm,
The surface will be almost flat.
平坦な層間絶縁膜が形成されることによシ、上層の配線
を形成した際、断線することが無くなるという効果があ
る。Formation of a flat interlayer insulating film has the effect of eliminating disconnection when forming upper layer wiring.
なお、上記第2の実施例においては、レーザー光CVD
による第1のS z 02膜パターン104の堆積をし
た後ランプ光CVDによシ第2のS10β106を堆積
しているが、膜堆積を同時に行っても平坦なS z 0
2膜が堆積できる。また、絶縁膜は、Si○以外にSi
3N4や5ioNでもよい。Note that in the second embodiment, laser light CVD
After the first S z 02 film pattern 104 is deposited by the method, the second S 10β 106 is deposited by lamp light CVD.
Two films can be deposited. In addition to Si○, the insulating film is made of Si
3N4 or 5ioN may also be used.
まだ、上記第2の実施例は層間絶縁膜の形成について説
明したが、本発明の方法は、それ以外にもトレンチ分離
における絶縁膜の埋込み等、凹凸を有する基板上に平坦
な膜を堆積する工程に適用することができる。Although the second embodiment described above describes the formation of an interlayer insulating film, the method of the present invention can also be used to deposit a flat film on an uneven substrate, such as burying an insulating film in trench isolation. It can be applied to the process.
発明の効果
以上述べてきたように本発明の半導体装置の製造方法お
よび半導体製造装置によれば、次のような効果が得られ
る。Effects of the Invention As described above, according to the semiconductor device manufacturing method and semiconductor manufacturing apparatus of the present invention, the following effects can be obtained.
■ レーザー光CVD法による基板凹部への選択的堆積
とランプ光CVD法による基板全面への堆積を組合せる
ことによって、平坦な膜堆積ができる。(2) A flat film can be deposited by combining selective deposition in the concave portions of the substrate by laser light CVD and deposition on the entire surface of the substrate by lamp light CVD.
■ 光CVD法を用いているので、プラズマによる素子
特性の損傷が無い。(2) Since the photo-CVD method is used, there is no damage to device characteristics due to plasma.
■ 同一装置内での堆積工程だけで平坦化できるので工
程が簡略でアル。■ Flattening can be achieved by simply depositing in the same device, which simplifies the process.
■ 多層配線の層間絶縁膜の形成に適用すれば、上層の
配線の断線が防止できる。また、多層配線を実現するこ
とによシ素子の高集積化が計れる。■ If applied to the formation of an interlayer insulating film for multilayer wiring, disconnection of upper layer wiring can be prevented. Furthermore, by realizing multilayer wiring, it is possible to achieve high integration of the elements.
以上のように、本発明は素子にダメージを与えることな
く平坦な絶縁膜を簡易な工程で形成でき、素子の高集積
化並びに信頼性の向上に大きく寄与するものである。As described above, the present invention can form a flat insulating film through a simple process without damaging the device, and greatly contributes to higher integration and reliability of the device.
第1図は本発明方法に用いる半導体製造装置を示す概略
断面図、第2図は同半導体製造装置を用いた半導体装置
の製造方法め実施例を説明するための工程断面図、第3
図は従来の平坦化法の1つであるエッチバック法を説明
するだめの工程断面図である。
2・・・・・・レーザー、4・・・・・・マスク、6・
・・・・・水銀ランプ、10・・・・・・光透過窓、1
6・・・・・・反応室、18・・・・・・サセプタ、1
2,50,100・・・・・・Si 基板、62 、1
02 、108−・−−−−Al&MA、54,60゜
104 * 106 ”・・・・CV D S 10
2膜、56.58・・・・・・レジスト膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名2−
m−し−ヂー
4・−マスク()ぐグーン有)
乙−水錘乃ンフ。
8− ミラー
to −−−−1f、±過−懇
12・−基板
14− ヒーター
(ハラ
/8/6
第1図
(B)
/、!3A l6A
2−m−し−ブ−
4−−−マスク()ぐグーン腐)
6− 水4艮ランプ
8− ミラー
10−一尤透、逢慈
12−基板
14−−−ヒーター
16−及瓦・呈
/8−”!7”ゼア゛り
18B 16β
lθ0−5i基板
lθと−Al百己8養(第1導イネハ゛ターンリlθ4
−−3t(h膜パターン(レーー尤CVr)−3dhl
j)10δA
/IZA/(7281Rc
50−−− Si基板
52−Af西已線
54−−− CVD−8,i、0こ膜(却U株膜)第
3 図FIG. 1 is a schematic cross-sectional view showing a semiconductor manufacturing apparatus used in the method of the present invention, FIG. 2 is a process cross-sectional view for explaining an embodiment of a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus,
The figure is a process cross-sectional view for explaining the etch-back method, which is one of the conventional planarization methods. 2...Laser, 4...Mask, 6.
...Mercury lamp, 10...Light transmission window, 1
6...Reaction chamber, 18...Susceptor, 1
2,50,100...Si substrate, 62, 1
02, 108----Al&MA, 54,60°104*106''...CV D S 10
2 film, 56.58...Resist film. Name of agent: Patent attorney Toshio Nakao and 1 other person2-
M-shi-ji 4・-mask ()gugoonyu) Otsu-Mizuannofu. 8-Mirror to---1f, ±over-contact 12・-substrate 14-Heater (Hara/8/6 Fig. 1(B)/,!3A l6A 2-m-shi-bu-4--- Mask () Gugoonro) 6- Water 4 lamp 8- Mirror 10- One-pass, Aiji 12- Substrate 14-- Heater 16- and tile display/8-"!7" Zea-ri 18B 16β lθ0-5i substrate lθ and -Al 100% (first conductor return lθ4
--3t (h film pattern (CVr) -3dhl
j) 10δA /IZA/(7281Rc 50--- Si substrate 52-Af Nishihama line 54--- CVD-8, i, 0 film (U stock film) No.
3 diagram
Claims (2)
る第1の光源としてのレーザーと、前記レーザーと前記
基板の間に位置し前記基板の凹部にのみ前記レーザー光
が入射するようにパターンの描かれたマスクとを用いて
前記基板の凹部に選択的に薄膜を形成する工程と、第2
の光源としてのランプにより前面に薄膜を形成する工程
とを備え、凹凸を有する前記基板上に平坦な薄膜を堆積
するようにした半導体装置の製造方法。(1) A laser as a first light source positioned so that its light is perpendicularly incident on the substrate, and a laser that is positioned between the laser and the substrate so that the laser beam is incident only on the concave portion of the substrate. selectively forming a thin film in the concave portions of the substrate using a patterned mask;
forming a thin film on the front surface using a lamp as a light source, and depositing a flat thin film on the uneven substrate.
る第1の光源としてのレーザーと、前記レーザーと前記
基板の間に位置し前記基板の凹部にのみ前記レーザー光
が入射するようにパターンの描かれたマスクと、第2の
光源としてのランプとから構成される光源を有し、前記
レーザー光と前記マスクによる前記基板の凹部への選択
堆積と前記ランプ光による前記基板上への全面堆積を行
う半導体製造装置。(2) A laser as a first light source positioned so that its light is perpendicularly incident on the substrate, and a laser that is positioned between the laser and the substrate so that the laser beam is incident only on the concave portion of the substrate. It has a light source consisting of a mask with a pattern drawn thereon and a lamp as a second light source, and selectively deposits onto the concave portions of the substrate using the laser beam and the mask, and deposits onto the substrate using the lamp light. Semiconductor manufacturing equipment that performs full-surface deposition.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25012587A JPH0191441A (en) | 1987-10-02 | 1987-10-02 | Manufacture of semiconductor device and manufacturing equipment of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25012587A JPH0191441A (en) | 1987-10-02 | 1987-10-02 | Manufacture of semiconductor device and manufacturing equipment of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0191441A true JPH0191441A (en) | 1989-04-11 |
Family
ID=17203194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25012587A Pending JPH0191441A (en) | 1987-10-02 | 1987-10-02 | Manufacture of semiconductor device and manufacturing equipment of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0191441A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160020031A1 (en) * | 2014-07-18 | 2016-01-21 | Samsung Electro-Mechanics Co., Ltd. | Composite electronic component and board having the same |
-
1987
- 1987-10-02 JP JP25012587A patent/JPH0191441A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160020031A1 (en) * | 2014-07-18 | 2016-01-21 | Samsung Electro-Mechanics Co., Ltd. | Composite electronic component and board having the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3216104B2 (en) | Metal plug forming method and wiring forming method | |
JPH0645327A (en) | Semiconductor device and manufacture thereof | |
JPH05206128A (en) | Method for formation of metal interlayer insulating film in semiconductor device | |
JPS60502179A (en) | How to interconnect metal layers | |
JPH08330305A (en) | Insulation film formation of semiconductor device | |
JPH03295239A (en) | Manufacture of semiconductor device | |
JPH0191441A (en) | Manufacture of semiconductor device and manufacturing equipment of semiconductor | |
JPH06124948A (en) | Wiring forming method | |
US6214735B1 (en) | Method for planarizing a semiconductor substrate | |
JP2716156B2 (en) | Method for manufacturing semiconductor device | |
JPH0645313A (en) | Manufacture of semiconductor device | |
JPH08203891A (en) | Fabrication of semiconductor device | |
JPH0758104A (en) | Manufacture of semiconductor device | |
JPS63131546A (en) | Semiconductor device | |
JP2001337241A (en) | Method for manufacturing optical waveguide | |
JPH0611044B2 (en) | Method for manufacturing semiconductor device | |
JPH0590203A (en) | Manufacture of semiconductor device | |
JPS59139648A (en) | Manufacture of semiconductor device | |
GB2026797A (en) | Microelectronic circuit and method of manufacture | |
JPH01135044A (en) | Semiconductor device | |
KR19990021110A (en) | Planarization method of semiconductor device | |
JP2001091779A (en) | Semiconductor waveguide element and its manufacturing method | |
JPS59195845A (en) | Fabrication of multilayer interconnection | |
JPH07122634A (en) | Semiconductor device | |
JPS5892226A (en) | Manufacture of integrated circuit element |