GB2026797A - Microelectronic circuit and method of manufacture - Google Patents
Microelectronic circuit and method of manufacture Download PDFInfo
- Publication number
- GB2026797A GB2026797A GB7926096A GB7926096A GB2026797A GB 2026797 A GB2026797 A GB 2026797A GB 7926096 A GB7926096 A GB 7926096A GB 7926096 A GB7926096 A GB 7926096A GB 2026797 A GB2026797 A GB 2026797A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- conductive material
- substrate
- microelectronic circuit
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004377 microelectronic Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000005291 magnetic effect Effects 0.000 claims abstract description 13
- 239000011810 insulating material Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 230000005294 ferromagnetic effect Effects 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000002223 garnet Substances 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- 229910000889 permalloy Inorganic materials 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241001148599 Gorgonidium Species 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 231100001261 hazardous Toxicity 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/06—Thin magnetic films, e.g. of one-domain structure characterised by the coupling or physical contact with connecting or interacting conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
- H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Magnetic Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
In a magnetic bubble domain circuit, a conductive layer 13 on a garnet substrate 10 is etched to form conductor patterns. The grooves through the layer 13 are filled with an insulating material, e.g. a glass, 21, 22, 23, to provide a flat surface. Therefore when an insulating layer and patterned permalloy overlay 25 are subsequently provided, there are no steps in the overlay. This eliminates a source of defects and the uniform spacing of the overlay from the substrate results in better operating characteristics. The same technique, employing a flat surface, can be used in semiconductor circuits. <IMAGE>
Description
SPECIFICATION
Microelectronic circuit and method of manufacture
This invention relates to microelectronic circuits and is specifically useful in circuits employing semiconductor devices or magnetic bubble domain devices.
Microelectronic circuits are being made ever smaller, as fineline lithography and other fabrication techniques are developed and improved. The circuits are typically made by producing layers of materials sequentially on an original substrate. Each new layer generally follows the contours of the preceding layers.
Consequently, a non-planar device is produced which has many known shortcomings or hazardous processing steps. Thus, in the multilevel devices, crossover areas, corners and so on are frequently subject to problems such as cracks, discontinuities or other defects.
In addition, and notably in magnetic bubble domain circuits, thermal gradients can be produced as a result of localized power requirements which are utilized for switching or other operations. The thermal gradients result in severe margin degradation because of the lack of thermal uniformity over large area magnetic bubble domain chips. In a problem which is peculiar to magnetic bubble domain structures, device characterization by optical/visual techniques suffers from lack of bubble domain contrast as the bubble domain diameter decreases and as the layer of bubble domain material becomes thinner.
Non-planar bubble domain device operating margins suffer a degradation due to the fact that all the permalloy elements cannot be located at the optimum spacing distance from the garnet substrate. Further, higher drive field power is required to operate the non-planar device compared to planar devices. Therefore, comprises have to be made in the bubble domain device component design to allow for the non-planar nature of the topographical features.
All of the problems noted above affect yield and performance characteristics. However, no suitable solution has previously been proposed which can solve one or more of these shortcomings.
According to the present invention there is provided, a microelectronic circuit comprising a substrate, a layer of electrically conductive material on the substrate having channels therethrough forming a pattern of conductive portions, a layer of insulating material in the channels flush with the surface of the layer of conductive material, and microelectronic devices formed on the flat surface of the layer of conductive material and the insulating material.
The invention further provides a method of manufacturing a microelectronic circuit, comprising the steps of forming a layer of electrically conductive material on the surface of a substrate, etching channels in the layer of conductive material to form a pattern of the layer of conductive material, filling the channels with an electrically insulating material flush with the surface of the layer of conductive surface, and forming microelectronic circuit devices on the flat surface thereby provided.
The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:
Figures 1 to 4 are cross-sectional views of a bubble domain circuit embodying the invention in successive manufacturing steps, and
Figure 5 is a top view of the circuit as shown in Figure 3.
In Figure 1, a plurality of layers are shown on a
substrate 10 which may be of an suitable material
for a microelectronic circuit, e.g. a semiconductor.
However, for the purposes of this explanation, the
substrate 10 may be considered to be a magnetic
bubble domain material such as a suitable garnet
which is well known in the art. The garnet substrate may be of any suitable thickness such as
about 0.5 mm. Deposited on the surface of the substrate 10 is a layer 1 1 of a dielectric isolation
material, e.g. Schott glass about 300 to 1000
angstrom thick. The layer 11 may be deposited
using E-beam evaporation at a substrate temperature of approximately 2000C.
A thin layer 12 of nickel-chrome (NiCr) about 25 to 150 angstrom thick is deposited on the upper surface of layer 11. This thin, flash layer is used primarily to establish and enhance adhesion of subsequent layers to the layer 11. The layer 12
may not be needed if the subsequent material has a characteristically good adhesion to the layer 11.
A layer 13 formed of material which is conductive, both thermally and electrically, is then provided on the layer 12, e.g. by evaporation or electrodeposition. The layer 13 # may have a thickness of 1000 to 6000 angstrom. The type of
material depends on the characteristics required by the microelectronic device but the layer 13 may be a copper-doped-aluminium.
A further adhesion layer 14 which is similar to the adhesion layer 12 is provided on the surface of conductor layer 13 and may be about 25 to 200 angstrom thick. The layer 14 also performs the function of providing an electrochemical or electroless chemical plating surface for increasing the thickness of conductor bonding pads.
A masking layer 15 is then provided on the upper surface of the adhesion layer 14 and may be photoresist type AziAZ1350~J manufactured by Shipley. The thickness of the masking layer 1 5 depends on the processes to be used but may be
1.0 to 2.0 micron. Masking layer 1 5 is then treated in the appropriate manner for establishing a mask, e.g. being exposed to ultraviolet light and developed. The mask is used in an etching operation which may be chemical etching, although ion milling or other dry etching techniques can be utilized.
The etching removes the material between dashed lines 16, 17 and 18 completely through to the isolation layer 11. By using ion milling techniques and with the appropriate thicknesses of the materials, substantially vertical walls (defined by lines 16, 17 and 18) can be produced but chemical etching has also proved satisfactory.
Referring now to Figure 2, a second layer of
Schott glass or other isolation material is provided over the surface of the entire structure shown in
Figure 2 to a thickness of about 1000 to 6000 angstrom, being substantially the same as the sum of the thicknesses of the conductive layer 1 3
and adhesion layers 12 and 14. Thus, a relatively
uniform thickness layer 20 is provided on the surface of the masking layer 1 5 where it exists. In addition, a relatively uniform thickness of the glass is formed at portions 21, 22 and 23 in the channels or grooves etched in the composite structure. The second Schott glass layer 20 may also be provided by using a standard E-beam deposition method.
Referring now to Figure 3, there is shown the composite structure from Figure 2 after lifting off the masking layer 15 e.g. by soaking in a solution such as warm acetone for a short time (e.g. 10 to
15 minutes). This soak is usually sufficient to swell and dissolve the masking layer 15 so that it and any materials deposited thereon are removed.
Consequently, a planar surface is provided by the conductive layer 13 (coated with layer 14) and isolation layer portions 21, 22 and 23. As is shown in Figure 5, conductive layer portions 13A and 1 38 are isolated from the remainder of the conductive layer 13; they could also be isolated from each other by the isolation portion 22. The actual pattern of the portions of the layer 13 depends on the design of the circuit. Any desirable cleaning steps can be undertaken, such as ultrasonically removing any of the masking layer
15 which may adhere to the composite, cleaning offthe acetone and so on.
Once the cleansing processes have been completed, the final layers can be formed.
Referring to Figure 4, a composite structure representative of a magnetic bubble domain device is shown. A thin layer 24 of silicon dioxide (SiO2) or other suitable dielectric material is deposited over the surface of the composite structure, with a thickness of about 300 to 3000 angstrom. The dielectric layer can be provided by means of sputter deposition. Thereafter, a layer 25, which is preferably a permalloy, is deposited on the layer 24. The layer 25 can be 3500 + 200 angstrom thick and can also be sputtered or otherwise deposited. Suitable patterns can be produced in the layer 25 by using a photoresist mask and ion milling or chemical etching. The
photoresist is then stripped and passivation layer 26 of dielectric material can be deposited to a thickness of 1000 to 30000 angstrom.
In Figure 5, portions of some of the layers have
been removed in order to show the substrate 10
as well as the layer 11 and conductive layer 13
thereon. The intermediate adhesion layers are not
shown. The relationship of the isolation layer
portions 21,22 and 23 to the conductive layer 13
and its portions 13A and 1 3B is also shown. Thus a conductor loop is shown as an example and the ends of the loop can be exposed for forming conductive pads and attachment of leads. More complicated conductor patterns can be produced.
The composite structure of Figure 3 permits planar devices to be produced; various switching devices and so on can be fabricated. In magnetic bubble domain devices, a lower drive field is permitted and a wider margin is produced. In addition, switch resistance on magnetic bubble domain devices can be substantially reduced for a given design. Also increased design flexibility is permitted in fabricating circuits.
In addition, the large area of thermally conductive layer 13 is able to distribute temperature gradients and operate as a heat sink.
This facility reduces thermal gradients from one area to another in the microelectronics structure and is especially desirable and useful in magnetic bubble domain circuits.
Another advantage of this composite structure is in the testing thereof. That is, optical/visual testing has been performed in the past wherein the contrast between the bubble domain and the surrounding layer of magnetic bubble domain material is observed. Of course, as bubbles become smaller the contrast is more difficult to observe. Furthermore, as the bubble layer (i.e.
garnet substrate 10) becomes thinner in order to establish smaller diameter bubbles, contrast is also reduced. In the past, optical rotation and other effects have been employed in reflecting a light beam from the propagation layer in order to enhance the contrast. In the composite structure shown and described herein, the conductive layer 13 also serves as a mirror surface which reflects any light projected from beneath the substrate.
This highly reflective layer operates to improve the reflection of the device vastly and, thus to enhance the contrast and the visual testing capability.
The advantages of the planar device in various processing techniques will be clear. The crossover and step fabrication problems are eliminated, difficulties in fabrication uniformity are reduced and surface abrasion is minimized because of the lack of steps to be abraded.
Claims (12)
1. A microelectronic circuit comprising a substrate, a layer of electrically conductive material on the substrate having channels therethrough forming a pattern of conductive portions, a layer of insulating material in the channels flush with the surface of the layer of conductive material, and microelectronic devices formed on the flat surface of the layer of conductive material and the insulating material.
2. A microelectronic circuit according to claim 1, including an isolation layer on the substrate between the substrate and the layer of conductive material.
3. A microelectronic circuit according to claim 2, including an adhesion layer between the isolation layer and the layer of conductive material.
4. A microelectronic circuit according to claim 1, 2 or 3, including a layer of dielectric material disposed between the layer of conductive material and the microelectronic devices.
5. A microelectronic circuit according to claim 1, comprising a layer of dielectric material on the flat surface and herein the substrate is a magnetic bubble domain material, and the said devices are elements of a magnetic overlay pattern on the layer of dielectric material, the said pattern of conductive portions providing conductors for controlling the propagation of the bubble domains.
6. A microelectronic circuit according to any of claims 1 to 5, wherein the layer of conductive material is non-ferromagnetic.
7. A microelectronic circuit according to any of claims 1 to 6, wherein the conductive material is indium-doped-silver.
8. A method of manufacturing a microelectronic circuit, comprising the steps of forming a layer of electrically conductive material on the surface of a substrate, etching channels in the layer of conductive material to form a pattern of portions of the layer of conductive material, filling the channels with an electrically insulating material flush with the surface of the layer of conductive surface, and forming microelectronic circuit devices on the flat surface thereby provided.
9. A method according to claim 8, wherein a layer of dielectric material is formed on the substrate before forming the layer of conductive material.
10. A method according to claim 8 or 9, wherein a passivation layer is formed on the microelectronic circuit devices.
11. A method according to claim 8, 9 or 10, wherein the channels are etched through a mask formed on the layer of conductive material.
12. A method according to claim 11, wherein the electrically insulating material is deposited over the whole composite structure before removing the mask to such a thickness as to fill the etched channels flush, and the mask is then removed with the insulating material thereon.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US92848778A | 1978-07-27 | 1978-07-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2026797A true GB2026797A (en) | 1980-02-06 |
| GB2026797B GB2026797B (en) | 1982-07-07 |
Family
ID=25456302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7926096A Expired GB2026797B (en) | 1978-07-27 | 1979-07-26 | Microelectronic circuit and method of manufacture |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5525893A (en) |
| DE (1) | DE2929297A1 (en) |
| GB (1) | GB2026797B (en) |
| IT (1) | IT1118119B (en) |
| NL (1) | NL7905689A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990003046A1 (en) * | 1988-05-31 | 1990-03-22 | Unisys Corporation | Integrated circuit employing dummy conductors for planarity |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618117A (en) * | 1984-06-20 | 1986-01-14 | Power Reactor & Nuclear Fuel Dev Corp | Arrangement of rotor receiving apparatus |
-
1979
- 1979-07-19 DE DE19792929297 patent/DE2929297A1/en not_active Withdrawn
- 1979-07-23 NL NL7905689A patent/NL7905689A/en not_active Application Discontinuation
- 1979-07-24 JP JP9483379A patent/JPS5525893A/en active Pending
- 1979-07-24 IT IT49851/79A patent/IT1118119B/en active
- 1979-07-26 GB GB7926096A patent/GB2026797B/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990003046A1 (en) * | 1988-05-31 | 1990-03-22 | Unisys Corporation | Integrated circuit employing dummy conductors for planarity |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5525893A (en) | 1980-02-23 |
| IT1118119B (en) | 1986-02-24 |
| NL7905689A (en) | 1980-01-29 |
| IT7949851A0 (en) | 1979-07-24 |
| GB2026797B (en) | 1982-07-07 |
| DE2929297A1 (en) | 1980-02-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |