KR100248356B1 - Method for semiconductor device - Google Patents
Method for semiconductor device Download PDFInfo
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- KR100248356B1 KR100248356B1 KR1019970030223A KR19970030223A KR100248356B1 KR 100248356 B1 KR100248356 B1 KR 100248356B1 KR 1019970030223 A KR1019970030223 A KR 1019970030223A KR 19970030223 A KR19970030223 A KR 19970030223A KR 100248356 B1 KR100248356 B1 KR 100248356B1
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- South Korea
- Prior art keywords
- pattern
- metal wiring
- insulating layer
- semiconductor device
- groove
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000005368 silicate glass Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 미세패턴 제조방법에 관한 것으로, 특히 배선마스크가 허용하는 최소선폭 보다 작게 금속배선패턴을 형성함으로써 배선간의 상호간섭, 커플링 등의 기생효과를 줄여 소자의 전기적 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a fine pattern of a semiconductor device, and in particular, by forming a metal wiring pattern smaller than the minimum line width allowed by the wiring mask, thereby reducing parasitic effects such as mutual interference and coupling between wirings, thereby improving electrical characteristics and reliability of the device. It is about a technique to improve.
이를 위한 본 발명은 반도체 기판 상부에 제 1절연막과 감광막패턴을 형성하고 상기 감광막패턴을 마스크로 상기 제 1 절연막을 식각하여 홈을 형성한 다음, 전표면에 제 2절연막을 형성하고 상기 홈을 매립하는 금속배선을 형성한 후, 에치-백 및 CMP공정으로 상기 제 2절연막이 노출될때 까지 연마하여 금속배선패턴을 형성하는 반도체 소자의 미세패턴 제조방법을 제공한다.According to the present invention, a first insulating layer and a photoresist pattern are formed on a semiconductor substrate, and the groove is formed by etching the first insulating layer using the photoresist pattern as a mask, and then a second insulating layer is formed on the entire surface, and the groove is buried. After the metal wiring is formed, the semiconductor device provides a method of manufacturing a fine pattern of a semiconductor device in which a metal wiring pattern is formed by polishing until the second insulating layer is exposed by an etch-back and a CMP process.
Description
본 발명은 반도체 소자의 미세패턴 제조방법에 관한 것으로, 특히 배선마스크가 허용하는 최소선폭 보다 작게 금속배선패턴을 형성함으로써 배선간의 상호간섭, 커플링 등의 기생효과를 줄여 소자의 전기적 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE
일반적으로, 반도체 소자가 고집적화됨에 따라 소자 제조공정에 있어 보다 작은 디자인룰(design rule)이 요구되는데, 현재 약 0.3㎛이하의 선폭을 형성하기 위해 노광 과정에서의 노광원은 원자외선(DUV)이 사용되고 있으며, 콘택(contact) 노광 과정에서의 미스-어라인(miss align)에 의한 상부 배선과 하부 배선 사이의 단락을 방지하기 위해 셀프-어라인드 콘택트(Self-Aligned Contact 이하, SAC) 공정이 도입되고 있는 실정이다.In general, as the semiconductor devices are highly integrated, smaller design rules are required in the device manufacturing process. In order to form a line width of about 0.3 μm or less, the exposure source in the exposure process is far ultraviolet (DUV). Self-Aligned Contact (SAC) process is introduced to prevent short-circuit between upper and lower wiring due to miss align during contact exposure. It's happening.
제1a도 내지 제1c도는 종래 기술에 따른 반도체 소자의 미세패턴 제조공정도이다.1A to 1C are diagrams illustrating a process of manufacturing a fine pattern of a semiconductor device according to the prior art.
먼저, 반도체 기판(1) 상부에 산화막의 재질로 이루어진 제 1 절연막(3)과 감광막패턴(5)을 형성한다.First, the first
다음, 상기 감광막패턴(5)을 마스크로 상기 제 1 절연막(3)을 식각하여 일정 깊이의 홈(7)을 형성한 다음, 상기 감광막패턴(5)을 제거한다.(제1a도 참조)Next, the first insulating
그 다음, 상기 홈(7)을 매립하는 일정 두께의 금속배선(9)을 형성한다.(제1b도 참조)Next, a
다음, CMP(chemical mechanical polishing)공정으로 상기 제 1절연막(3)이 노출될때 까지 연마하여 금속배선(9)패턴을 형성한다.(제1c도 참조)Next, by the chemical mechanical polishing (CMP) process, the first
상기와 같은 종래 기술에 따르면, 디바이스의 고밀도화에 비례하여 배선밀도가 증가하고 있으며 이에 따라 배선과 배선간의 상호 간섭작용, 커플링 커패시턴스(coupling capacitance)등 원하지 않는 기생효과를 발생하는 문제점이 있다.According to the prior art as described above, the wiring density is increased in proportion to the increase in the density of the device, and thus there is a problem in that unwanted parasitic effects such as mutual interference between the wiring and the wiring, coupling capacitance, etc. are generated.
이때, 배선의 선폭을 줄임으로써 상기한 기생효과를 감소시킬 수는 있으나 배선폭을 마스크의 허용 최소선폭 이하로 제작하기에는 많은 어려움이 있다.At this time, the parasitic effect can be reduced by reducing the line width of the wiring, but there are many difficulties in manufacturing the wiring width below the allowable minimum line width of the mask.
또한, 상기 배선폭은 광마스크 및 기존 노광기술로 웨이퍼 상에 형성할 수 있는 최소 선폭에 의해 제한을 받게 된다.In addition, the wiring width is limited by the minimum line width that can be formed on the wafer by the optical mask and conventional exposure techniques.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 금속배선으로 예정된 부위의 제 1절연막을 식각하여 금속배선용 홈을 형성한 다음, 금속배선을 바로 증착하지 않고 제 2절연막을 일정 두께 증착하여 금속배선 폭을 줄인 후에 금속배선을 증착하여 금속배선 폭의 배선마스크가 허용하는 최소선폭 보다 작게 금속배선 패턴을 형성함으로써 배선간의 상호간섭, 커플링 등의 기생효과를 줄여 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체 소자의 미세패턴 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems to form a groove for the metal wiring by etching the first insulating film of the predetermined portion of the metal wiring, and then depositing a second thickness of the second insulating film without directly depositing the metal wiring to the metal wiring After reducing the width, the metal wiring is deposited to form a metal wiring pattern smaller than the minimum wire width allowed by the wiring mask of the metal wiring width, thereby reducing parasitic effects such as mutual interference and coupling between the wires, thereby improving the electrical characteristics and reliability of the device. It is an object of the present invention to provide a method for manufacturing a fine pattern of a semiconductor device.
제1a도 내지 제1c도는 종래 기술에 따른 반도체 소자의 미세패턴 제조공정도.1A to 1C are fine pattern manufacturing process diagrams of a semiconductor device according to the prior art.
제2a도 내지 제2d도는 본 발명에 따른 반도체 소자의 미세패턴 제조공정도.2a to 2d is a micropattern manufacturing process diagram of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,20 : 반도체 기판 3,22 : 제 1 절연막1,20
5,24 : 감광막패턴 7,26 : 홈5,24
9,30 : 금속배선 28 : 제 2 절연막9,30 metal wiring 28: second insulating film
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 미세패턴 제조방법은In order to achieve the above object, a method of manufacturing a fine pattern of a semiconductor device according to the present invention
반도체 기판 상부에 제 1절연막과 감광막패턴을 형성하는 공정과,Forming a first insulating film and a photosensitive film pattern on the semiconductor substrate;
상기 감광막패턴을 마스크로 상기 제 1절연막을 식각하여 홈을 형성하는 공정과,Etching the first insulating layer using the photoresist pattern as a mask to form a groove;
상기 구조의 전표면에 제 2절연막을 형성하는 공정과,Forming a second insulating film on the entire surface of the structure;
상기 홈을 매립하는 금속배선을 형성하는 공정과,Forming a metal wiring to fill the groove;
에치-백 및 CMP공정으로 상기 제 2절연막이 노출될때 까지 연마하여 금속 배선패턴을 형성하는 공정을 포함하는 것을 특징으로 한다.And etching through the etch-back and CMP processes until the second insulating layer is exposed to form a metal wiring pattern.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 미세패턴 제조 방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명에 따른 반도체 소자의 미세패턴 제조공정도이다. 먼저, 반도체 기판(20) 상부에 일정 두께의 제 1절연막(22)과 감광막패턴(24)을 순차적으로 형성한다.2a to 2d is a process diagram of manufacturing a fine pattern of a semiconductor device according to the present invention. First, the first
여기서, 상기 제 1절연막(22)은 산화막, 질화막, 산화질화막, 실리케이트 유리질 중의 하나로 구성된다.Here, the first
다음, 상기 감광막패턴(24)을 마스크로 상기 제 1절연막(22)을 식각하여 일정깊이의 홈(26)을 형성한다.(제2a도 참조)Next, the first insulating
그 다음, 상기 구조의 전표면에 일정 두께의 제 2절연막(28)을 형성한다.Next, a second
여기서, 상기 제 2절연막(28)은 산화막, 질화막, 산화질화막, 실리케이트 유리질 중의 하나로 구성된다.Here, the second
이 때, 상기 제 2절연막(28)은 상기 홈(26)의 폭 보다 절반 이하의 두께로 형성한다.(제2b도 참조)At this time, the second
다음, 상기 홈(26)을 매립하는 일정 두께의 금속배선(30)을 형성한다.Next, a
여기서, 상기 금속배선(30)은 상기 감광막패턴(24)의 두께보다 작게 형성한다.(제2c도 참조)Here, the
그 다음, 에치-백(etch-back) 및 CMP공정으로 상기 제 2절연막(28)이 노출될때 까지 연마하여 금속배선(30)패턴을 형성한다.Next, the
이 때, 상기 금속배선(30)폭의 배선마스크가 허용하는 최소선폭 보다 작게 금속배선(30)패턴을 형성함으로써 배선간의 상호간섭, 커플링 등의 기생효과를 줄일수 있다.(제2d도 참조)At this time, by forming the
상기한 바와같이 본 발명에 따르면, 광마스크 및 기존 노광기술로 금속배선폭의 배선마스크가 허용하는 최소선폭 보다 작게 금속배선패턴을 형성함으로써 배선간의 상호간섭, 커플링 등의 기생효과를 줄여 소자의 전기적 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, by forming a metal wiring pattern smaller than the minimum line width allowed by the wiring mask of the metal wiring width by using the optical mask and the existing exposure technology, the parasitic effects such as mutual interference and coupling between the wirings are reduced. There is an advantage of improving electrical characteristics and reliability.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030223A KR100248356B1 (en) | 1997-06-30 | 1997-06-30 | Method for semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030223A KR100248356B1 (en) | 1997-06-30 | 1997-06-30 | Method for semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19990006001A KR19990006001A (en) | 1999-01-25 |
| KR100248356B1 true KR100248356B1 (en) | 2000-05-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970030223A KR100248356B1 (en) | 1997-06-30 | 1997-06-30 | Method for semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763538B1 (en) | 2006-08-29 | 2007-10-05 | 삼성전자주식회사 | Method of forming mask pattern and method of forming fine pattern using the same in a semiconductor device fabricating |
| WO2021230966A1 (en) * | 2020-05-12 | 2021-11-18 | Micron Technology, Inc. | Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features |
-
1997
- 1997-06-30 KR KR1019970030223A patent/KR100248356B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763538B1 (en) | 2006-08-29 | 2007-10-05 | 삼성전자주식회사 | Method of forming mask pattern and method of forming fine pattern using the same in a semiconductor device fabricating |
| WO2021230966A1 (en) * | 2020-05-12 | 2021-11-18 | Micron Technology, Inc. | Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features |
| US11600707B2 (en) | 2020-05-12 | 2023-03-07 | Micron Technology, Inc. | Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features |
| US11948984B2 (en) | 2020-05-12 | 2024-04-02 | Micron Technology, Inc. | Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990006001A (en) | 1999-01-25 |
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