JPH0178436U - - Google Patents
Info
- Publication number
- JPH0178436U JPH0178436U JP1987175612U JP17561287U JPH0178436U JP H0178436 U JPH0178436 U JP H0178436U JP 1987175612 U JP1987175612 U JP 1987175612U JP 17561287 U JP17561287 U JP 17561287U JP H0178436 U JPH0178436 U JP H0178436U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- digital signal
- analog
- input
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000203 mixture Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の具体的な回路構成を示す回路図
、第３図は本考案の他の実施例を示す回路図、第
４図はラダー型Ｄ／Ａコンバータの構成を示す回
路図、第５図は積分型Ｄ／Ａコンバータの構成を
示すブロツク図である。
主要部分の符号の説明、１１……第１のＤ／Ａ
変換部、１２……第２のＤ／Ａ変換部、１３……
混合器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the specific circuit configuration of FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a circuit diagram showing the configuration of a ladder type D/A converter. , FIG. 5 is a block diagram showing the configuration of an integral type D/A converter. Explanation of symbols of main parts, 11...1st D/A
Conversion section, 12... Second D/A conversion section, 13...
mixer.
Claims (1)
号に変換するＤ／Ａコンバータであつて、２組に
分割された前記デイジタル信号の各組の桁に対応
してそれぞれ設けられかつ互いに縦続接続された
一対のＤ／Ａ変換部からなり、上位のＤ／Ａ変換
部は入力デイジタル信号に対応したアナログ値及
びこれよりも最小分解能のレベルだけ高いアナロ
グ値の２つのアナログ値を出力とし、下位のＤ／
Ａ変換部は前記２つのアナログ値を入力デイジタ
ル信号に応じた比で混合して出力することを特徴
とするＤ／Ａコンバータ。 (2) 前記下位のＤ／Ａ変換部は、前記２つのア
ナログ値を２入力としかつ入力デイジタル信号に
応じて切換え制御される入力ビツト数に応じた数
のスイツチと、入力ビツト数に応じた数の差動ア
ンプからなり前記スイツチの各出力を混合する混
合器とからなることを特徴とする実用新案登録請
求の範囲第１項記載のＤ／Ａコンバータ。[Claims for Utility Model Registration] (1) A D/A converter for converting a multi-bit digital signal into an analog signal, which is divided into two sets, each of which is provided corresponding to each digit of the digital signal. The upper D/A converter converts two analog values, one corresponding to the input digital signal and the other analog value higher than this by the minimum resolution level. is the output, and the lower D/
A D/A converter, wherein the A converter mixes the two analog values at a ratio depending on the input digital signal and outputs the mixture. (2) The lower D/A converter has two inputs for the two analog values, and has a number of switches corresponding to the number of input bits whose switching is controlled according to the input digital signal, and a number of switches corresponding to the number of input bits. 2. The D/A converter according to claim 1, which is a utility model, and further comprises a mixer that includes several differential amplifiers and mixes the outputs of the switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987175612U JPH0178436U (en) | 1987-11-17 | 1987-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987175612U JPH0178436U (en) | 1987-11-17 | 1987-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0178436U true JPH0178436U (en) | 1989-05-26 |
Family
ID=31467397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987175612U Pending JPH0178436U (en) | 1987-11-17 | 1987-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0178436U (en) |
-
1987
- 1987-11-17 JP JP1987175612U patent/JPH0178436U/ja active Pending
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