JPH01768A - Method for manufacturing semiconductor devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION CObject of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor element using a direct bonding technique between semiconductor substrates.

(Prior Art) In power semiconductor devices and the like, as the rated voltage increases, it is necessary to further increase the specific resistance of epitaxial wafers formed by vapor phase growth. However, when a semiconductor substrate with a high impurity concentration is used, it is difficult to form a high resistance epitaxial layer thereon because of impurity contamination from the substrate. For example, it is very difficult to form an epitaxial wafer with an n''-n'''' junction in which the n-type layer has a resistance of 100 Ω·cIr1 or more.

In addition, in conductive modulation type MOS FET etc.
In some cases, an n+ type layer and an n- type layer are sequentially epitaxially grown on a p+ type substrate, but when such an epitaxial wafer is formed, impurity dispersion occurs at the p+-〇〇 junction interface. It is difficult to obtain desired bonding properties. A similar problem occurs when a high impurity concentration layer of the opposite conductivity type is formed within the high impurity concentration layer by a diffusion method.

(Problems to be Solved by the Invention) As described above, conventional epitaxial growth methods and diffusion methods have limitations in forming desired pn junction characteristics.

In view of these points, the present invention provides a semiconductor device in which device wafers are formed using direct bonding technology of semiconductor substrates, and device characteristics are improved by taking advantage of the short carrier life at the bonding interface. The purpose is to provide a manufacturing method for.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, first and second semiconductor substrates having mirror-polished surfaces are directly bonded and heat-treated in a clean atmosphere without the intervention of foreign matter. Then, a device wafer is formed. In this case, in the present invention, the first semiconductor substrate is a first conductivity type high impurity concentration substrate, the second semiconductor substrate is a second conductivity type high resistance substrate, and the impurities are transferred from the first substrate to the second substrate. The total amount of electrically active impurities per unit area is 1×10]3/cm2 to 2×1015/cI in the second substrate.
A feature is that a first conductivity type diffusion layer of II2 is formed.

(Function) When the second conductivity type diffusion layer formed on the second substrate side of the element wafer formed according to the present invention is used as an emitter, the emitter injection efficiency becomes a suitably low value. This is because there is a substrate bonding interface with a short carrier life immediately after the emitter bonding, and the total amount of impurities between the emitter bonding and this bonding interface is small.

Therefore, for example, when a conductivity modulation type MO8FET, GTO, etc. is constructed using the element wafer obtained according to the present invention,
By increasing the carrier life of the second substrate serving as a high-resistance base layer, high-speed switching operation becomes possible. Moreover, since the carrier life of this second substrate is long, the forward voltage drop of the element can be kept small.

Note that if the total amount of impurities in the first conductivity type diffusion layer diffused and formed on the second substrate side is smaller than 1×1o13/crII2,
This diffusion layer no longer functions effectively as an emitter layer.

Further, this diffusion layer needs to be thinner than or equal to the carrier diffusion length, and preferably has a side length of 6 μm or less. 1st. In order to reduce the carrier lifetime at the adhesion interface of the second substrate, it is desirable to disturb the lattice at the interface, and for this purpose it is sufficient to make the surface indices of both substrates different. Alternatively, it is also possible to utilize the property of thermally diffusing time killers and gathering them at interfaces.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to (C) show the conductivity modulation type MO3F according to the present invention.
This is a manufacturing process of an example applied to ET. Figure 1(a)
As shown in FIG. 2, a p÷ type Si substrate (first semiconductor substrate) 11 and an n- type Si substrate (second semiconductor substrate) 12, each mirror-polished, are prepared. The impurity concentration of the p-sized St substrate 11 is 2× 10”/cx3~5x 1019/
Let it be cm3.

A 2x dose of phosphorus is applied to the polished surface of the n-type Si substrate 12.
A shallow n+ diffusion layer 13 is formed by ion implantation with a thickness of 7 cm2.Also, the plane orientations of the inner substrates 11 and 12 are different.The polished surfaces of these substrates 11 and 12 are polished in a clean atmosphere. They are bonded and heat treated to form an integrated structure as shown in FIG. 1(b).

A specific method for directly bonding the substrates is, for example, as follows. First, the surfaces of the two substrates to be bonded have a surface roughness of 500
Mirror polished to Å or less. Depending on the surface condition of the substrate, the substrate is subjected to pre-treatments such as degreasing and stain film removal. This pretreatment includes, for example, H2O2+H2SO,
1 = Aqua regia boil-HF process. Thereafter, the substrate is washed with clean water for several minutes, and dehydrated by drying with a spinner at room temperature. This dehydration treatment is to remove excess moisture adsorbed on the mirror-polished surface, and it is important to avoid heating and drying at 100° C. or higher, which would evaporate most of the adsorbed moisture. Thereafter, the polished surfaces of both substrates are adhered to each other in a clean atmosphere of class 1 or lower, with substantially no foreign matter present, and heat treated at 200° C. or higher. In the case of a Si substrate, a preferable heat treatment temperature is 1000°C to 1200°C.

In this way, the two boards are integrated, as shown in Figure 1(b).
An integrated element uni 71 shown in FIG. At this time, after bonding, further heat treatment is performed if necessary to form a p-type diffusion layer 14 on the n-type Si substrate 12 side. The thickness of the p-type diffusion layer 14 from the adhesive interface 15 is approximately 6 μm or less, and the total amount of electrically active impurities per unit area is 1×10 13 /Cm 2
~2×1015/c1B2. More preferably, l
Xl0" to lXl0" 7cm2.

After this, as shown in FIG. 1(c), the n-type Si substrate 12
After polishing the sides to a predetermined thickness as necessary, a gate electrode 17 is formed via a gate insulating film 16, a p-type base layer 18 and an n÷-type source layer 19 are formed by diffusion,
Furthermore, a source electrode 20 and a drain electrode 21 are formed to complete the conductivity modulation type MO5FET.

According to this embodiment, unlike the case where an n medium layer and an n- type layer are sequentially grown on a p-type substrate by an epitaxial method, there is no impurity compensation and good characteristics can be obtained. The p-type diffusion layer 14 formed by diffusion from the p + -type substrate 11 acts as an emitter for injecting holes, causing conductivity modulation. If the heat treatment at the time of bonding the substrate or after that is insufficient, the total amount of impurities in this p-type diffusion layer 14 will be 1×1.
013/cr12 or less, and no conductive modulation occurs. Further, the upper limit of the total amount of impurities in the p-type diffusion layer 14 is set because if it is made larger than this, the emitter injection efficiency becomes too high and the switching speed becomes slow due to excessive accumulation of carriers. If the injection efficiency becomes too high, it may be possible to shorten the carrier lifetime by irradiating the carrier with an electron beam, but this will cause the following problems. That is, the turn-off time is shortened at room temperature, but at 125° C., for example, the turn-off time increases to three times that at 25° C. N small layer 13 formed in advance on the n-type Si substrate 12 side
remains at a predetermined thickness, and the total amount of electrically active impurities per unit area is 5×1013/CjlI2~1×1
015/Cm2.

As described above, according to this embodiment, by reducing the total amount of impurities in the p-type diffusion layer as an emitter that is diffused through the adhesive interface, the cooperative relationship between the switching speed and forward voltage drop of the device is improved. becomes. In other words, even elements with the same switching speed have p! If the total amount of impurities in the 42 diffusion layer 14 is large, the lifetime of the n-type substrate 12 must be shortened.
can have a sufficiently high resistance to provide a long lifetime and a low forward voltage drop.

2(a) to 2(c) show the manufacturing process of a conductivity modulation type MO3FET according to another embodiment of the present invention.
It is shown in correspondence with c). In this embodiment, a phosphorus ion implantation layer 13' is formed on the n-type Si substrate 12 side, and the bonding process is started without performing heat treatment to activate the impurity. The conditions for forming the ion implantation layer 13' are, for example, an acceleration voltage of 40k.
eV.

The dose is m2 x 1015/C112. The rest is the same as in the previous embodiment. The impurities in the ion-implanted layer 13' are activated in a heat treatment process at about 1100° C. after bonding the substrates, and an n-type medium layer 13 is formed as in the previous embodiment, and a p-type layer is formed at a predetermined depth from the adhesive interface 15. 14 is formed on the n-type Si substrate 12 side.

In the method of this embodiment, the p-type small Si substrate 11 has a specific resistance in the range of 0.01 to 0.05 Ω·a, and the thickness of the p-type layer 14 which is diffused and formed on the n-type St substrate 12 side after the substrates are integrated. It is preferable to set the conditions so that the thickness is in the range of 3 to 7 μm. , their supporting data will be explained below.

FIG. 3 shows the thickness xj of the p-type layer 14 and the collector
The relationship between the emitter voltage VCE is shown. The board used is
The p-type St substrate 11 has a specific resistance of 0.0.15 Ωcm, and the nIC2Si substrate 12 has a specific resistance of 62.5 Ωcm.The measurement conditions are a gate voltage Va=15V and a collector current IC-25A. It can be seen that conductive modulation is not observed when xj<3 μm, and that xj≧3 μm is necessary in order to obtain vc and ≦4V, which are effective in terms of characteristics.

Next, the device obtained in this example was irradiated with an electron beam to increase the speed. V,: The maximum irradiation amount that satisfies E≦4V is 1, and the electron beam irradiation amount is 0.0.5.160.
11.5, the relationship between the switching speed (fall time) tr of the element and VCE is shown in FIG. Further, FIG. 5 shows the range in which preferable device characteristics can be obtained based on the relationship between the electron beam irradiation amount and xj. The upper limit of the shaded range in FIG. 5 is the upper limit for satisfying tr≦0.9 μSQQ required for device characteristics, and the lower limit indicates that conductive modulation does not occur below this. From these results, it can be seen that the upper limit of xj is approximately 7 μm.

FIG. 6 shows the results of determining the withstand voltage of the element obtained by varying the specific resistance of the p-sized Si substrate 11 by Δ-1. This result shows that when the resistivity is less than 0.01 Ω·cm, the withstand voltage is extremely reduced.

This is because if the specific resistance of the p-sized Si substrate 11 is too small,
This is because the thickness of the p-type layer 14 increases, and the n-type medium layer 13 for suppressing the extension of the depletion layer is substantially eliminated. Also, if the specific resistance is greater than 0.05Ω・cm, p
It becomes difficult to obtain the necessary thickness for the mold layer 14.

In each of the above embodiments, the p-type layer 14 was formed by diffusion from the p-small Si substrate 11. Boron ion implantation for the p-type layer 14 may be performed in advance on the n-type 5iJJ plate 12 side.

The present invention is based on the conductivity modulation type MO3 shown in each of the above embodiments.
The present invention is not limited to FETs, and can be applied to other elements. For example, a structural example when applied to a GTO is shown in FIG. To briefly explain the manufacturing process, pms i board 31
and n-type Si substrate 32 are directly bonded together in the same manner as in the above embodiment to form an integrated structure. At this time, if necessary, further heat treatment is applied after bonding to remove impurities from the p-type substrate 31.
A p-type diffusion layer 33 is formed by diffusing to the type substrate 32 side.

After this, a p-type base layer 35. An n-type emitter layer 36 is formed, and a cathode electrode 37. A gate electrode 38 and an anode electrode 39 are formed.

In this embodiment as well, the p-type diffusion layer 33 on the adhesive interface 34
By setting the total amount of impurities in the same range as in the previous example, the same effects as in the previous example can be obtained.

In addition, in order to reduce the lifetime of the interface, it is also possible to thermally diffuse a lifetime killer such as gold and utilize the property that it gathers at the adhesive interface.

[Effects of the Invention] As described above, according to the present invention, when forming an element wafer using direct bonding technology of substrates, the carrier lifetime of the adhesive interface is low, and By operating the diffusion layer formed on the high-resistance substrate side as an emitter and regulating the total amount of impurities in the diffusion layer of the four elements within a predetermined range, it is possible to achieve excellent device characteristics that cannot be obtained with conventional methods. .

[Brief explanation of drawings]

FIGS. 1(a) to 1(c) are diagrams showing the manufacturing process of a conductivity modulation type MOSFET according to an embodiment of the present invention, and FIGS. 2(a) to 2(c)
(c) is a diagram showing the manufacturing process of a conductivity modulation type MO3FET according to another example, FIG. 3 is a diagram showing the relationship between the p-type layer thickness and the collector-emitter voltage of the device obtained by that example, The diagrams are the same (Figure 5 is a diagram showing the relationship between collector-emitter voltage and switching speed, Figure 5 is a diagram showing the range where favorable device characteristics can be obtained in the relationship between electron beam irradiation amount and p-type layer thickness, and Figure 6 is a diagram showing the relationship between collector-emitter voltage and switching speed. The figure also shows the relationship between the specific resistance of the p-sized St substrate and the withstand voltage of the resulting device, and Fig. 7 is a diagram showing the GTO according to another example. semiconductor substrate), 12
... n-type Si substrate (second semiconductor substrate), 13...
・N-type diffusion layer, 13'...n-type impurity ion implantation layer,
14...p-type diffusion layer, 15...adhesive interface, 16...
・Gate insulating film, 17...gate electrode, 18...p
Type base layer, 19... N-type emitter layer, 20... Source electrode, 21... Drain electrode, 31... P-type Si substrate, 32... N- type Si substrate, 33...・p-type diffusion layer, 34... adhesive interface, 35..., p-type base layer, 36... n-type emitter layer, 37... cathode electrode, 38... gate electrode, 39... anode electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 1] Figure 2 -am)

Claims (1)

[Scope of Claims] (1) A first semiconductor substrate of a first conductivity type and having a high impurity concentration and having a mirror-polished surface; and a second semiconductor substrate of a second conductivity type and having a high resistance and having a mirror-polished surface. In the method for manufacturing a semiconductor device, the method includes a step of bonding polished surfaces together in a clean atmosphere without intervening foreign substances, and heat-treating and integrating the second semiconductor from the first semiconductor substrate through the adhesive interface. By diffusing impurities into the substrate, the total amount of electrically active impurities per unit area is 1×10^1^3/cm^2~2
A method for manufacturing a semiconductor device, characterized in that a first conductivity type diffusion layer of x10^1^5/cm^2 is formed and a pn junction is formed on the second semiconductor substrate side (2) The thickness of the 1-conductivity type diffusion layer from the adhesive interface is 6
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has a diameter of μm or less. (3) A second conductivity type diffusion layer is formed in advance on the side of the second semiconductor substrate to be bonded to the first semiconductor substrate, and the first conductivity type is diffused by impurity diffusion from the first semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the layer is formed so that a portion of the second conductivity type diffusion layer remains. (4) The total amount of electrically active impurities per unit area of the second conductivity type diffusion layer left on the second semiconductor substrate side is 5×
10^1^3 to 1 x 10^1^5/cm^2. The method for manufacturing a semiconductor device according to claim 3. (5) The method of manufacturing a semiconductor device according to claim 1, wherein the first and second semiconductor substrates have different surface indices or are subjected to a time killer thermal diffusion treatment. (6) An ion implantation layer of a second conductivity type impurity is formed in advance on the side of the second semiconductor substrate to be bonded to the first semiconductor substrate, and after bonding both substrates without heat treatment, heat treatment is performed. , the first conductivity type diffusion layer formed by impurity diffusion from the first semiconductor substrate is formed such that a part of the diffusion layer obtained by activating the second conductivity type impurity remains. A method for manufacturing the semiconductor device described above. (7) The first semiconductor substrate has a specific resistance of 0.01 to 0.05 Ωcm, and after bonding, the second semiconductor substrate
7. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductivity type diffusion layer formed on the semiconductor substrate side has a thickness of 3 to 7 μm from the adhesive interface.