JPH0172728U

JPH0172728U -

Info

Publication number: JPH0172728U
Application number: JP1987169378U
Authority: JP
Priority date: 1987-11-04
Filing date: 1987-11-04
Publication date: 1989-05-16

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は第１図に示す各部の波形図、第３図は従
来の一例を示すブロツク図、第４図は第３図の各
部の波形図、第５図は従来の他の例を示すブロツ
ク図、第６図は第５図の各部の波形図である。１……電圧比較器、２……カツトオフ周波数可
変ローパスフイルタ、３……カウンタ、４……レ
ベル調整器。 FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a waveform diagram of each part shown in Fig. 1, Fig. 3 is a block diagram showing a conventional example, Fig. 4 is a waveform diagram of each part of Fig. 3, and Fig. 5 is another conventional example. The block diagram, FIG. 6, is a waveform diagram of each part of FIG. 5. 1...Voltage comparator, 2...Cut-off frequency variable low-pass filter, 3...Counter, 4...Level adjuster.

Claims

[Scope of utility model registration request]

a voltage comparator that connects a signal to be binarized to a first input terminal and outputs a binary signal; and a voltage comparator that inputs the signal to be binarized and applies an integral signal to a second input terminal of the voltage comparator. A binarization circuit comprising: a variable cut-off frequency low-pass filter that inputs the binarized signal and connects an output pulse counted down to a cut-off frequency control terminal of the variable cut-off frequency low-pass filter.